CN101662280A - 集成电路及锁相环电路 - Google Patents
集成电路及锁相环电路 Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1206—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification
- H03B5/1212—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair
- H03B5/1215—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device using multiple transistors for amplification the amplifier comprising a pair of transistors, wherein an output terminal of each being connected to an input terminal of the other, e.g. a cross coupled pair the current source or degeneration circuit being in common to both transistors of the pair, e.g. a cross-coupled long-tailed pair
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- H—ELECTRICITY
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- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1228—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device the amplifier comprising one or more field effect transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
- H03B5/12—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device
- H03B5/1237—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator
- H03B5/124—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance
- H03B5/1243—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance active element in amplifier being semiconductor device comprising means for varying the frequency of the generator the means comprising a voltage dependent capacitance the means comprising voltage variable capacitance diodes
Abstract
本发明提供一种集成电路与锁相环电路,上述集成电路包含:偏压电路,产生第一偏压电压与第二偏压电压;LC共振电路,产生具有振荡频率的振荡信号;以及电流模式逻辑分频器,接至偏压电路与LC共振电路,由第一偏压电压与第二偏压电压偏压,接收振荡信号,以产生具有输出频率的输出信号,输出频率具有振荡频率的比率,其中振荡信号包含AC与DC成分,电流模式逻辑分频器接收AC成分以决定注入频率并重新使用DC成分,来提供末端电流以决定电流模式逻辑分频器的固有频率,且输出频率由注入频率与固有频率决定。本发明的集成电路因需要较少电容,能够占据较少电路面积并降低制造成本。
Description
技术领域
本发明大体是有关于高速通信,更具体地,是关于一种高速通信中使用的压控振荡器(voltage controlled oscillator)与锁相环电路。
背景技术
对于例如电脑、通信装置、RF IC技术以及高频时钟的应用来说,近年来高速数据传送的需要逐渐增长。高速压控振荡器与分频器(frequency divider)是电脑与通信应用普遍采用以进行例如频率合成,升频及降频操作的必要构造模块。举例来说,由分频器所实施的预分频器(prescaler)是锁相环电路(Phase-Locked Loop,PLL)内的重要组件之一(如图1所示),其广泛被作为无线接收器的频率合成器来应用。RF/微波的PLL中普遍使用静态或动态数字分频器。它们具有架构简单、带宽大与较佳的过程变化(process variations)稳定性。可是,随着无线操作的频率超过了低GHz范围,数字分频器的功率消耗成为一个问题。换句话说,数字分频器要达到功率要求越来越难,特别是对低功耗的移动应用更具挑战。而且,由于大量功率消耗,高速数字分频器还可能引起显著的噪音损害。
压控振荡器一般利用电感与电容库(inductors and capacitor bank)来形成共振网络(resonance network),并产生高频振荡信号。一般地,IC中电感与电容库占据比其它电路更大的电路面积,导致IC电路尺寸更大,因此提高了制造成本。
因此,需要更高功效且更小电路尺寸的压控振荡器与分频器。
发明内容
因此,本发明提供一种新的集成电路与锁相环电路。
本发明提供一种集成电路,包含:偏压电路,产生第一偏压电压与第二偏压电压;LC共振电路,产生具有振荡频率的振荡信号;以及电流模式逻辑分频器,接至偏压电路与LC共振电路,由第一偏压电压与第二偏压电压偏压,接收振荡信号,以产生具有输出频率的输出信号,输出频率具有振荡频率的比率,其中振荡信号包含AC与DC成分,电流模式逻辑分频器接收AC成分以决定注入频率并重复使用DC成分,来提供末端电流以决定电流模式逻辑分频器的固有频率,且输出频率由注入频率与固有频率决定。
本发明另提供一种锁相环电路,包含:鉴相器,侦测参考信号与输出信号的相位差信号;LC共振电路,耦接至上述鉴相器,接收上述相位差信号以产生具有振荡频率的振荡信号;偏压电路,产生第一偏压电压与第二偏压电压;以及电流模式逻辑分频器,耦接至偏压电路与LC共振电路,由第一偏压电压与第二偏压电压偏压,接收振荡信号以产生具有振荡频率的比率的输出频率的输出信号,其中振荡信号包含AC与DC成分,电流模式逻辑分频器接收AC成分以决定注入频率并重复使用DC成分,来提供末端电流以决定电流模式逻辑分频器的固有频率,且输出频率由注入频率与固有频率决定。
本发明的集成电路因需要较少电容,能够占据较少电路面积并降低制造成本。
附图说明
图1显示锁相环电路的示例方框示意图。
图2显示根据本发明的示例压控振荡器与CML分频器的方框示意图。
具体实施方式
在说明书及权利要求书当中使用了某些词汇来称呼特定的元件。本领域的技术人员应可理解,硬件制造商可能会用不同的名词来称呼同一个元件。本说明书及权利要求书并不以名称的差异来作为区分元件的方式,而是以元件在功能上的差异来作为区分的准则。在通篇说明书及权利要求书当中所提及的“包含”是开放式的用语,故应解释成“包含但不限定于”。此外,“耦接”一词在此是包含任何直接及间接的电气连接手段。因此,若文中描述第一装置耦接于第二装置,则代表第一装置可直接电气连接于第二装置,或通过其它装置或连接手段间接地电气连接到第二装置。
图1显示锁相环电路的示例方框示意图,其包含在回路中耦接的鉴相器100,环路滤波器102,压控振荡器104,以及分频器106。
压控振荡器104可为LC共振器(LC resonator),其产生振荡信号SVCO。分频器106将振荡信号SVCO的频率除一个因子(例如除2),来产生输出信号SOUT。分频器106可为利用差分架构的电流模式逻辑(Current Mode Logic,CML)分频器。如图1所应用的电路的压控振荡器104需要较少的电容,于是减少了LC共振器内的电容库的电路面积与制造成本。
图2显示根据本发明的示例压控振荡器与CML分频器的方框示意图,其包含偏压电路20,LC共振器22,CML分频器24,CML缓冲器26与去耦电路28。偏压电路20耦接至LC共振器22与CML分频器24,且两者都耦接至CML缓冲器26,接着耦接至去耦电路28。
偏压电路20包含电流源Ibias,晶体管M200,以及偏压电阻R200至R204,用于提供偏压电流给CML分频器24。电流源Ibias与晶体管M200提供电流镜偏压,以建立R200至R204的偏压电压。偏压电压依据电流要求可为相同或不同。
LC共振器22是LC库振荡器(LC tank resonator),其于振荡频率产生振荡信号。LC共振器22包含PMOS交叉耦接的晶体管对M220,电容C220与C222,变容二极管V220与V222,电容库C224以及电感L220。PMOS交叉耦接的晶体管对M220提供负的gm来消除LC共振器22内的阻性能量消耗。LC共振器22可更包含NMOS交叉耦接的晶体管对(图未示),以作为PMOS交叉耦接晶体管的替换。实际上,PMOS交叉耦接的晶体管对提供比NMOS交叉耦接的晶体管对更佳的闪烁噪音性能(flicker noise performance)。振荡信号的振荡频率可由控制电压Vtune来细调。振荡信号包含差分信号对CLK+与CLK-。振荡信号包含AC与DC成分,CML分频器24接收AC成分来决定注入频率(injected frequency),并重复利用DC成分来提供末端电流(tailcurrent),以决定CML分频器的固有频率(natural frequency),以及CML分频器24的输出频率由注入频率与固有频率决定。电感L220的中间抽头(center tap)通过电容对C280耦接至CML分频器24,如此其中所有DC电流经过CML分频器24流向接地端。因为偏压电路20控制由晶体管M241至M247产生偏压电流,CML分频器24内的DC总量与LC共振器22内的DC总量相等,都由偏压电路20限制。其中晶体管M241、M243、M245及M247可被称作末端晶体管,其接收偏压电压及振荡信号,以产生末端电流给差分晶体管对M240、M242、M244及M246来产生差分输出信号VVCO1与VVCO2。
CML分频器24AC耦接至LC共振器22,以通过电容C240与C242接收差分振荡信号CLK+与CLK-。CML分频器24是由CML电路将差分输出信号VVCO1与VVCO2反馈给输入端构成的两个D触发器。CML分频器24操作于由振荡信号对CLK+与CLK-决定的跟踪与锁存模式(track and latch mode)。于跟踪模式中,信号CLK+为“高”,而信号CLK-为“低”,晶体管M24 1开启且晶体管M243关闭,使得晶体管对M240的漏电流跟踪输出电压对VVCO1及VVCO2,如此通过电阻R240与R242来建立输出漏极电压。于锁存模式中,信号CLK+为“低”,而信号CLK-为“高”,晶体管M241关闭而晶体管M243开启,使得锁存晶体管对M242锁存之前晶体管级M240的输出漏极电压。同样,当信号CLK+为“低”且信号CLK-为“高”时,晶体管M245开启而晶体管M247关闭,使得晶体管对M244跟踪晶体管对M240的输出漏极电压,并通过电阻R244及R246建立输出漏极电压。当CLK+信号为“高”且CLK-信号为“低”时,晶体管M245关闭而晶体管M247开启,使得晶体管对M246锁存之前晶体管级M244的输出漏极电压并输出输出电压对。电阻R240至R246不仅用来决定输出信号对的固有频率,也用来隔离输出信号对与LC共振器22。
当振荡信号具有零振幅时,CML分频器24产生输出信号对,其具有由负载电阻R240至R246、小信号跨导gm,以及栅极与接线电容(gate and wire capacitance)决定的固有频率,即所谓的自振荡(self-oscillation)。当振荡信号的幅度增加时,CML分频器24会经历“注入锁相效应(injection locking effect)”。因为输入振荡信号CLK+与CLK-的注入,CML分频器24表现为具有从固有频率获得的输出信号的输出时钟频率的振荡器,以于输入振荡信号CLK+与CLK-的半速率频率振荡,表现为除2的分频器。
CML缓冲器26操作时有小幅电压摆动(small voltage swings),2VTHN的峰-峰差分模式,其中电压VTHN为NMOS晶体管260至266的阈值电压,如此提供高速振荡输出SOUT1与SOUT2。去耦电路2 8耦接至电感L220的中间抽头,从LC共振器22提供AC信号的虚拟接地端。
本发明虽用较佳实施方式说明如上,然而其并非用来限定本发明的范围,任何本领域中技术人员,在不脱离本发明的精神和范围内,做的任何更动与改变,都在本发明的保护范围内,具体以权利要求界定的范围为准。
Claims (17)
1.一种集成电路,包含:
偏压电路,产生第一偏压电压与第二偏压电压;
LC共振电路,产生具有振荡频率的振荡信号;以及
电流模式逻辑分频器,耦接至上述偏压电路与上述LC共振电路,由上述第一偏压电压与上述第二偏压电压偏压,并接收上述振荡信号,以产生具有输出频率的输出信号,上述输出频率是上述振荡频率的一比值,
其中上述振荡信号包含AC与DC成分,上述电流模式逻辑分频器接收上述AC成分以决定注入频率并重复使用上述DC成分,来提供末端电流以决定上述电流模式逻辑分频器的固有频率,且上述输出频率由上述注入频率与上述固有频率决定。
2.如权利要求1所述的集成电路,其特征在于,更包含去耦电容,耦接至上述电感的中间,提供AC信号一个虚拟接地。
3.如权利要求1所述的集成电路,其特征在于,上述偏压电路包含:
电流源,提供偏压电流;
偏压晶体管,耦接至上述电流源与上述电流模式逻辑分频器,配置为电流镜,以接收上述偏压电流并产生镜像电流;以及
第一偏压电阻与第二偏压电阻,耦接至上述偏压晶体管与上述电流模式逻辑分频器,接收上述镜像电流来建立上述第一偏压电压与上述第二偏压电压。
4.如权利要求1所述的集成电路,其特征在于,上述电流模式逻辑分频器包含第一电容与第二电容,耦接来自LC共振电路的上述振荡信号至上述电流模式逻辑分频器。
5.如权利要求1所述的集成电路,其特征在于,上述电流模式逻辑分频器包含:
第一末端晶体管,接收上述第一偏压电压与上述振荡信号,以产生第一末端电流;
第二末端晶体管,接收上述第二偏压电压与上述振荡信号,以产生第二末端电流;以及
第一差分晶体管对与第二差分晶体管对,分别耦接至上述LC共振电路与上述第一末端晶体管之间及上述LC共振电路与上述第二末端晶体管之间,接收上述第一末端电流与上述第二末端电流以产生上述输出信号。
6.如权利要求5所述的集成电路,其特征在于,当上述第一末端晶体管开启而上述第二末端晶体管关闭时,上述第一差分晶体管对跟踪上述输出信号,并建立输出漏极电压;当上述第一末端晶体管关闭而上述第二末端晶体管开启时,上述第二差分晶体管对锁存上述第一差分晶体管对的上述输出漏极电压。
7.如权利要求5所述的集成电路,其特征在于,上述电流模式逻辑分频器更包含:
第三末端晶体管,接收上述第一偏压电压与上述振荡信号;
第四末端晶体管,接收上述第二偏压电压与上述振荡信号;以及
第三差分晶体管对与第四差分晶体管对,分别耦接至上述LC共振电路与上述第三末端晶体管之间及上述LC共振电路与上述第四末端晶体管之间,
其中当上述第三末端晶体管开启而上述第四末端晶体管关闭时,上述第三差分晶体管对跟踪上述第一差分晶体管对的输出漏极电压;当上述第三末端晶体管关闭而上述第四末端晶体管开启时,上述第四差分晶体管对锁存上述第三差分晶体管对的上述输出漏极电压。
8.如权利要求1所述的集成电路,其特征在于,更包含电流模式逻辑缓冲器,耦接至上述电流模式逻辑分频器。
9.如权利要求1所述的集成电路,其特征在于,上述振荡信号与上述输出信号为差分信号。
10.一种锁相环电路,包含:
鉴相器,侦测参考信号与输出信号的相位差信号;
LC共振电路,耦接至上述鉴相器,接收上述相位差信号以产生具有振荡频率的振荡信号;
偏压电路,产生第一偏压电压与第二偏压电压;以及
电流模式逻辑分频器,耦接至上述偏压电路与上述LC共振电路,由上述第一偏压电压与上述第二偏压电压偏压,接收上述振荡信号以产生具有上述振荡频率的比率的输出频率的上述输出信号,
其中上述振荡信号包含AC与DC成分,上述电流模式逻辑分频器接收上述AC成分以决定注入频率并重复使用上述DC成分,来提供末端电流以决定上述电流模式逻辑分频器的固有频率,且上述输出频率由上述注入频率与上述固有频率决定。
11.如权利要求10所述的锁相环电路,其特征在于,更包含去耦电容,耦接至上述电感的中间,给AC信号提供一个虚拟接地。
12.如权利要求10所述的锁相环电路,其特征在于,上述偏压电路包含:
电流源,提供偏压电流;
偏压晶体管,耦接至上述电流源与上述电流模式逻辑分频器,被配置为电流镜,以接收上述偏压电流并产生镜像电流;以及
第一偏压电阻与第二偏压电阻,耦接至上述偏压晶体管与上述电流模式逻辑分频器,接收上述镜像电流来建立上述第一偏压电压与上述第二偏压电压。
13.如权利要求10所述的锁相环电路,其特征在于,上述电流模式逻辑分频器包含第一电容与第二电容,耦接来自LC共振电路的上述振荡信号至上述电流模式逻辑分频器。
14.如权利要求10所述的锁相环电路,其特征在于,上述电流模式逻辑分频器包含:
第一末端晶体管,接收上述第一偏压电压与上述振荡信号,以产生第一末端电流;
第二末端晶体管,接收上述第二偏压电压与上述振荡信号,以产生第二末端电流;以及
第一差分晶体管对与第二差分晶体管对,分别耦接至上述LC共振电路与上述第一末段晶体管之间及上述LC共振电路与上述第二末端晶体管之间,接收上述第一末端电流与上述第二末端电流以产生上述输出信号。
15.如权利要求14所述的锁相环电路,其特征在于,当上述第一末端晶体管开启而上述第二末端晶体管关闭时,上述第一差分晶体管对跟踪上述输出信号,并建立输出漏极电压;当上述第一末端晶体管关闭而上述第二末端晶体管开启时,上述第二差分晶体管对锁存上述第一差分晶体管对的上述输出漏极电压。
16.如权利要求14所述的锁相环电路,其特征在于,上述电流模式逻辑分频器更包含:
第三末端晶体管,接收上述第一偏压电压与上述振荡信号;
第四末端晶体管,接收上述第二偏压电压与上述振荡信号;以及
第三差分晶体管对与第四差分晶体管对,分别耦接至上述LC共振电路与上述第三末端晶体管之间及上述LC共振电路与上述第四末端晶体管之间,
其中当上述第三末端晶体管开启而上述第四末端晶体管关闭时,上述第三差分晶体管对跟踪上述第一差分晶体管对的输出漏极电压;当上述第三末端晶体管关闭而上述第四末端晶体管开启时,上述第四差分晶体管对锁存上述第三差分晶体管对的上述输出漏极电压。
17.如权利要求10所述的锁相环电路,其特征在于,更包含电流模式逻辑缓冲器,耦接至上述电流模式逻辑分频器。
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CN102843130A (zh) * | 2012-09-18 | 2012-12-26 | 北京大学 | 基于cml逻辑的相位检测器 |
CN104105293A (zh) * | 2013-04-15 | 2014-10-15 | 阮树成 | 直流低压电源四推挽注锁功率合成无极灯组 |
CN104641560A (zh) * | 2012-09-12 | 2015-05-20 | 德克萨斯仪器股份有限公司 | Rf逻辑分频器 |
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JP5174055B2 (ja) * | 2010-02-02 | 2013-04-03 | 株式会社半導体理工学研究センター | 広帯域発振回路 |
TW201136147A (en) * | 2010-04-01 | 2011-10-16 | Nat Univ Tsing Hua | Integrated circuit capable of repeatedly using currents |
US8203374B2 (en) * | 2010-05-06 | 2012-06-19 | Aeroflex Colorado Springs Inc. | Electrically tunable continuous-time circuit and method for compensating a polynomial voltage-dependent characteristic of capacitance |
WO2013141837A1 (en) * | 2012-03-19 | 2013-09-26 | Taner Sumesaglam | Self-biased oscillator |
ITRM20130467A1 (it) * | 2013-08-08 | 2015-02-06 | Stefano Perticaroli | Ota based differential harmonic class c vco |
US10020777B2 (en) * | 2015-10-22 | 2018-07-10 | Mediatek Inc. | Voltage controlled oscillator and control method thereof |
US9800249B2 (en) * | 2016-02-23 | 2017-10-24 | Qualcomm Incorporated | Current steering phase control for CML circuits |
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JP3488180B2 (ja) * | 2000-05-30 | 2004-01-19 | 松下電器産業株式会社 | 周波数シンセサイザ |
US6762624B2 (en) * | 2002-09-03 | 2004-07-13 | Agilent Technologies, Inc. | Current mode logic family with bias current compensation |
US6765448B2 (en) * | 2002-10-30 | 2004-07-20 | Qualcomm Incorporated | Self-biased VCO |
US7196551B2 (en) * | 2004-05-28 | 2007-03-27 | Lattice Semiconductor Corporation | Current mode logic buffer |
KR100810501B1 (ko) * | 2005-12-08 | 2008-03-07 | 한국전자통신연구원 | 광대역 다중모드 주파수 합성기 및 가변 분주기 |
US7605667B2 (en) * | 2007-04-26 | 2009-10-20 | Mediatek Inc. | Frequency synthesizer with a harmonic locked phase/frequency detector |
TW200906066A (en) * | 2007-07-19 | 2009-02-01 | Uniband Electronic Corp | CMOS cross-coupled differential voltage controlled oscillator |
US8970272B2 (en) * | 2008-05-15 | 2015-03-03 | Qualcomm Incorporated | High-speed low-power latches |
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CN104641560A (zh) * | 2012-09-12 | 2015-05-20 | 德克萨斯仪器股份有限公司 | Rf逻辑分频器 |
CN104641560B (zh) * | 2012-09-12 | 2017-12-12 | 德克萨斯仪器股份有限公司 | Rf逻辑分频器 |
CN102843130A (zh) * | 2012-09-18 | 2012-12-26 | 北京大学 | 基于cml逻辑的相位检测器 |
CN102843130B (zh) * | 2012-09-18 | 2014-10-08 | 北京大学 | 基于cml逻辑的相位检测器 |
CN104105293A (zh) * | 2013-04-15 | 2014-10-15 | 阮树成 | 直流低压电源四推挽注锁功率合成无极灯组 |
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US20100052803A1 (en) | 2010-03-04 |
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