CN101661921B - Metal routing layer structure in microwave monolithic integrated circuit and preparation method thereof - Google Patents
Metal routing layer structure in microwave monolithic integrated circuit and preparation method thereof Download PDFInfo
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- CN101661921B CN101661921B CN2009103075189A CN200910307518A CN101661921B CN 101661921 B CN101661921 B CN 101661921B CN 2009103075189 A CN2009103075189 A CN 2009103075189A CN 200910307518 A CN200910307518 A CN 200910307518A CN 101661921 B CN101661921 B CN 101661921B
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Abstract
The invention relates to a metal routing layer structure in a microwave monolithic integrated circuit (MMIC) and a preparation method thereof, and belongs to the technical field of integrated circuits. The metal routing layer structure is arranged between a first Si3N4 layer and a second Si3N4 layer, and comprises a first Ti layer, a Ni layer which is arranged on the first Ti layer, a second Ti layer which is arranged on the Ni layer, an Au layer which is arranged on the second Ti layer, and a third Ti layer which is arranged on the Au layer. Metal Ni in the metal routing layer structure can protect the routing layer and the part above through an ICP etched substrate, thus a back hole process of the MMIC can be carried out smoothly, the upper layer metal and the lower layer metal Ti of the structure improves adhesive capacity with an Si3N4 dielectric layer and performance of capacitors, and produces little influence of the whole structure on the capacitance value. Introduction of the metal Ti above the metal Ni layer can solve the problem of poor adhesive capacity between the metal Ni and the metal Au.
Description
Technical field
The present invention relates to a kind of metal routing layer structure and preparation method thereof, relate in particular to metal routing layer structure in a kind of microwave monolithic integrated circuit and preparation method thereof, belong to technical field of integrated circuits.
Background technology
Microwave monolithic integrated circuit (Monolithic Microwave Integrated Circuit, MMIC) in, need can dispel the heat better like this, and can improve the ground connection performance of source end with the source end through dorsal pore ground connection; The element that in MMIC, has simultaneously a lot of parallelly connected ground connection makes that the series inductance that causes through the dorsal pore grounded metal is very little, and is also smaller to the influence of high-frequency circuit, so the dorsal pore technology is one of requisite critical process in the MMIC circuit technology flow process.
In the process of making dorsal pore; Require back side plated metal just to touch the wiring layer metal and then could form good being electrically connected; Promptly to remove wiring layer to the part between the metal layer on back; Usually use the method for plasma etching (ICP), etching is removed wiring layer to all material between the metal layer on back, so just must introduce the barrier layer and make the wiring metal layer can not be destroyed; The whole etchings of material in the middle of will guaranteeing simultaneously are clean, in the wiring layer metal, introduce metal Ni through the experiment proof and can accomplish barrier effect.
Traditional wiring layer metal structure titanium/gold and titanium/gold/titanium etc. all are to can be used in the metal wiring layer that normal circuit is made, but the dorsal pore technology that can not be used for making microwave monolithic integrated circuit.
Summary of the invention
The present invention is directed to and have the deficiency that metal wiring layer can not be used for making microwave monolithic integrated circuit dorsal pore technology now, a kind of metal routing layer structure that is applicable to making dorsal pore technology in microwave monolithic integrated circuit and preparation method thereof is provided.
The technical scheme that the present invention solves the problems of the technologies described above is following: the metal routing layer structure in a kind of microwave monolithic integrated circuit; Be arranged between a Si3N4 layer and the 2nd Si3N4 layer, comprise a Ti layer, be arranged on Ni layer on the said Ti layer, be arranged on the 2nd Ti layer on the said Ni layer, be arranged on the Au layer on said the 2nd Ti layer and be arranged on the 3rd Ti layer on the said Au layer.
Further, the thickness of the first layer of Si3N4 2000
~ 4000
; said second Si3N4 layer has a thickness of 500
~ 2000
; said first Ti layer has a thickness of 200
~ 400
; said Ni layer thickness of 500
~ 1000
; said second Ti layer thickness of 200
~ 400
; wherein the thickness of the Au layer 2000
~ 4000
; said third Ti layer thickness of 200
~ 400
The present invention also provides a kind of technical scheme that solves the problems of the technologies described above following: the preparation method of the metal routing layer structure in a kind of microwave monolithic integrated circuit may further comprise the steps:
Step 10: behind spin coating photoresist on the 2nd Si3N4 layer, and through photoetching, development formation metal line layer pattern;
Step 20: the method through electron beam evaporation forms a Ti layer, Ni layer, the 2nd Ti layer, Au layer and the 3rd Ti layer successively;
Step 30: the Ti layer on the photoresist, Ni layer, the 2nd Ti layer, Au layer and the 3rd Ti layer are peeled off.
Further, the thickness of the first layer of Si3N4 2000
~ 4000
; said second Si3N4 layer has a thickness of 500
~ 2000
; said first Ti layer has a thickness of 200
~ 400
; said Ni layer thickness of 500
~ 1000
; said second Ti layer thickness of 200
~ 400
; wherein the thickness of the Au layer 2000
~ 4000
; said third Ti layer thickness of 200
~ 400
The invention has the beneficial effects as follows: the metal Ni in the metal routing layer structure of the present invention is after passing through the ICP etched substrate; Can protect wiring layer to reach with top; Make MMIC dorsal pore technology to carry out smoothly; And the Ti of double layer of metal up and down in this metal routing layer structure has improved the adhesiveness with the Si3N4 dielectric layer; Improved the performance of electric capacity, whole metal routing layer structure is little to the influence of capacitance simultaneously, and the introducing of layer of metal Ti can improve the bad problem of adhesiveness of metal Ni and metal A u above the metal Ni; The preparation method of whole metal routing layer structure can accomplish through disposable evaporated metal, and method is simple, and very big effect has been played in the realization of MMIC technology.
Description of drawings
Fig. 1 has the metal routing layer structure sketch map of dorsal pore for the present invention;
Fig. 2 is a stereoscan photograph of dorsal pore in the metal routing layer structure of the present invention;
Fig. 3 is another stereoscan photograph of dorsal pore in the metal routing layer structure of the present invention;
Fig. 4 does not adopt the dorsal pore break-through sketch map of Ni metal level for metal routing layer structure of the present invention;
The pad sketch map that comes off when Fig. 5 directly contacts with the Au metal level for Ni metal level in the metal routing layer structure of the present invention;
Fig. 6 is the capacitance curve synoptic diagram of Ti/Au/Ti metal routing layer structure of the present invention;
Fig. 7 is the capacitance curve synoptic diagram of Ti/Ni/Ti/Au/Ti metal routing layer structure of the present invention;
Fig. 8 is the quality factor curve synoptic diagram of the electric capacity of Ti/Au/Ti metal routing layer structure of the present invention;
Fig. 9 is the quality factor curve synoptic diagram of the electric capacity of Ti/Ni/Ti/Au/Ti metal routing layer structure of the present invention;
Figure 10 is the voltage endurance curve synoptic diagram of electric capacity in Ti/Au/Ti metal routing layer structure of the present invention and the Ti/Ni/Ti/Au/Ti metal routing layer structure;
Figure 11 is a metal routing layer structure preparation method flow chart of the present invention.
Embodiment
Below in conjunction with accompanying drawing principle of the present invention and characteristic are described, institute gives an actual example and only is used to explain the present invention, is not to be used to limit scope of the present invention.
Fig. 1 has the metal routing layer structure sketch map of dorsal pore for the present invention.As shown in Figure 1, the metal routing layer structure in the said microwave monolithic integrated circuit is arranged on a Si
3N
4Layer the 106 and the 2nd Si
3N
4Between the layer 107, comprise a Ti layer 101, be arranged on Ni layer 102 on the said Ti layer 101, be arranged on the 2nd Ti layer 103 on the said Ni layer 102, be arranged on the Au layer 104 on said the 2nd Ti layer 103 and be arranged on the 3rd Ti layer 105 on the said Au layer 104.Said the 2nd Si
3N
4 Layer 107 is arranged on the SiC substrate 108.A said Si
3N
4Layer is disposed with furling plating Ti/Au109 and electrodeposited coating Au110 on 106, said electrodeposited coating Au110 be arranged on furling plating Ti/Au109 above, and do not have the differentiation of strictness between the furling plating Ti/Au109.Through etching formation dorsal pore zone 111, form furling plating Ti/Au in said dorsal pore zone 111 on the said SiC substrate 108, and then electroplate formation electrodeposited coating Au through electron beam evaporation.
The thickness of said SiC substrate 108 is about 100um; A said Si
3N
4The thickness of layer 106 is 2500
Said the 2nd Si
3N
4The thickness of layer 107 is 1000
The thickness of a said Ti layer 101 is 200
The thickness of said Ni layer 102 is 600
The thickness of said the 2nd Ti layer 103 is 200
The thickness of said Au layer 104 is 4000
The thickness of said the 3rd Ti layer 105 is 200
Fig. 2 is a stereoscan photograph of dorsal pore in the metal routing layer structure of the present invention, and Fig. 3 is another stereoscan photograph of dorsal pore in the metal routing layer structure of the present invention.Like Fig. 2 and shown in Figure 3, Fig. 2 is the vertical view of dorsal pore, and the metal in the hole is followed successively by electrodeposited coating Au, furling plating Ti/Au, metal routing layer structure Ti/Ni/Ti/Au/Ti; Fig. 3 is the sectional view of dorsal pore; The degree of depth of dorsal pore is about substrate thickness, and promptly the degree of depth of etching is about about 100um, and as can beappreciated from fig. 3 electrodeposited coating metal in the back side has formed good the connection with the wiring layer metal; Dorsal pore has also reached the diameter and the degree of depth that require; The existence that metal Ni is described has produced barrier effect to etching gas, has protected the wiring layer metal, has accomplished dorsal pore technology smoothly.
Fig. 4 does not adopt the dorsal pore break-through sketch map of Ni metal level for metal routing layer structure of the present invention, the pad sketch map that comes off when Fig. 5 directly contacts with the Au metal level for Ni metal level in the metal routing layer structure of the present invention.Fig. 4 is that an electric capacity 206 is connected in the circuit through microstrip line 201 and air bridges 202; All Ranges among the figure all is plated metals 204 except 205; If in wiring layer, do not adopt the Ni metal level; Then when carrying out the ICP etching, etchant gas can directly erode the metal section and part of wiring layer and destruction front pad PAD203 through the dorsal pore zone, like the sign black circles 205 of dorsal pore break-through among Fig. 4; Have only that to have adopted the Ni metal level be that normal dorsal pore technology can be realized in the barrier layer, accomplish the electrical communication of back side electrodeposited coating metal and wiring layer metal through dorsal pore.Fig. 5 is that an electric capacity 301 is connected in the circuit through microstrip line 302 and air bridges 305, test PAD303, and dorsal pore ground connection PAD is 304; All Ranges is plated metal 306 except 307 among the figure; The wiring layer metal structure that adopts Ni/Au directly to contact, and between Ni and Au, do not add Ti, the metal of testing in this case on the PAD303 comes off easily; Like test PAD identification division 307 among Fig. 5; Especially connect through spun gold or when contact with high frequency probe whole PAD be prone to started, after the centre adds Ti, can avoid the generation of this situation, so the middle Ti metal level of Ni, Au is essential.
Fig. 6 is the capacitance curve synoptic diagram of Ti/Au/Ti metal routing layer structure of the present invention, and Fig. 7 is the capacitance curve synoptic diagram of Ti/Ni/Ti/Au/Ti metal routing layer structure of the present invention.Fig. 6 adopts the capacitance curve synoptic diagram of Ti/Au/Ti metal routing layer structure when showing capacity area and being 120 * 120um2; Capacitance is 1.857pF under 8GHz; Fig. 7 shows the capacitance curve that adopts new metal routing layer structure Ti/Ni/Ti/Au/Ti when capacity area is 120 * 120um2; Capacitance is 1.917pF under 8GHz; Can see that it is not very big that the metal routing layer structure that makes new advances changes on capacitance values, and capacitance there is not very great fluctuation process in 110MHz～15.1GHz scope, does not have influence on the application of electric capacity.
Fig. 8 is the quality factor curve synoptic diagram of the electric capacity of Ti/Au/Ti metal routing layer structure of the present invention, and Fig. 9 is the quality factor curve synoptic diagram of the electric capacity of Ti/Ni/Ti/Au/Ti metal routing layer structure of the present invention.The electric capacity that Fig. 8 shows the Ti/Au/Ti metal routing layer structure is 9.137 in the quality factor of 8GHz; Ti/Ni/Ti/Au/Ti metal routing layer structure shown in Fig. 9 is 19.5 in the quality factor of 8GHz; The electric capacity quality factor of 2GHz～10GHz frequency range Ti/Ni/Ti/Au/Ti metal routing layer structure with respect to Fig. 8 in the electric capacity quality factor of Ti/Au/Ti metal routing layer structure different liftings is all arranged, improved capacitance characteristic.
Figure 10 is the voltage endurance curve synoptic diagram of electric capacity in Ti/Au/Ti metal routing layer structure of the present invention and the Ti/Ni/Ti/Au/Ti metal routing layer structure.Shown in figure 10; Depress in same electrical; The Ti/Ni/Ti/Au/Ti metal routing layer structure is littler than the direct current electric leakage of Ti/Au/Ti metal routing layer structure, and the Ti/Ni/Ti/Au/Ti metal routing layer structure is more high pressure resistant than Ti/Au/Ti metal routing layer structure, has improved capacitive property.
Adding metal Ni when accomplishing selective etch in traditional wiring layer metal (titanium/gold, titanium/gold/titanium etc.), considering has Si below the wiring layer
3N
4Dielectric layer is in order to improve metal Ni and Si
3N
4The adhesiveness of dielectric layer must be at metal Ni and Si
3N
4Add layer of metal Ti between the dielectric layer again, Si is also arranged on wiring layer simultaneously
3N
4Dielectric layer also need add the contact performance that layer of metal Ti improves dielectric surface, makes the capacitance characteristic of in the MMIC circuit, making to improve.Simultaneously; Because metal A u is arranged above the metal Ni; When finding that in experiment metal Ni directly contacts with metal A u, metal Ni is easy to come off, and the contact performance of metal Ti and metal Ni, metal A u is all good; Intermediate demand has layer of metal Ti to improve the contact performance of metal Ni and metal A u like this, has so just formed metal routing layer structure of the present invention: Ti/Ni/Ti/Au/Ti.
The problem on barrier layer when the introducing of metal Ni has solved the etching dorsal pore in the metal routing layer structure of the present invention has avoided the material above the wiring layer metal to be corroded; The lower metal Ti of metal Ni has improved metal Ni and Si
3N
4The contact performance of dielectric layer has also promoted the performance and stability of electric capacity in conjunction with the metal Ti of the superiors, and very little to the change of capacitance; The upper strata metal Ti of metal Ni has been improved the adhesion property between metal Ni and the metal A u; Make metal routing layer structure more firm; Peel off and metal PAD carries out metal difficult drop-off when connecting, facts have proved that whole metal wiring layer new construction has good electrical characteristic.
Figure 11 is a metal routing layer structure preparation method flow chart of the present invention.Shown in figure 11, the preparation method of the metal routing layer structure in the said microwave monolithic integrated circuit may further comprise the steps:
Step 10: at the 2nd Si
3N
4On the layer 107 behind the spin coating photoresist, and through photoetching, formation metal line layer pattern develops.
Step 20: the method through electron beam evaporation forms the metal routing layer structure of a Ti layer 101, Ni layer 102, the 2nd Ti layer 103, Au layer 104 and the 3rd Ti layer 105 successively, also forms the electric capacity bottom crown simultaneously.
Just do not form said metal routing layer structure in the said step 20 through evaporated metal on the metal line layer pattern that forms at photoresist, also need be at said the 2nd Si
3N
4Layer does not have the wiring layer metal structure of place the formations needs of the metal line layer pattern that photoresist forms on 107.The power of said electron beam evaporation is about 700W, and the chamber vacuum degree is 8.5 * 10
-6Mbar, cavity temperature are 30 ℃, and general evaporation time is about 30min.Followed by evaporation to a thickness of 200
the first Ti layer 101 having a thickness of 600
Ni layer 102; thickness of 200
the second Ti layer 103 having a thickness of 4000
Au layer 104 and a thickness of 200
Third Ti layer 105.
Step 30: the Ti layer 101 on the photoresist, Ni layer 102, the 2nd Ti layer 103, Au layer 104 and the 3rd Ti layer 105 are peeled off.
The metal routing layer structure of the Ti layer 101 on the photoresist, Ni layer 102, the 2nd Ti layer 103, Au layer 104 and the 3rd Ti layer 105 soaked about 30min with acetone carry out peeling off of metal, clean up with acetone and ethanol successively then and get final product.And at the 2nd Si
3N
4There is not the position of photoresist will form metal routing layer structure of the present invention on the layer 107.
It is no problem that the manufacture craft of traditional wiring metal structure is applied in the making of wiring layer of normal circuit; Yet in MMIC technology,, will there be some problems like this: at first owing to will the source end of all tube cores be carried out being connected with the parallelly connected element that needs commonly; When accomplishing dorsal pore technology; After metal level etched away SiC through ICP, can't stop the etching air-flow will be corroded, and will further corrode top secondary media Si like this
3N
4With furling plating and electrodeposited coating metal, will destroy the connection of the entire circuit path of accomplishing through back side plated metal behind the dorsal pore, so must in metal wiring layer, add Ni metal completion stopping and then protect upper layer of material to air-flow; Secondly, needing above the Ni metal also need introduce the adhesiveness that metal Ti is improved Ni and Au with being connected with its Au that can not form good contact, all is Si at the wiring layer upper and lower surface simultaneously
3N
4Dielectric layer; And the adhesion between Ni and the dielectric layer is bad, need to increase one deck Ti and form excellent contact, and the introducing of this two-layer Ti has improved the characteristic of the electric capacity of making among connection and the MMIC of whole metal level; So adopting this new wiring layer metal structure is considerable for the technological process of whole M MIC; Not only satisfied the smooth completion of dorsal pore technology, and taken into account the correlation properties requirement of electric capacity, the connectedness of entire circuit has also been played a good role.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being done, is equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (4)
1. the metal routing layer structure in the microwave monolithic integrated circuit, said metal routing layer structure is arranged on a Si
3N
4Layer (106) and the 2nd Si
3N
4Between the layer (107); It is characterized in that said metal routing layer structure comprises a Ti layer (101), be arranged on Ni layer (102) on the said Ti layer (101), be arranged on the 2nd Ti layer (103) on the said Ni layer (102), be arranged on the Au layer (104) on said the 2nd Ti layer (103) and be arranged on the 3rd Ti layer (105) on the said Au layer (104).
2. the metal routing layer structure in the microwave monolithic integrated circuit according to claim 1 is characterized in that, a said Si
3N
4The thickness of layer (106) is 2000
～4000
Said the 2nd Si
3N
4The thickness of layer (107) is 500
～2000
The thickness of a said Ti layer (101) is 200
～400
The thickness of said Ni layer (102) is 500
～1000
The thickness of said the 2nd Ti layer (103) is 200
～400
The thickness of said Au layer (104) is 2000
～4000
The thickness of said the 3rd Ti layer (105) is 200
～400
3. the preparation method of the metal routing layer structure in the microwave monolithic integrated circuit is characterized in that said preparation method may further comprise the steps:
Step 10: at the 2nd Si
3N
4After layer (107) is gone up the spin coating photoresist, and through photoetching, development formation metal line layer pattern;
Step 20: the method through electron beam evaporation forms a Ti layer (101), Ni layer (102), the 2nd Ti layer (103), Au layer (104) and the 3rd Ti layer (105) successively;
Step 30: the Ti layer (101) on the photoresist, Ni layer (102), the 2nd Ti layer (103), Au layer (104) and the 3rd Ti layer (105) are peeled off the formation metal routing layer structure;
Step 40: on said metal routing layer structure, form a Si
3N
4Layer (106).
4. the preparation method of the metal routing layer structure in the microwave monolithic integrated circuit according to claim 3 is characterized in that, a said Si
3N
4The thickness of layer (106) is 2000
～4000
Said the 2nd Si
3N
4The thickness of layer (107) is 500
～2000
The thickness of a said Ti layer (101) is 200
～400
The thickness of said Ni layer (102) is 500
～1000
The thickness of said the 2nd Ti layer (103) is 200
～400
The thickness of said Au layer (104) is 2000
～4000
The thickness of said the 3rd Ti layer (105) is 200
～400
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| CN2009103075189A CN101661921B (en) | 2009-09-23 | 2009-09-23 | Metal routing layer structure in microwave monolithic integrated circuit and preparation method thereof |
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|---|---|---|---|
| CN2009103075189A CN101661921B (en) | 2009-09-23 | 2009-09-23 | Metal routing layer structure in microwave monolithic integrated circuit and preparation method thereof |
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| CN101661921B true CN101661921B (en) | 2012-04-18 |
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|---|---|---|---|---|
| CN102456611B (en) * | 2010-10-20 | 2014-09-17 | 中国科学院微电子研究所 | Method for controlling shape of cross section of back hole |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5156998A (en) * | 1991-09-30 | 1992-10-20 | Hughes Aircraft Company | Bonding of integrated circuit chip to carrier using gold/tin eutectic alloy and refractory metal barrier layer to block migration of tin through via holes |
| CN1373514A (en) * | 2001-03-03 | 2002-10-09 | 三星电子株式会社 | Single chip microwave integrated circuit and mfg. method thereof |
-
2009
- 2009-09-23 CN CN2009103075189A patent/CN101661921B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5156998A (en) * | 1991-09-30 | 1992-10-20 | Hughes Aircraft Company | Bonding of integrated circuit chip to carrier using gold/tin eutectic alloy and refractory metal barrier layer to block migration of tin through via holes |
| CN1373514A (en) * | 2001-03-03 | 2002-10-09 | 三星电子株式会社 | Single chip microwave integrated circuit and mfg. method thereof |
Non-Patent Citations (1)
| Title |
|---|
| Jae-Sung Rieh et al..X- and Ku-Band Amplifiers Based on Si/SiGe HBT"s and Micromachined Lumped Components.《IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES》.1998,第46卷(第5期),第685页至第692页. * |
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