CN101656594B - Method and equipment for branch path synchronization of deletion type convolution code - Google Patents
Method and equipment for branch path synchronization of deletion type convolution code Download PDFInfo
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Abstract
The present invention relates to a method for branch path synchronization of deletion type convolution codes, including steps: setting a plurality of synchronization detection modes, wherein each synchronization detection mode corresponds with a combination form; calculating a measurement value of the current detection mode; implementing a coarse synchronization judge according to the synchronization measurement value and a synchronization threshold value to provide a coarse synchronization indication, wherein the synchronization threshold value is set according to the current mode and a number of traversing all the detection modes; implementing a fine synchronization judge based on the coarse synchronization direction, so as to provide a fine synchronization direction. By setting a dynamic threshold value, the invention improves a synchronizing speed and synchronization capability with a high signal-to-noise ration, and avoids wrong synchronizations and unable synchronizations; a fiducial mechanism is capable of reinforcing the stability of a synchronizing system; apart from code rate and deletion position detections, the invention is also used to detect synthetically phase ambiguity and frequency spectrum reversion, etc.
Description
Technical field
The present invention relates to the communications field, relate in particular to a kind of branch road method for synchronous and equipment thereof of deletion type convolution code.
Background technology
Convolution code is a kind of channel error correction coding commonly used in the communication system.On the one hand, under the identical condition of encoder complexity, the performance of convolution code is superior to block code.On the other hand, convolution code has strict Algebraic Structure unlike the block code that kind, and it can't connect error-correcting performance and code structure regularly, therefore mostly utilizes the good sign indicating number in the computer search convolution code.Yet, owing to practical good sign indicating number is less,, can on the coding codeword basis of female sign indicating number, delete some code word bits wherein regularly, thereby obtain the deletion type convolution code of different code checks in order to adapt to the message transmission demand.Every kind of code check of deletion type convolution code is corresponding a kind of deletion pattern, wherein, the deletion pattern preferably determines through performance simulation.
Fig. 1 is that a kind of code check is the structured flowchart of female code coder of 1/2.
In European digital video-frequency broadcast standard DVB-S and DVB-T, chnnel coding has adopted the mode of outer sign indicating number and ISN cascade, and wherein ISN is exactly (2,1,7) convolution code, and its production is (171,133).
Fig. 2 is according to the code check of the mother's sign indicating number of Fig. 1 and deletion type subcode, deletion pattern and the schematic of the transmission relation after also string is changed.
Female sign indicating number code check shown in Fig. 1 is 1/2, on its basis, can obtain code check and be respectively 4 kinds of deletion type subcodes of 2/3,3/4,5/6 and 7/8, wherein, code check, deletion pattern and and the string conversion after the corresponding relation of transfer sequence see Fig. 2 for details.
The Viterbi decoding of soft-decision mode is adopted in the decoding of convolution code usually.In the decoding of deletion type convolution code, also need fill irrelevant bit in the position of deletion code word bits, make code stream be reduced to the code check of female sign indicating number, be convenient to unified decoding.Therefore, judge the delete position in the code stream, make each bit correspond to correct branch road, become a major issue in the Viterbi decoding, wherein, the I/Q that said delete position is promptly imported props up the position in the corresponding deletion of the circuit-switched data pattern.Have only and realized that branch road is synchronous, could correctly separate deletion and decoding.
U.S. Pat 7161995B1 " Method and Apparatus for ViterbiSynchronization " discloses a kind of method for synchronous of Viterbi decoding.In this scheme, the output result of Viterbi decoding is recoded, and the hard decision data synchronization delay before will deciphering.Through the hard decision data after heavier coding result and the delay, can obtain error amount.Simultaneously, also adopted a clock counter, latched the cumulative errors value of a count cycle, perhaps latched the count value that reaches certain cumulative errors value, with latched value and threshold ratio, can judge whether decoding unit gets into synchronous regime.
In such scheme, threshold value has directly determined synchronous judgement, so it chooses performance impact very big.Under different signal to noise ratio conditions, the differing greatly of cumulative errors value, and adopt the method underaction of a fixed threshold in the scheme, threshold value is too little then maybe all the time can't be synchronous, possibly be synchronous with asynchronous erroneous judgement too greatly then.
Publication number is the one Chinese patent application of CN101247203A, and denomination of invention is " detecting the apparatus and method of punctured position in the punctured convolutional codes ".This patent application has proposed a kind of method that from deletion type convolution code, detects the delete position that need not to recode.This method is 0 principle according to the particular verified polynomial value of coded bit stream, utilize ball bearing made using such as delayer and XOR gate calculate code streams each maybe the delete position the check polynomial value, thereby the corresponding delete position of minimum value is judged as sync bit.
Such scheme has only been explained the method that from certain known code check, detects the delete position, and how explanation possibly not detect code check the code check from multiple.In fact, multiple maybe code check the time when existing, also need set a threshold value and judge whether that synchronously this relates to the inflexible problem of fixed threshold every kind of code check.In addition, this scheme can't some phase ambiguity of comprehensive detection or situation such as reversing spectrum.
Therefore, the branch road method for synchronous and the equipment thereof that need a kind of deletion type convolution code that can overcome the above problems.
Summary of the invention
The present invention proposes a kind of branch road method for synchronous and equipment thereof of the deletion type convolution code that can address the above problem.
In first aspect; The invention provides a kind of branch road method for synchronous of deletion type convolution code; Comprise: the various combination form according to code check and delete position is provided with a plurality of synchronous detecting patterns; Code check, the delete position of output under the preamble pattern, wherein, the corresponding a kind of combining form of each synchronous detecting pattern; I/Q circuit-switched data according to said code check, said delete position and said deletion type convolution code is calculated the synchronization metric value; Carry out thick synchronous judgment according to said synchronization metric value and synchronization threshold, provide thick indication synchronously, wherein, said synchronization threshold is to be provided with according to said code check and traversal number of times, and said traversal number of times is the number of times of all synchronous detecting patterns of traversal; On the basis of said thick indication synchronously, carry out smart synchronous judgment based on the decode results of said I/Q circuit-switched data, provide smart indication synchronously.
Preferably, the step that synchronization threshold is set comprises: the bound and threshold value increase step-length of setting synchronization threshold according to the code check under the present mode; Traveling through in the synchronous detecting for the first time, said synchronization threshold is set to said lower limit; All do not have to realize synchronously if travel through all synchronous detecting patterns, then increase synchronization threshold according to said threshold value increase step-length and said traversal number of times; If realize synchronously, then indication synchronously is set to the said upper limit with zero clearing of said traversal number of times and said synchronization threshold based on said essence.
Preferably, said combination also comprises phase ambiguity and reversing spectrum, and said method also comprises: the situation according to said phase ambiguity under the present mode and said reversing spectrum is recovered back output to said I/Q circuit-switched data.
Preferably, said thick synchronizing step and said smart synchronizing step give the step-out indication, be used to reset said thick synchronizing step and said smart synchronizing step, and be used for indicating next synchronous detecting pattern that switches to.
In second aspect; The invention provides a kind of branch road synchronizer of deletion type convolution code, comprise that mode setting unit, synchronization metric value computing unit, thick lock unit, smart lock unit and synchronization threshold are provided with the unit, wherein: mode setting unit; Be used for a plurality of synchronous detecting patterns being set according to the various combination form of code check and delete position; Code check, the delete position of output under the preamble pattern, wherein, the corresponding a kind of combining form of each synchronous detecting pattern; Synchronization metric value computing unit is used for calculating the synchronization metric value according to the I/Q circuit-switched data of said code check, said delete position and said deletion type convolution code; Thick lock unit; Be used for carrying out thick synchronous judgment according to said synchronization metric value and synchronization threshold; Provide thick indication synchronously; Wherein, said synchronization threshold be said synchronization threshold be provided with the unit according to said code check with the traversal number of times be provided with, said traversal number of times be the traversal all synchronous detecting patterns number of times; Smart lock unit is used for carrying out smart synchronous judgment on the said thick basis of indication synchronously based on the decode results of said I/Q circuit-switched data, provides smart indication synchronously.
The present invention has accelerated synchronizing speed through setting dynamic threshold under the high s/n ratio condition, under the low signal-to-noise ratio condition, improved synchronizing capacity, has avoided false sync and situation that can't be synchronous; Put letter mechanism and can strengthen the stability of synchro system; Except code check and delete position detection, situation such as all right comprehensive detection phase ambiguity and reversing spectrum.
Description of drawings
Below with reference to accompanying drawings specific embodiments of the present invention is explained in more detail, in the accompanying drawings:
Fig. 1 is that a kind of code check is the structured flowchart of female code coder of 1/2;
Fig. 2 is according to the code check of the mother's sign indicating number of Fig. 1 and deletion type subcode, deletion pattern and the schematic of the transmission relation after also string is changed;
Fig. 3 is the structured flowchart of the branch road synchronizer of deletion type convolution code according to an embodiment of the invention;
Fig. 4 is the structured flowchart according to a kind of synchronization metric value computing unit of Fig. 3;
Fig. 5 is the structured flowchart according to the another kind of synchronization metric value computing unit of Fig. 3;
Fig. 6 is the structured flowchart according to a kind of thick lock unit of Fig. 3;
Fig. 7 is the structured flowchart according to a kind of smart lock unit based on data-frame sync of Fig. 3;
Fig. 8 is the structured flowchart according to a kind of smart lock unit based on Bit Error Ratio Measurement of Fig. 3.
Embodiment
Fig. 3 is the structured flowchart of the branch road synchronizer of deletion type convolution code according to an embodiment of the invention.
As shown in Figure 3, this branch road synchronizer comprises: mode setting unit, synchronization metric value computing unit, thick lock unit, smart lock unit and synchronization threshold are provided with the unit.
Mode setting unit is provided with multiple synchronous detecting pattern, and synchronization metric value computing unit and synchronization threshold are provided with the unit respectively according to going out the synchronization metric value when the preamble mode computation, and the bound of synchronization threshold is set.Thick lock unit carries out thick synchronous judgment according to synchronization metric value and synchronization threshold lower limit, as then carrying out smart synchronous judgment synchronously; Restart to carry out synchronous detecting like asynchronous next synchronous detecting pattern that then switches to.If in smart synchronous judgment, judge to get into synchronous regime, then export synchronous indicating signal, synchronization threshold is set to the upper limit to guarantee stability simultaneously.All do not have then to increase synchronization threshold synchronously if travel through all synchronous detecting patterns, restart synchronous detecting.Synchronization threshold progressively increases along with traveling through all synchronous detecting pattern number of times on the basis of its lower limit, till getting into smart synchronous regime.
Describe the concrete course of work of branch road synchronizer below in detail.
Mode setting unit is provided with the synchronous detecting pattern; Different code rate, delete position, phase ambiguity and reversing spectrum situation can be combined as multiple possible synchronous detecting pattern; The branch road synchronization scenario need travel through detection in order to all possible pattern, till accomplishing synchronously.
Should be pointed out that the deletion type convolution code that possibly adopt various code rate in the system, possibly have a plurality of delete positions under every kind of code check.For example in the DVB-S standard, 1/2 code check has only a kind of possible delete position, and 2/3 code check has 3 kinds, and 3/4 code check has 2 kinds, and 5/6 code check has 3 kinds, and 7/8 code check has 4 kinds.
Should also be noted that because also possibly there is the problem of phase ambiguity in receiver in demodulating process, promptly the I/Q two paths of signals of input in fact possibly be (I, Q), (Q ,-I), (I ,-Q) or (Q, a kind of in I); The problem that also possibly have reversing spectrum in addition, at this moment also need add (Q, I), (I, Q), (Q ,-I) with (I ,-Q) these 4 kinds of possibilities; So adding the situation of phase ambiguity and reversing spectrum in the combination is the problem that phase ambiguity and reversing spectrum possibly occur in order to solve, also can be with the combination of code check and delete position as the synchronous detecting pattern.
Next, mode setting unit is recovered the I/Q road signal of importing by phase ambiguity under the preamble pattern and reversing spectrum situation, then it is offered synchronization metric value computing unit; Simultaneously, code check and the delete position that will work as the preamble pattern are imported synchronization metric value computing unit into, and will work as code check under the preamble pattern and import synchronization threshold into the unit is set.In addition, mode setting unit is also to traveling through time counting number, and imports it into synchronization threshold the unit is set, and wherein, the traversal number of times is the number of times of all synchronous detecting patterns of traversal.When receiving the final synchronous indicating signal that smart lock unit imports into, will travel through the number of times zero clearing so that after step-out, reset synchronization threshold.Behind the of-step signal that receives from thick lock unit or smart lock unit, mode setting unit switches to next synchronous detecting pattern.
Whether synchronous synchronization metric value computing unit calculate one according to the code check of setting and delete position and be used to judge metric, is referred to as the synchronization metric value, and imports it into thick lock unit.The synchronization metric value both can be the difference aggregate-value of hard decision result with the decoding back recodification code word of decoding input, also can be decoding input hard decision result's check polynomial value.The more little then synchronous possibility of synchronization metric value is big more, otherwise then nonsynchronous possibility is big more.
Thick lock unit carries out thick synchronous judgment according to synchronization metric value and synchronization threshold, synchronously the time, imports synchronous indicating signal into smart lock unit, indicates smart lock unit to carry out further smart synchronous judgment; When step-out, import the step-out index signal into smart lock unit and mode setting unit respectively, get into next synchronous detecting pattern so that reset respectively smart lock unit and notification mode are provided with the unit.
Though should be appreciated that slightly and can accelerate detection speed synchronously, under the low signal-to-noise ratio situation, the raising of synchronization threshold possibly cause the erroneous judgement of thick lock unit, so need smart lock unit whether on thick synchronous basis, further to judge exactly synchronously.
Smart lock unit carries out smart synchronous judgment according to the synchronous indicating signal of thick lock unit, so that confirm whether thick synchronous judged result is correct.
If the transmission data possess specific form, smart lock unit can carry out synchronous judgment according to data frame structure.For example, every frame of MPEG-2 code stream comprises 188 bytes, and every frame starts as sync byte with the 0x47 byte, in this case can be synchronous according to the synchronization character achieve frame in the data flow.
If before the convolutional encoding also cascade other channel encoders, smart lock unit can carry out synchronous judgment according to the Bit Error Ratio Measurement result of the back level decoder of cascade.
Get into smart synchronous regime if judge, then exporting final synchronous indicating signal, to have got into branch road with indication synchronous, and import this signal into synchronization threshold respectively unit and mode setting unit are set; If can't get into essence synchronously, import the step-out index signal into mode setting unit and thick lock unit respectively, so that being provided with the unit, notification mode gets into next the synchronous detecting pattern and the thick lock unit that resets.
Synchronization threshold is provided with the unit and dynamically arranges synchronization threshold, and imports it into thick lock unit.The size of this threshold value directly has influence on synchronous speed and accuracy.Threshold value is too small possibly to make thick lock unit judge by accident synchronously to asynchronous, thereby can't get into synchronous regime all the time; Threshold value is excessive then possibly make thick lock unit with asynchronous erroneous judgement for synchronously, need smartly further to judge synchronously, thereby reduce synchronous speed.Be provided with in the unit in synchronization threshold, every kind of code check has been set a synchronization threshold lower limit T
MinWith upper limit T
MaxTraveling through in the testing process for the first time, synchronization threshold is made as lower limit, i.e. T=T
MinIf it is not synchronous yet that traversal detects all patterns, then in traversal detection next time, increase synchronization threshold, up to reaching higher limit T
MaxTill.The step-length that threshold value increases can be made as
Thereby the relational expression that obtains synchronization threshold T and traversal frequency n does
In addition, when the synchronous indicating signal of smart lock unit is effective, current synchronization threshold directly is made as limit T
MaxTo guarantee stability, will travel through the number of times zero clearing simultaneously in case after step-out again from lower limit T
MinBegin to detect synchronously.
Fig. 4 is the structured flowchart according to a kind of synchronization metric value computing unit of Fig. 3.
As shown in Figure 4, be input as the soft information data of I/Q two-way that mode setting unit provides.On the one hand, the Viterbi decoding unit is accomplished and to be separated deletion and decoding, and with decode results once more convolutional encoding obtain the code word of recoding, import the recodification code word into comparator.On the other hand, the soft information data of I/Q two-way is carried out hard decision.Because Viterbi decoding exists decoding to postpone,, the hard decision result postpones to keep also importing the hard decision result who postpones into comparator synchronously with the recodification code word so also will passing through.At last, comparator with the recodification code word with postpone after the hard decision result compare by turn, accumulative total goes out difference bit number wherein and it is exported as the synchronization metric value.
Fig. 5 is the structured flowchart according to the another kind of synchronization metric value computing unit of Fig. 3.
As shown in Figure 5; The soft information of I/Q two-way to input is at first carried out hard decision; Go out the check polynomial value that each maybe place, delete position according to the specific polynomial computation of coded bit stream then, the accumulation result of the check polynomial value that will repeatedly calculate through accumulator is at last exported as the synchronization metric value.
Fig. 6 is the structured flowchart according to a kind of thick lock unit of Fig. 3.
As shown in Figure 6, thick lock unit comprises latch, cycle counter, comparator, decision unit.
Cycle counter produces a pulse signal and imports it into latch when count value reaches the count cycle.Latch latchs according to the synchronization metric value of this pulse signal with input, thereby obtains the synchronization metric value of a count cycle.Decision unit is judged synchronously or step-out according to the comparative result of synchronization metric value that latchs and synchronization threshold.Decision unit can adopt two confidence counter (not shown)s, and a generating and communicating advanced television and a step-out confidence counter are respectively applied for and judge synchronously and step-out.When synchronization metric value during less than synchronization threshold, generating and communicating advanced television adds 1 and the step-out confidence counter subtracts 1; When synchronization metric value during greater than synchronization threshold, generating and communicating advanced television subtracts 1 and the step-out confidence counter adds 1.When putting the letter count value synchronously when reaching a certain threshold value, judge to get into synchronous regime, provide synchronous indicating signal, the step-out that resets confidence counter; And put the letter count value when reaching a certain threshold value when step-out, judge to provide the step-out index signal, the reset synchronization confidence counter by synchronization failure.Should be appreciated that synchronous indicating signal and step-out index signal can be simultaneously not effectively.Synchronous indicating signal is transfused to smart lock unit, so that thick synchronized result is carried out further smart synchronous judgment; The step-out index signal is transfused to smart lock unit and mode setting unit, and also be used to reset smart lock unit and notification mode are provided with the unit and switch to next pattern.
Fig. 7 is the structured flowchart according to a kind of smart lock unit based on data-frame sync of Fig. 3.
As shown in Figure 7, it is the cycle decode results of convolution code to be carried out cycle count with the data frame length that smart lock unit adopts a location counter.When the synchronization character detecting unit receives the convolution code decode results, therefrom detect synchronization character and notify latch.The current count value of latches location counter.After this, when current count value equaled this and latchs count value, the synchronization character identifying unit judged whether the input data of current time are synchronization characters, and imports judged result into decision unit.Decision unit provides synchronous indicating signal and step-out index signal according to judged result, puts the letter method and is similar to thick decision unit in synchronously, repeats no more at this.
The structure that should be appreciated that the smart lock unit of Fig. 7 can combine the structure of Fig. 4 to realize.
Fig. 8 is the structured flowchart according to a kind of smart lock unit based on Bit Error Ratio Measurement of Fig. 3.
As shown in Figure 8, the error rate is further deciphered and added up to cascade decoder to the convolution code decode results.When the count value of cycle counter equals measurement period, latch the error rate and with preset threshold relatively.Decision unit judges whether synchronously according to comparative result, provides synchronous indicating signal and step-out index signal, puts the letter method and is similar to thick decision unit in synchronously equally, repeats no more at this.
The structure that should be appreciated that the smart lock unit of Fig. 8 can combine the structure of Fig. 4 to realize.
Yet; Those skilled in the art are readily appreciated that; If Fig. 7 and Fig. 8 realize with the structure that combines Fig. 5; Then the smart lock unit of Fig. 7 and Fig. 8 also need add a viterbi decoder, promptly carries out folding coding according to said code check and said delete position synchronously carrying out essence, to draw the convolution code decode results for carrying out smart synchronous judgment.
In sum, the present invention proposes a kind of branch road method for synchronous of deletion type convolution code decoding.At first draw the possible integrated mode of institute of code check, delete position, phase ambiguity, reversing spectrum etc., confirm traversal order.Preset a kind of pattern; Calculate the next measurement period of this pattern the synchronization metric value and with synchronization threshold relatively; The locking comparative result is judged synchronously thick, does not then detect next pattern synchronously, and is synchronous then continue smart synchronous judgement to confirm slightly synchronous result; If then explanation is slightly wrong synchronously synchronously can't essence, continues to detect next pattern.If it is synchronously smart that traversal still is unrealized for one time afterwards, then synchronization threshold is increased the traversal of carrying out a new round and detect.
The present invention has accelerated synchronizing speed through setting dynamic threshold under the high s/n ratio condition, under the low signal-to-noise ratio condition, improved synchronizing capacity, has avoided false sync and situation that can't be synchronous; Put letter mechanism and can strengthen the stability of synchro system; Except code check and delete position detection, situation such as all right comprehensive detection phase ambiguity and reversing spectrum.
The present invention can be applied in the communication system that has adopted convolution code.For example, European DVB DVB-S and DVB-T, and the communication system that adopts the J.83/B standard of ITU-T.
Obviously, under the prerequisite that does not depart from true spirit of the present invention and scope, the present invention described here can have many variations.Therefore, the change that all it will be apparent to those skilled in the art that all should be included within the scope that these claims contain.The present invention's scope required for protection is only limited described claims.
Claims (9)
1. the branch road method for synchronous of a deletion type convolution code comprises:
Various combination form according to code check and delete position is provided with a plurality of synchronous detecting patterns, code check, the delete position of output under the preamble pattern, wherein, the corresponding a kind of combining form of each synchronous detecting pattern;
I/Q circuit-switched data according to said code check, said delete position and said deletion type convolution code is calculated the synchronization metric value;
Carry out thick synchronous judgment according to said synchronization metric value and synchronization threshold, provide thick indication synchronously, wherein, said synchronization threshold is to be provided with according to said code check and traversal number of times, and said traversal number of times is the number of times of all synchronous detecting patterns of traversal;
On the basis of said thick indication synchronously, carry out smart synchronous judgment based on the decode results of said I/Q circuit-switched data, provide smart indication synchronously;
The said step that synchronization threshold is set comprises: bound and the threshold value of setting synchronization threshold according to the code check under the present mode increase step-length; Traveling through in the synchronous detecting for the first time, said synchronization threshold is set to said lower limit; All do not have to realize synchronously if travel through all synchronous detecting patterns, then increase synchronization threshold according to said threshold value increase step-length and said traversal number of times; If realize synchronously, then indication synchronously is set to the said upper limit with zero clearing of said traversal number of times and said synchronization threshold based on said essence.
2. method according to claim 1, wherein, said combination also comprises phase ambiguity and reversing spectrum, said method also comprises:
Situation according to said phase ambiguity under the present mode and said reversing spectrum is recovered back output to said I/Q circuit-switched data.
3. method according to claim 1, wherein, said thick synchronizing step and said smart synchronizing step give the step-out indication, be used to reset said thick synchronizing step and said smart synchronizing step, and be used for indicating next synchronous detecting pattern that switches to.
4. the branch road synchronizer of a deletion type convolution code comprises that mode setting unit, synchronization metric value computing unit, thick lock unit, smart lock unit and synchronization threshold are provided with the unit, wherein:
Mode setting unit is used for according to the various combination form of code check and delete position a plurality of synchronous detecting patterns being set, code check, the delete position of output under the preamble pattern, wherein, the corresponding a kind of combining form of each synchronous detecting pattern;
Synchronization metric value computing unit is used for calculating the synchronization metric value according to the I/Q circuit-switched data of said code check, said delete position and said deletion type convolution code;
Thick lock unit; Be used for carrying out thick synchronous judgment according to said synchronization metric value and synchronization threshold; Provide thick indication synchronously; Wherein, said synchronization threshold be said synchronization threshold be provided with the unit according to said code check with the traversal number of times be provided with, said traversal number of times be the traversal all synchronous detecting patterns number of times;
Smart lock unit is used for carrying out smart synchronous judgment on the said thick basis of indication synchronously based on the decode results of said I/Q circuit-switched data, provides smart indication synchronously;
Synchronization threshold is provided with the unit, is used for setting according to the code check under the present mode bound and the threshold value increase step-length of synchronization threshold; Traveling through in the synchronous detecting for the first time, said synchronization threshold is set to said lower limit; All do not have to realize synchronously if travel through all synchronous detecting patterns, then increase synchronization threshold according to said threshold value increase step-length and said traversal number of times; If realize synchronously, then indication synchronously is set to the said upper limit with zero clearing of said traversal number of times and said synchronization threshold based on said essence.
5. according to the equipment of claim 4, wherein, said synchronization metric value computing unit comprises viterbi decoder, convolution coder, comparator, difference value accumulator, hard decision unit, delay cell:
Viterbi decoder is used for according to said code check and said delete position the I/Q circuit-switched data being carried out Viterbi decoding, obtains decode results;
Convolution coder is used for said decode results is carried out convolutional encoding, obtains the convolutional encoding result;
Comparator is used for said convolutional encoding result and hard decision result are compared by turn, draws difference bit number wherein;
The difference value accumulator; Be used for accumulative total said difference bit number and with it as said synchronization metric value; Wherein, said hard decision result carries out hard decision by said hard decision unit to the soft information data in I/Q road before deciphering, and carries out synchronization delay by said delay cell then and obtains.
6. according to the equipment of claim 4, wherein, said synchronization metric value computing unit comprises hard decision unit, check polynomial value computing unit and accumulator:
The hard decision unit is used for the I/Q circuit-switched data of input is carried out hard decision, obtains the hard decision result;
Check polynomial value computing unit is used for calculating the check polynomial value of encoding code stream in each possibility delete position according to said code check, said delete position and said hard decision result;
Accumulator, be used for the verification polynomial value add up and with accumulation result as said synchronization metric value.
7. according to the equipment of claim 4, wherein, said smart lock unit comprises synchronization character detecting unit, synchronization character identifying unit, location counter, latch and decision unit:
The synchronization character detecting unit is used for detecting synchronization character in said decode results;
Latch is used to latch the current count value when detecting synchronization character, and said count value is to be the cycle said decode results to be carried out cycle count to obtain with the data frame length through said location counter;
The synchronization character identifying unit is used for when current count value equals the said count value that latchs, judging whether present input data is synchronization character;
Decision unit is used for carrying out confidence judgement according to judged result, provides said essence and indicates synchronously.
8. according to the equipment of claim 4, wherein, said smart lock unit comprises cascade decoder, Bit Error Ratio Measurement unit, counter, latch, comparator, decision unit:
Cascade decoder is used for said decode results is carried out cascade decoding, draws the cascade decode results;
The Bit Error Ratio Measurement unit is used for based on the cascade decode results statistics error rate;
Latch is used for when count value equals measurement period, latching the said error rate, and wherein, said count value is to be the cycle said decode results to be carried out cycle count to obtain with the data frame length;
Comparator is used for the said error rate and predetermined threshold value are compared;
Decision unit is used for carrying out confidence judgement according to said comparative result, provides said essence and indicates synchronously.
9. equipment according to claim 6 also comprises:
The Viterbi decoding unit is used for according to said code check and said delete position the I/Q circuit-switched data being carried out Viterbi decoding, draws said decode results.
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| CN1179036A (en) * | 1996-08-23 | 1998-04-15 | 大宇电子株式会社 | Synchronous method and device in wetby decoder |
| CN1183678A (en) * | 1996-10-25 | 1998-06-03 | 松下电器产业株式会社 | Method and device for determining thresholds of metric values used in Viterbi synchronization evaluation circuits |
| US7161995B1 (en) * | 2002-03-15 | 2007-01-09 | Xilinx, Inc. | Method and apparatus for Viterbi synchronization |
| CN101247203A (en) * | 2007-02-16 | 2008-08-20 | 联发科技股份有限公司 | Apparatus and method for determining a detected punctured position in punctured convolutional codes |
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