CN101656256A - Active area structure - Google Patents
Active area structure Download PDFInfo
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- CN101656256A CN101656256A CN200810041882A CN200810041882A CN101656256A CN 101656256 A CN101656256 A CN 101656256A CN 200810041882 A CN200810041882 A CN 200810041882A CN 200810041882 A CN200810041882 A CN 200810041882A CN 101656256 A CN101656256 A CN 101656256A
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- active area
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Abstract
The invention relates to an active area structure. An active area is a second type active area in a semiconductor substrate; the surface of the second type active area is covered with a gate oxide layer; the gate oxide layer is provided with a source selecting gate corresponding to the position of the second type active area; the second type active area also comprises an insulator well area; and the insulator well area corresponds to the position of an interconnecting structure for connecting the source selecting gate. By arranging the insulator well area at the position of the interconnectingstructure corresponding to the source selecting gate in the second type active area, the active area structure can effectively increase resistance between the source selecting gate and the second type active area under the source selecting gate and improve the insulated isolation performance between the both, thereby solving the problem of big leakage current between the source selecting gate andthe active area caused by the damage of the gate oxide layer under the interconnecting structure of the source selecting gate, reducing the power consumption of a NAND device, and improving the stability of the device.
Description
Technical field
The present invention relates to the making field of NAND Logic (hereinafter to be referred as NAND) flush memory device, the active area structure under the grid contact hole is selected in the source that relates in particular to NAND.
Background technology
The nand flash memory device is a kind of common memory device in the present consumer electronics product market, belongs to voltage-controlled device.This device is based on tunnel effect, by self floating grid being charged and discharging, realizes writing and wiping of data.
See also NAND shown in Figure 1 and relate to the domain schematic diagram that grid (Source Selection Gate:SSG) part is selected in the source.Domain has as shown in Figure 1 illustrated to be produced on the active area in the Semiconductor substrate.Active differentiation first kind active area: the active area that is used to make memory cell device; The second class active area: non-memory cell device is made the active area in zone, is similar to the second class active area.First kind active area shown in Figure 1 is an example with NAND device stores unit active area 51, and it is that example is described the problem that present active area exists that the second class active area leads to source region 52 with trap.The source selects grid 4 to be positioned at memory cell active area 51 and trap leads on the source region 52.Make its interconnection structure-active area contact hole 12 on the memory cell active area 51.The source is selected to be manufactured with on the grid 4 corresponding interconnection structure-source and is selected grid contact hole 11.The source selects filled conductive plug realization sources in grid contact hole 11 and the active area contact hole 12 to select being connected of grid and first kind active area and external metallization wiring layer.According to layout design rules, with domain shown in Figure 1 is example, select to select the grid contact hole in the making source on grid 4 parts with the source that memory cell active area 51 overlaps, therefore under the situation of not increase source selection grid additional areas, making source selection grid contact hole 11 on grid 4 parts is selected in the source of selecting to lead to source region 52 overlappings with trap.
See also shown in 2 device cross sectional representation along domain AA ' direction correspondence shown in Figure 1.Memory cell active area 51 and trap lead to source region 52 and are positioned at Semiconductor substrate 9.Between the memory cell active area 51 or memory cell active area 51 and trap lead between the source region 52 to isolating shallow trench (Shallow TrenchIsolation, STI) 8.Gate oxide 7 is positioned at and has Semiconductor substrate 9 surfaces that memory cell active area 51 and trap lead to source region 52.The source selects grid 4 to be positioned at gate oxide 7 surfaces.Above-mentioned interconnection structure: grid contact hole 11 and active area contact hole 12 are selected in the source, are to connect interlayer dielectric layer 6 to form.Interlayer dielectric layer 6 is positioned at the surface of the gate oxide 7 of making source selection grid 4, and grid 4 are selected in the covering source.Active area contact hole 12 and source are selected grid contact hole 11 to be used for successive process and are selected filled conductive plug in the grid contact hole 11 at active area contact hole 12 and source.Realize that like this memory cell active area 51 and source select being connected of grid 4 and external metallization wiring layer.
As shown in Figure 2, active area contact hole 12 and source select grid contact hole 11 normally to adopt dry etching, come etching interlayer dielectric layer 6 to form.Dry etching mainly is ion(ic) etching, promptly bombards presumptive area with etch ion, material in the etching presumptive area.Using etch ion etching interlayer dielectric layer 6, when selecting grid contact hole 11 with the formation source, etch ion will be passed the source and be selected grid contact hole 11 to select grid 4 along the source of conductive material, and the gate oxide 7 under the grid contact hole 11 is selected in the source that enters, and this will make gate oxide 7 damage.It is relatively poor that the source selects the damage of gate oxide 7 under the grid contact hole source that can make to select grid 4 and trap to lead to source region 52 insulation isolation, causes leakage current big, the power consumption increase of nand flash memory device, and the problem of bad stability.
For addressing the above problem, prior art is by selecting grid 4 to extend to the source, extend and be specifically designed to the zone that the exit of grid 4 is selected in the making source, thereby avoid the source is selected grid contact hole 11 to be produced on to be similar to address the above problem on the second class active area that trap leads to source region 52.Yet it is the area of selecting grid 4 with the increase source that prior art addresses this problem, and then the area that increases the nand flash memory device is a cost.Therefore, it is little that this method has reduced the nand flash memory device area to a great extent, the advantage that memory capacity is high.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of active area structure, can solve because of gate oxide under the source selection grid interconnection structure damages to cause the source to select the big problem of leakage current between the grid and the second class active area.
For solving the problems of the technologies described above, active area structure provided by the invention, related active area are the second class active area in the Semiconductor substrate, and the described second class active area is coated with gate oxide; On the described gate oxide with the corresponding active selection grid in the second class active area position; It is characterized in that, also comprise an insulant wellblock in the described second class active area, described insulant wellblock is corresponding with the position of the interconnection structure that is used for connection source selection grid.
Active area structure provided by the invention is provided with the insulant wellblock in corresponding active area position under the interconnection structure of source selection grid, the insulation isolation between the grid and the second class active area is selected in the source that can further improve, this insulant wellblock.Even as described in the background section, damage gate oxide when the interconnection structure of ion(ic) etching formation source selection grid, the reduction source is selected under the situation of insulation isolation between the grid and the second class active area, the grid and the second class active area are selected in this insulant wellblock effectively isolation source, solve the gate oxide damage big problem of leakage current down.Therefore, the power consumption that active area structure provided by the invention can further solve the nand flash memory device that due to leakage current causes greatly increases, and the problem of bad stability.
Active area structure provided by the invention in addition need not to select grid to carry out any extension to the source, thereby need not the area that grid are selected in the increase source, meets the NAND component compact, the characteristics that area is little.
Description of drawings
Below in conjunction with the drawings and specific embodiments active area structure of the present invention is described in further detail.
Fig. 1 is the part domain schematic diagram of NAND device.
Fig. 2 is the device cross sectional representation along domain AA ' direction correspondence shown in Figure 1.
Fig. 3 is the part domain schematic diagram that the NAND device source is selected grid in the embodiment of the invention.
Fig. 4 is the device cross sectional representation along BB ' direction domain correspondence shown in Figure 3.
Embodiment
Fig. 3 is the part domain schematic diagram that the NAND device source is selected grid in the embodiment of the invention.Can see the active area in the Semiconductor substrate from the domain shown in Figure 3.Active area comprises the first kind active area and the second class active area.As identical in the background technology, to lead to source region 52 with memory cell active area 51, the second class active areas with trap be example to first kind active area in the present embodiment.Memory cell active area 51 and trap lead to and make active selection grid 4 on the source region 52.Make interconnection structure-active area contact hole 12 on the memory cell active area 51.The source is selected to be manufactured with on the grid 4 interconnection structure-source and is selected grid contact hole 11.It is that trap leads to source region 52 that the active area under the grid contact hole 11 is selected in the source.As stated in the Background Art, when selecting grid interconnection structure-source to select grid contact hole 11 in etching formation source, etch ion can cause damage by the gate oxide that the source selects grid contact hole 11 and conductor source to select 4 pairs of sources of grid to select grid 4 and trap to lead between the source region 52, thereby reduce gate oxide source selection grid 4 and trap is led to the insulating properties isolation that is play a part in source region 52.Lead to insulating properties between source region 52 and the source selection grid 4 for further improving trap, trap under interconnection structure-source selection grid contact hole 11 of aligning source selection grid leads to the position, source region one insulant wellblock 521 is set, and plays the effect that further raising trap leads to insulating properties between source region 52 and the source selection grid 4.
Structure for the practical devices of more clearly describing Fig. 3 domain correspondence sees also Fig. 4.Fig. 4 is the device cross sectional representation along BB ' direction domain correspondence shown in Figure 3.Corresponding to active area shown in Figure 3, promptly memory cell active area 51 and trap lead to source region 52 and all are positioned at Semiconductor substrate 9.Semiconductor substrate 9 surface coverage with active area have gate oxide 7; Gate oxide 7 surfaces are manufactured with corresponding to the source of Fig. 3 and select grid 4 on the active area.For making the interconnection structure that grid 4 are selected in memory cell active area 51 and source, select grid 4 surfaces and gate oxide 7 surfaces all to be coated with interlayer dielectric layer 6 in the source.Interlayer dielectric layer 6 has the source that connects interlayer dielectric layer and selects grid interconnection structure-source to select grid contact hole 11 and memory cell active area 51 interconnection structures-active area contact hole 12.Select grid contact hole 11 and active area contact hole 12 corresponding to source shown in Figure 3, the source selects filled conductive plugs in grid contact hole 11 and the active area contact hole 12 to select being connected of grid 4 and memory cell active area 51 and metal wiring layer in the realization source respectively.Shown between the memory cell active area 51 or trap lead to and have the shallow trench 8 of isolation between source region 52 and the memory cell active area 51.Isolate in the shallow trench 8 and be filled with insulant silicon dioxide.Isolating shallow trench is semiconductor fabrication isolation technology commonly used, therefore repeats no more.Corresponding to Fig. 3, as shown in Figure 4, be that the raising source selects the source under the grid contact hole 11 to select grid 4 parts and the second class active area, promptly trap leads to source region 52, between insulating properties, trap leads to an insulant wellblock 521 in the source region 52.As shown in Figure 4, the surface of this insulant wellblock 521 contacts with the gate oxide 7 on Semiconductor substrate 9 surfaces, and grid contact hole 11 is selected in the source that these 521 aligning sources, insulant wellblock are selected to open in the interconnection structure-interlayer dielectric layer 6 of grid.
When using etch ion etching interlayer dielectric layer 6, when selecting grid contact hole 11 with the formation source, the insulating properties that the insulant wellblock can the realization source selects grid 4 and trap to lead between the source region 52 is isolated, and the big between the two leakage problem that gate oxide 7 damages of avoiding plasma etching to cause cause produces.Therefore, the embodiment of the invention is provided with insulant wellblock 521 by leading at trap in the source region 52, can increase substantially trap and lead to source region 52 and source and select resistance between the grid 4, and the reduction source selects grid 4 and trap to lead to leakage current between the source region 52.The reduction of leakage current between the two can effectively reduce the NAND device power consumption, improves its stability.
The active area structure of the embodiment of the invention, trap leads to source region 52 and forms an insulant wellblock by the trap active area position under source grid contact hole 11, select under the grid contact hole source to select grid pre-4 and trap to lead to resistance between the source region 52 by the raising source, thus insulating properties buffer action between the two.Therefore, the active area structure of the embodiment of the invention source that makes is selected grid to need not to carry out any extension to avoid the source to select the grid contact hole to be made on the active area of semiconductor substrate, thereby need not the area that grid are selected in the increase source, make the active area structure of the embodiment of the invention meet the NAND component compact, the characteristics that area is little.
At present, source selection grid contact hole 11 and active area contact hole 12 all are to adopt dry etching interlayer dielectric layer 6 to form.When the etch ion etching interlayer dielectric layer 6 that adopts dry etching, when selecting grid contact hole 11 with the formation source, the etch ion of different angles will be passed the source and be selected grid contact hole 11 and source to select grid 4, enter into gate oxide 7, this will cause the relative source of area to select the gate oxide 7 that grid contact hole 11 will be big slightly to damage.By the gate oxide 7 of damage, the source selects grid 4 and trap to lead between the source region 52 can exist bigger leakage current.Certainly, the trap area that leads to insulant wellblock 521 in the source region 52 is less than or equal to the source and selects the area of grid contact hole 11 also can play further raising source to select trap in grid 4 and the Semiconductor substrate to lead to the effect of the insulation isolation between the source region 52.For guaranteeing that comprehensively effectively the isolation source selects grid 4 and trap to lead to source region 52, the source selects grid contact hole 11 upright projections to be positioned at insulant wellblock 521 in the zone of active area 52, and promptly the area of insulant wellblock 521 is greater than the area that grid contact hole 11 is selected in the source.Like this, when even etch ion causes the relative source of area to select the big slightly gate oxide of grid contact hole 11 areas from different perspectives, insulant wellblock 521 also can select grid 4 and trap to lead to comprehensive insulating properties isolation in source region 52 in the realization source, trap leads to the leakage current that exists between the source region in reduction source selection grid and the Semiconductor substrate, thereby reduce the NAND device power consumption, improve device stability.
The embodiment of the invention also provides the structure type that the insulant wellblock can make in the source region.This insulant wellblock 521 can be made as the isolation shallow trench.Owing to when making the active area of NAND, need be manufactured with usually and isolate shallow trench between the source region.The insulant wellblock is made as the isolation shallow trench, in the isolation shallow trench of making between Semiconductor substrate active area and the active area 8, just can makes trap so and lead to insulant wellblock 521 among the source region 52.The source selects the trap under the grid contact hole to draw the existence of insulant wellblock 521 in the active area structure, the degree of depth regardless of the insulant wellblock 521 that makes, promptly less than, be equal to or greater than the degree of depth that trap leads to source region 521, all can play the raising source and select grid and trap to lead to resistance between the source region, promptly insulating properties is isolated with effect.For guaranteeing to make the consistency of isolating shallow trench 8 and insulant wellblock 521 technologies, avoid adopting unique technology to make insulant wellblock 521 and the make efficiency of reduction NAND device, in the embodiment of the invention, the degree of depth of the isolation shallow trench 8 in the degree of depth of insulant wellblock 521 and the Semiconductor substrate between the active area is consistent as shown in Figure 4.Like this, the active area structure of the embodiment of the invention need not to change the manufacturing process of original NAND device fully, avoid increasing the insulation wellblock in the extra manufacturing process making active area structure, thereby improve the make efficiency of embodiment of the invention active area structure, reduce cost of manufacture.
Active area in the embodiment of the invention under the source selection grid contact hole is that trap leads to the source region, other device architectures can not occur but do not get rid of.If require the source select the source of grid contact hole select gate part with its down device architecture isolate, in this device architecture, all can make the insulant wellblock and play that grid are selected in the raising source and the insulating properties buffer action between the device architecture under it.Therefore, source of the present invention selects the trap of the conduct second class active area that the active area under the grid contact hole is not limited to exemplify among the embodiment to lead to the source region.Change and distortion in not breaking away from invention spirit and scope of the present invention, then the present invention also be intended to comprise these change and modification interior.
Claims (6)
1, a kind of active area structure, described active area are the second class active area in the Semiconductor substrate, and the described second class surfaces of active regions is coated with gate oxide; Have the source corresponding on the described gate oxide and select grid with the second class active area position; It is characterized in that, also comprise an insulant wellblock in the described second class active area, described insulant wellblock is corresponding with the position of the interconnection structure that is used for connection source selection grid.
2, active area structure as claimed in claim 1 is characterized in that, it is that the grid contact hole is selected in the source that the interconnection structure of grid is selected in described source, and described source selects the zone of grid contact hole upright projection on described active area to be positioned at described insulant wellblock.
3, active area structure as claimed in claim 1 is characterized in that, described insulant wellblock is for isolating shallow trench.
4, active area structure as claimed in claim 1 is characterized in that, the described second class active area is that trap leads to the source region.
5, active area structure as claimed in claim 1 is characterized in that, described gate oxide is an earth silicon material, and it is conductor material that grid are selected in described source.
6, active area structure as claimed in claim 5 is characterized in that, it is polycrystalline silicon material that grid are selected in described source.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100418820A CN101656256B (en) | 2008-08-19 | 2008-08-19 | Active area structure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2008100418820A CN101656256B (en) | 2008-08-19 | 2008-08-19 | Active area structure |
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| CN101656256A true CN101656256A (en) | 2010-02-24 |
| CN101656256B CN101656256B (en) | 2011-04-20 |
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| CN2008100418820A Active CN101656256B (en) | 2008-08-19 | 2008-08-19 | Active area structure |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456774A (en) * | 2012-06-01 | 2013-12-18 | 台湾积体电路制造股份有限公司 | Semiconductor device having non-orthogonal element |
| CN111785683A (en) * | 2020-07-17 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Semiconductor device forming method and layout structure |
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2008
- 2008-08-19 CN CN2008100418820A patent/CN101656256B/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103456774A (en) * | 2012-06-01 | 2013-12-18 | 台湾积体电路制造股份有限公司 | Semiconductor device having non-orthogonal element |
| CN111785683A (en) * | 2020-07-17 | 2020-10-16 | 上海华虹宏力半导体制造有限公司 | Semiconductor device forming method and layout structure |
| CN111785683B (en) * | 2020-07-17 | 2024-05-03 | 上海华虹宏力半导体制造有限公司 | Semiconductor device forming method and layout structure |
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| Publication number | Publication date |
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| CN101656256B (en) | 2011-04-20 |
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