JP3795798B2 - Semiconductor memory device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a dynamic semiconductor memory device (DRAM) having stacked memory cells.
[0002]
[Prior art]
In a conventional dynamic semiconductor memory device having a stack type memory cell, a storage cell capacitor is formed between a plurality of storage nodes and plate electrodes via a dielectric film.
[0003]
FIG. 15 shows a part of the configuration of a conventional stacked memory cell. A plate electrode 143 is formed on a plurality of storage nodes 141 formed on a semiconductor substrate (not shown) via a dielectric film 142. After forming up to the plate electrode 143 by a method such as spin coater, sputtering, or CVD, the plate electrode 143 and the dielectric film 142 are covered with a resist 144 in order to form the plate electrode 143 and the dielectric film 142 in a predetermined shape. Processing was performed by a dry etching technique using charged particles 145 such as RIE and CDE.
[0004]
[Problems to be solved by the invention]
However, these dry etching techniques use charged particles 145 accelerated by an electric field, and the charged particles 145 directly collide with the plate electrode 143.
[0005]
As shown in FIG. 16, since this etching is performed up to a predetermined depth on the surface of the plate electrode 143, charge-up occurs in the plate electrode 143 that is electrically floating in these processing steps. Since the plate electrode 143 is made of a conductive material, the charged charge moves through the plate electrode 143, and the capacitors on all the storage nodes 141 located away from the part that is actually processed are connected. There is a problem that electrical stress is applied to the dielectric film 142 to be formed, and in some cases, a discharge 146 is generated to damage the dielectric film 142.
[0006]
After processing the plate electrode, an interlayer insulating film 147 such as SiO 2 is formed thereon as shown in FIG. This is because contact with the interlayer green film 147 on the plate electrode 143 is performed in order to connect the voltage generating circuit (not shown) and the plate electrode 143 in order to give a specific potential to the plate electrode 143 during DRAM operation. This is because the hole 148 needs to be opened.
[0007]
The processing of the contact hole 148 is also performed by the dry etching technique in the same manner as the processing of the plate electrode 143 shown in FIG. As shown in FIG. 17, when the interlayer insulating film 147 remains, the contact resistance becomes high, so that the etching needs to be performed sufficiently. Therefore, dry etching of the contact hole 148 shows the bottom of the hole as shown in FIG. As described above, after reaching the plate electrode 143, the etching is performed slightly more and over-etching is performed so that a hole is dug shallowly in the plate electrode 143.
[0008]
Also at this time, the plate electrode 143 is charged up, causing a problem that the dielectric film 142 is damaged.
[0009]
Further, after opening a contact hole 148 on the plate electrode 143, although not shown, the contact hole 148 is filled with a contact material to form an upper wiring layer, and then this wiring layer is also processed by dry etching. Also in this case, similarly to the above, there is a problem that the plate electrode 143 is charged up by the electric charge passing through the conductive material such as the wiring layer and the contact, and the dielectric film 142 of the capacitor is damaged.
[0010]
Further, if a material having a high dielectric constant is used as the material of the dielectric film 142 and the thickness thereof can be reduced, the size and the speed can be reduced. However, the conventional apparatus is not possible due to the above-described problems.
[0011]
Therefore, the object of the present invention is to prevent damage to the capacitor dielectric film by avoiding the charge-up of the plate electrode of the cell capacitor in the dry etching process, thereby improving the yield and reliability, and further reducing the thickness of the dielectric film. Another object of the present invention is to provide a semiconductor memory device that can adopt a new dielectric film material and can easily disconnect the connection between the plate electrode and the semiconductor substrate at the end of the manufacturing process.
[0012]
[Means for Solving the Problems]
The present invention electrically connects a plate electrode of a dynamic semiconductor memory device (DRAM) having a stack cell capacitor to a semiconductor substrate, so that the cell capacitor is electrically connected to the cell capacitor portion during dry etching of the plate electrode and its upper wiring layer. The semiconductor memory device has a configuration in which stress can be alleviated and the connection between the plate electrode and the semiconductor substrate can be easily disconnected at the end of the manufacturing process.
[0013]
A semiconductor memory device according to the present invention includes a semiconductor substrate, a plurality of storage nodes of a memory cell formed on the semiconductor substrate, and at least one electrically connected to the semiconductor substrate along with the plurality of storage nodes. A plurality of dummy storage nodes, a dielectric film formed in common on the plurality of storage nodes excluding the dummy storage node, and a dummy storage node formed on the plurality of storage nodes via the dielectric film. An electrically connected plate electrode and a fuse electrically connected between the plate electrode and the semiconductor substrate via the dummy storage node are provided.
[0014]
With the above configuration, electrical stress can be relieved, so the life and reliability can be improved by preventing the deterioration of the dielectric film material of the cell capacitor, and the dielectric film is made thinner and new dielectric film material is adopted. And a semiconductor memory device having a configuration in which the connection between the plate electrode and the semiconductor substrate can be easily disconnected at the end of the manufacturing process.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Before describing embodiments of the present invention, a cross-sectional configuration of a semiconductor device related to the present invention will be described with reference to FIGS. In FIG. 1, a p-type well 11 is formed on an n-type silicon substrate 10, and two n + type diffusion regions 13 a and 13 b for forming a transfer gate 12 are formed on the surface of the well 11.
[0016]
When forming the two n + type diffusion regions 13a and 13b, the n + type diffusion region 14 is simultaneously formed outside the p type well 11 of the n type silicon substrate 10.
[0017]
A word line 16 serving as a gate electrode is formed on the surface of the p-well 11 where the two n + -type diffusion regions 13a and 13b are formed via a gate insulating film 15, and an interlayer insulating film 17 is formed as a whole. .
[0018]
A contact hole 18 is formed in the interlayer insulating film 17 so as to reach one n + type diffusion region 13a. The contact hole 18 is filled with a conductive material, and then a bit line 19 is formed on the interlayer insulating film 17. Is formed.
[0019]
An interlayer insulating film 17 is further formed on the bit line 19, and a storage node hole 20 is formed in the interlayer insulating film 17 so as to reach the other n + type diffusion region 13b. A conductive material is filled, and then a storage node 21 is formed on the interlayer insulating film 17.
[0020]
Similarly, a dummy terminal hole 22 having the same shape as the storage node 21 connected to the n + type diffusion region 14 formed outside the p-type well 11 is formed, and the dummy terminal hole 22 is filled with a conductive material. Then, the dummy terminal 23 is formed. As shown in FIG. 2, a capacitor dielectric film 24 is formed in common on the upper surface of the storage node 21 and the dummy terminal 23 thus formed, and a resist 25 is further formed thereon.
[0021]
Before forming the dielectric film 24 in a predetermined pattern using the resist 25 as a mask, the dielectric film 24 at a position corresponding to the dummy terminal 23 is removed by a dry etching technique using charged particles 26 such as RIE and CDE, As shown in FIG. 3, the dummy terminal 23 is exposed.
[0022]
Thereafter, the resist 25 is removed to expose the dielectric film 24, and a plate electrode 27 is formed on the upper surface of the dielectric film 24 and the dummy terminal 23 as shown in FIG.
[0023]
Thus, in this configuration, the plate electrode 27 is connected to the diffusion region 14 of the n substrate 10 via the dummy terminals 22 and 23 and is grounded. The n substrate 10 is grounded during the manufacturing process of the semiconductor memory device. For example, a base on which the n substrate 10 of the production line is placed may be grounded.
[0024]
As shown in FIG. 1, the normal storage node 21 is connected to the source / drain 13 b of the MOSFET which is the transfer gate 12. The transfer gate 12 is usually formed inside the p-well 11 and is not directly electrically connected to the substrate 10.
[0025]
For this reason, dummy terminals 22 and 23 having the same shape as the storage node 21 are installed at locations outside the well 11 so as to be electrically connected to the substrate 10.
[0026]
In the example in which the n-type MOSFET formed in the P-well 11 provided on the n-type substrate 10 is the transfer gate 12 as shown in FIG. 1, dummy terminals 22 and 23 having the same shape as the storage node 21. Uses the n + diffusion layer 14 having the same conductivity type as that of the substrate 10 so as to be directly electrically connected to the n-type substrate 10. In this case, the dummy terminals 22 and 23 are simultaneously processed by the same process as the storage node 21. Can be formed. Therefore, there is no increase in the process by providing dummy terminals 22 and 23 having the same shape as the storage node 21.
[0027]
After the plate electrode 27 is grounded using the dummy electrodes 22 and 23, an interlayer insulating film 30 such as SiO2 is formed thereon as shown in FIG. 5, and a resist 31 is further formed thereon.
[0028]
Next, in order to apply a specific potential to the plate electrode 27 during the DRAM operation, a contact is made to the interlayer green film 30 on the plate electrode 27 in order to connect the voltage generating circuit (not shown) and the plate electrode 27. Open the hole 32.
[0029]
During processing of the contact hole 32, dry etching is performed with the charged particles 33 so that the surface of the plate electrode 27 is over-etched.
[0030]
At this time, the plate electrode 27 is charged up, but the charge is discharged to the grounding portion via the dummy electrodes 22 and 23, so that the problem of damaging the dielectric film 24 does not occur.
[0031]
Although not shown, after opening the contact hole 32 on the plate electrode 27, the contact hole 32 is filled with a conductive contact material to form an upper wiring layer, and this wiring layer is also processed by dry etching. Do. In this case as well, the plate electrode 27 is charged up by the electric charge passing through the conductive material such as the wiring layer and the contact in the same manner as described above. However, since it is similarly discharged, the dielectric film 24 of the capacitor of the stack cell is damaged. Never give.
[0032]
Further, since it is possible to prevent the plate electrode 27 from being charged up, a material having a high dielectric constant can be used as the material of the dielectric film 24, and the thickness thereof can be made thinner than before, and the DRAM can be reduced in size and speeded up. .
[0033]
In this configuration, the n + diffusion layer 14 provided on the n-type substrate 10 is used to connect the plate electrode 27 and the substrate 10. However, even if the conductivity types of the substrate 10, well 11, and transfer gate 12 are reversed, the same applies. Can be configured.
[0034]
FIG. 6 shows an example, and the p + diffusion layer 44 is formed on the p-type substrate 40, and the dummy electrodes 52 and 53 can be grounded via the p substrate 40. The configuration example of FIG. 6 is the same as the configuration example of FIG.
[0035]
That is, in the n well 41 formed on the p substrate 40, p + diffusion regions 43a and 43b constituting the source / drain of the transfer gate 42 are formed. Between the p + diffusion regions 43a and 43b, a word line 46 as a gate is formed via a gate oxide film 45, and the p + diffusion layer 43a and the bit line 49 are connected by a contact 48 formed on the interlayer insulating film 47. To do.
[0036]
Further, contact holes 50 and 52 are formed in the interlayer insulating film 47, and a storage node 51 and a dummy terminal 53 are formed at the respective tips.
[0037]
After that, if a plate electrode connected to the dummy terminal 53 is formed in the same manner as shown in FIG. 5, even if the plate electrode is charged up with charged particles in the subsequent manufacturing process using dry etching, the plate electrode and the storage node It is possible to prevent an electrical stress from being applied to the capacitor dielectric film formed therebetween.
[0038]
In the configuration of FIG. 5, when the upper and lower electrodes of the dielectric film 24, that is, the portion of the dummy electrode 23 that contacts the dielectric film 24 and the portion of the plate electrode 27 that contacts the dielectric film 24 are formed of the same conductive material, When both are directly connected, a better electrical connection is obtained.
[0039]
On the other hand, when the materials of the dummy electrode 23 and the plate electrode 27 are different, a barrier metal is required at the connecting portion depending on the combination. In this case, after the dielectric film 24 is dry-etched in FIG. 3, a barrier metal (not shown) is formed on the dummy electrode 23 using the remaining resist 25 as a mask, and then the resist 25 is lifted off to form a dummy. A barrier metal can be formed only on the electrode 23.
[0040]
Further, in the configuration example shown in FIG. 6, the same operation can be performed by forming a p-well in the n-well 41 and forming a transfer gate therein. FIG. 7 shows an example. The configuration example of FIG. 7 is the same as the configuration example of FIG. 6 except that the transfer gate 42 is formed in the double diffusion well 61 provided on the p substrate 40. Description is omitted.
[0041]
Of course, in FIG. 7, the conductivity types of p and n may be reversed.
[0042]
After the manufacturing process is completed and the DRAM is completed, a potential at the plate electrode 27 is applied during operation. This method can be applied to the plate electrode from the wiring layer above the plate electrode 27 or from the substrate 10 to the plate electrode.
[0043]
When the semiconductor substrate 10 and the plate electrode 27 have the same potential during operation after the DRAM is manufactured in the configuration of FIG. 5, the connection between the two may be left as it is, but when the potential during operation differs. Both connections must be disconnected at the time of shipment.
[0044]
That is, although not shown, when a MOSFET that is directly a transfer gate is formed on a semiconductor substrate, a potential different from that of the plate electrode must be applied to the semiconductor substrate in order to apply a back gate voltage to the MOSFET. For this purpose, it is necessary to electrically separate the semiconductor substrate and the plate electrode. As a method therefor, in one embodiment of the present invention, a path for grounding the plate electrode is connected to the semiconductor substrate via a fuse at the time of manufacturing, and the fuse is cut at the end of the manufacturing process.
[0045]
8 and 9 show an embodiment of the present invention in which a fuse is used as an example of the cutting means. Between the plate electrode portion 67 facing the storage node 61 and the ground electrode portion 68 facing the dummy terminal 23, FIG. An elongated connection portion used as the fuse 69 is formed.
[0046]
When the fuse 69 is provided between the plate electrode portion 67 and the ground electrode portion 68, the plate electrode portion 67 facing the storage node 61 shown in FIGS. The ground electrode portion 68 facing the dummy terminal 23 and the elongated connection portion used as the fuse 69 can be formed.
[0047]
A difference from the configuration of FIGS. 2 to 4 is that the shape of the whole plate electrode is a dummy having a shape similar to that of the storage node 61 and the portion 67 facing the storage node 61 as shown in FIGS. The point is that a fuse 69 is provided between a portion 68 in contact with the terminal 62.
[0048]
As a method for cutting the fuse 69 after manufacturing the DRAM, there is a method using a laser blow. In this case, it is necessary to open a blow window on the fuse 69. This window can be formed in a portion corresponding to the fuse 69 of the insulating film 30 in common with the process of forming the contact hole 32 for applying a potential to the plate electrode 27 shown in FIG. As a result, an increase in the process does not occur. In addition to the laser blow, a method such as a current fuse that electrically cuts a fuse can also be used.
[0049]
In this embodiment, the wiring layer of the plate electrode is used as the wiring layer for providing the fuse. However, any of the word line wiring layer, the bit line wiring layer, and the storage node wiring layer can be installed.
[0050]
In the embodiment described above, the DRAM has a configuration in which a plurality of stacked memory cells are formed under one plate electrode. However, actually, a single DRAM chip has a plurality of plate electrodes. Required, multiple chips are formed under each plate electrode.
[0051]
These plate electrodes are connected in various forms depending on the application of the DRAM. It is classified as follows according to the connection method.
[0052]
1. When there are multiple plate electrodes that are not connected to each other.
[0053]
In this case, since a ground electrode connected to the dummy electrode is required for each plate electrode, a fuse for cutting the both is also required. Furthermore, a plate potential generating circuit for keeping the plate electrode at a predetermined potential during operation is also required.
[0054]
2. When a plurality of plate electrodes are connected to each other in the DRAM chip.
[0055]
In this case, as shown in the embodiment of FIG. 10, all plate electrodes 77-11, 77-12. . . It is only necessary to provide one ground electrode 78 and one fuse 79 for 77-mn. Of course, a plurality of fuses 79 may be formed in consideration of the reliability. Further, only one plate potential generation circuit (VPL gen.) 80 is required.
[0056]
The plate potential (VPL) generation circuit 80 is formed at the corner of the DRAM chip 71 in the embodiment of FIG. 10, but the position to be formed can be freely selected at the design stage.
[0057]
Further, the connection between the plate electrode and the VPL generation circuit can also be performed through a wiring layer formed in an upper layer or a lower layer than the plate electrode.
[0058]
For example, as shown in FIG. 12, a wiring layer 91 A formed on the plate electrode 27 via the interlayer insulating film 30 is connected to the VPL generation circuit 80. The plate electrode 27 and the wiring layer 91 </ b> A are connected via a contact 90 </ b> A formed on the interlayer insulating film 30.
[0059]
In the example of FIG. 13, the plate electrode 27 and the VPL generation circuit 80 are connected to a wiring layer 91B formed in the same layer as the bit line 19 via a contact 90B.
[0060]
Further, in the example of FIG. 14, the plate electrode 27 is connected directly to the n + diffusion region 94a of the output gate 93 of the VPL generation circuit 80 in the P well 11 in which the transfer gate 12 of the memory cell is formed, via a contact 90C. ing. However, it goes without saying that the VPL generation circuit 80 may be formed in a separate well without being formed in the same P well 11 as the transfer gate 12.
[0061]
For connection between the plurality of plate electrodes, a wiring layer formed above the layer of the plate electrodes can also be used. In this case, it is necessary to provide a fuse for each plate electrode.
[0062]
Alternatively, it can be performed using a plate electrode layer or a lower wiring layer. In this case, it is only necessary to form one fuse for the whole.
[0063]
In the embodiment of FIG. 10, fuses are formed inside the DRAM chip 71. In general, a plurality of DRAM chips are simultaneously formed on a silicon wafer and finally cut along a dicing line. Therefore, if the fuse is formed outside the chip along the dicing line, the fuse is also cut at the time of dicing, and the fuse cutting step can be omitted.
[0064]
FIG. 11 is an embodiment showing an example of this, and DRAM chips (only three chips 81A, 81B, 81C are shown here) formed on a silicon wafer are dicing lines x, y at the end of the manufacturing process. , For example, ground electrodes 88A, 88B, 88C for making contact with the semiconductor substrate drawn into the dicing lines x, y from the plate electrode groups 87A, 87B, 87C formed on the DRAM chip 81A, and All the fuses 89A, 89B, 89C are removed by dicing.
[0065]
In the embodiment shown in FIG. 11, the ground electrodes 88A, 88B, 88C and the fuses 89A, 89B, 89C for making contact with the semiconductor substrate are shown as having specific shapes. , 89B, 89C are removed without a fusing process by laser or current in this case, and a normal wiring layer may be formed.
[0066]
【The invention's effect】
As described above in detail, according to the present invention, during the manufacturing process, the deterioration of the stack cell capacitor can be suppressed and the yield can be improved, and the leakage current caused by high voltage stress is reduced, thereby improving the charge retention characteristics. In addition, a cell capacitor with a thin dielectric layer that could not be used due to deterioration by conventional plate electrode processing could be used, and furthermore, conventional plate electrode processing could not be used due to electrical breakdown and deterioration. It is possible to provide a semiconductor memory device having a configuration in which a new capacitor material can be used and the fuse can be easily cut at the end of the manufacturing process.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a configuration of a semi-finished product in the course of a manufacturing process of a semiconductor memory device related to the present invention.
2 is a cross-sectional view showing a state of a post-process in FIG. 1;
3 is a cross-sectional view showing a state of a post-process in FIG. 2;
4 is a cross-sectional view showing a plate electrode forming process that is a post-process of FIG. 3. FIG.
5 is a cross-sectional view showing a dry etching process that is a further post process of FIG. 4;
FIG. 6 is a cross-sectional view showing the configuration of a semi-finished product in the course of the manufacturing process of another semiconductor memory device related to the present invention.
FIG. 7 is a cross-sectional view showing the structure of a semi-finished product in the middle of the manufacturing process of still another semiconductor memory device related to the present invention.
FIG. 8 is a cross-sectional view showing a portion of a plate electrode with a fuse in the semiconductor device according to one embodiment of the present invention;
9 is a plan view of the portion of FIG. 8 as viewed from above.
FIG. 10 is a plan view showing an arrangement structure of plate electrode groups in one DRAM chip formed according to still another embodiment of the present invention.
FIG. 11 is a plan view showing a plurality of DRAM chips formed on a silicon wafer according to still another embodiment of the present invention.
FIG. 12 is a cross-sectional view showing an example of a method for connecting a plate electrode and a plate potential generating circuit in still another embodiment of the present invention.
FIG. 13 is a cross-sectional view showing another example of a method for connecting a plate electrode and a plate potential generating circuit.
FIG. 14 is a sectional view showing still another example of a method for connecting a plate electrode and a plate potential generating circuit.
FIG. 15 is a cross-sectional view showing a part of a manufacturing process of a conventional stacked memory cell.
16 is a cross-sectional view showing a post-process in FIG. 15;
FIG. 17 is a cross-sectional view showing a state in the middle of further post-process.
18 is a cross-sectional view showing the final stage of the process of FIG. 17;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... n board | substrate 14 ... n + diffusion area | region 21 ... storage node 23 ... dummy terminal 24 ... dielectric film 27 ... plate electrode 30 ... interlayer insulation film 31 ... resist 32 ... contact hole 33 ... charged particle 69 ... fuse

Claims (13)

A semiconductor substrate;
A plurality of storage nodes of memory cells formed on the semiconductor substrate;
At least one dummy storage node provided in parallel with the plurality of storage nodes and electrically connected to the semiconductor substrate;
A dielectric film formed on the plurality of storage nodes excluding the dummy storage node;
A plate electrode formed on the plurality of storage nodes via the dielectric film and electrically connected to the dummy storage node;
A fuse electrically connected between the plate electrode and the semiconductor substrate via the dummy storage node;
A semiconductor memory device comprising:   The semiconductor storage device according to claim 1, wherein the dummy storage node is electrically connected to the semiconductor substrate through a diffusion layer having the same conductivity type as the semiconductor substrate and having a higher impurity concentration than the semiconductor substrate.   The semiconductor storage device according to claim 1, wherein the dummy storage node is electrically connected to the semiconductor substrate by at least one metal contact forming a Schottky junction with the semiconductor substrate.   The semiconductor memory device according to claim 1, wherein the dummy storage node is electrically connected to the semiconductor substrate by at least one metal contact directly connected to the semiconductor substrate.   The semiconductor memory device according to claim 1, wherein the dummy storage node is electrically connected to the semiconductor substrate by at least one polycrystalline semiconductor contact directly connected to the semiconductor substrate. an n-type semiconductor substrate;
A p-type well formed on the n-type semiconductor substrate;
A plurality of first n-type regions formed on the p-type well;
A plurality of storage nodes electrically connected to the plurality of first n-type regions and formed on the memory cells;
At least one second n-type region formed on the n-type semiconductor substrate;
At least one dummy storage node electrically connected to the second n-type region so as to be provided alongside the plurality of storage nodes;
A dielectric film formed on the plurality of storage nodes excluding the dummy storage node;
A plate electrode formed on the plurality of storage nodes via the dielectric film and electrically connected to the dummy storage node;
A fuse electrically connected between the plate electrode and the dummy storage node;
A semiconductor memory device comprising: a p-type semiconductor substrate;
An n-type well formed on the p-type semiconductor substrate;
A plurality of first p-type regions formed on the surface of the n-type well;
A plurality of storage nodes of memory cells electrically connected to the plurality of first p-type regions,
At least one second p-type region formed on the surface of the p-type semiconductor substrate;
At least one dummy storage node electrically connected to the second p-type region so as to be co-located with the plurality of storage nodes;
A dielectric film formed on the plurality of storage nodes excluding the dummy storage node;
A plate electrode formed on the plurality of storage nodes via the dielectric film and electrically connected to the dummy storage node;
A fuse electrically connected between the plate electrode and the dummy storage node;
A semiconductor memory device comprising:   The semiconductor memory device according to claim 7, wherein the dummy storage node is electrically connected to the p-type semiconductor substrate through the second p-type region.   8. The semiconductor memory device according to claim 7, wherein the dummy storage node is electrically connected to the p-type semiconductor substrate by a metal contact that forms a Schottky junction with the p-type semiconductor substrate.   The semiconductor storage device according to claim 7, wherein the dummy storage node is electrically connected to the p-type semiconductor substrate by a metal contact directly connected to the p-type semiconductor substrate.   The semiconductor storage device according to claim 7, wherein the dummy storage node is electrically connected to the p-type semiconductor substrate by a polycrystalline semiconductor contact directly connected to the p-type semiconductor substrate. a p-type semiconductor substrate;
An n-type well formed on the p-type semiconductor substrate;
A p-type well formed in the n-type well;
A plurality of n-type regions formed on the surface of the p-type well;
A plurality of storage nodes of memory cells respectively electrically connected to the plurality of n-type regions;
At least one p-type region formed on the surface of the p-type semiconductor substrate;
At least one dummy storage node electrically connected to the p-type region so as to be provided side by side with the plurality of storage nodes;
A dielectric film formed on the plurality of storage nodes excluding the dummy storage node;
A plate electrode formed on the plurality of storage nodes via the dielectric film and electrically connected to the dummy storage node;
A fuse electrically connected via the dummy storage node between the plate electrode and the semiconductor substrate;
A semiconductor memory device comprising: an n-type semiconductor substrate;
A p-type well formed on the n-type semiconductor substrate;
An n-type well formed in the p-type well;
A plurality of first p-type regions formed on the surface of the n-type well;
A plurality of storage nodes of memory cells electrically connected to the plurality of first p-type regions,
At least one second p-type region formed on the surface of the n-type semiconductor substrate;
At least one dummy storage node electrically connected to the second p-type region so as to be co-located with the plurality of storage nodes;
A dielectric film formed on the plurality of storage nodes excluding the dummy storage node;
A plate electrode formed on the plurality of storage nodes via the dielectric film and electrically connected to the dummy storage node;
A fuse electrically connected between the plate electrode and the dummy storage node;
A semiconductor memory device comprising:

Images