CN101654221B - Electron beam exposure method for processing limit nano pattern on silicon material of insulator - Google Patents
Electron beam exposure method for processing limit nano pattern on silicon material of insulator Download PDFInfo
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- CN101654221B CN101654221B CN2009100322998A CN200910032299A CN101654221B CN 101654221 B CN101654221 B CN 101654221B CN 2009100322998 A CN2009100322998 A CN 2009100322998A CN 200910032299 A CN200910032299 A CN 200910032299A CN 101654221 B CN101654221 B CN 101654221B
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- 239000002210 silicon-based material Substances 0.000 title claims abstract description 55
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- 238000010894 electron beam technology Methods 0.000 title claims abstract description 37
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- 239000012212 insulator Substances 0.000 title claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 46
- 230000004888 barrier function Effects 0.000 claims abstract description 20
- 238000005498 polishing Methods 0.000 claims abstract description 9
- 238000001259 photo etching Methods 0.000 claims abstract description 6
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
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Abstract
The invention discloses an electron beam exposure method for processing a limit nano pattern on silicon material (SOI) of an insulator. The distinctive steps sequentially comprise: carrying out thickness reducing and polishing on bottom layer Si on back face of SOI; covering an etching barrier layer on the surface of top layer Si and bottom layer Si of front and back faces of SOI; carrying out photo-etching or combined etching on bottom layer Si to form an etching window, and further etching to buried layer SiO2 to form a self supporting structure having deep hole on the back face and film onthe front face; eliminating residual etching barrier layer on SOI, coating electron beam resist on top layer Si, and carrying out electron beam direct writing exposure on the top layer Si of SOI; andfinally developing and fixating the top layer Si to obtain the required limit nano pattern. The invention carries out deep etching technique on the back face of the area where the required pattern isgenerated facing SOI, thus greatly reducing bad influence of electron proximity effect, and providing an electron beam exposure method which features easy and convenient implementation, high pattern precision and low cost, and is used for generating limit nano level pattern on semi-conductive materials.
Description
Technical field
The present invention relates to a kind of semiconductor nano process technology, relate in particular to a kind of electron beam lithography that approach effect generates limit nano graph that on semi-conducting material, can overcome.
Background technology
The development of semiconductor, nano-device technology depends on the continuous progress of micro-nano process technology to a great extent.Along with the generally employing of electron beam lithography and constantly development, the figure working ability to semi-conducting material has reached nanometer scale at present.Electron beam exposure need not to use mask, can design the graphics processing of arbitrary shape through software, and is flexible and convenient to use; And the working ability with very fine, the present lines that obtained 10nm through this technology.
Yet because the existence of electronics approach effect; Adopt electron beam lithography processing limit nano level figure (such as the lines of 10～20nm live width of dense distribution; The triangle of the inferior 50nm length of side, rectangle etc.) be quite difficult, often need the approach effect alignment technique of more complicated.And the correction of approach effect is a whole set of very complicated process, need set up a series of models, and to various resists and backing material, needs to extract model parameter separately.The common approach effect correction software price of a current cover is often up to more than 500,000 yuan; Even and adopted the approach effect correction; The special graph of part limit gauge; Such as the triangle of the inferior 50nm length of side, rectangle etc., still difficultly prepare the figure that meets required precision, thereby restricted the deep application of semi-conducting material under limit nanoscale.For this reason, seeking a kind of electron beam exposure method that overcomes the electronics approach effect, and be introduced into the technology that semiconductor microcosmic figure generates, is the important topic that current the sector technical staff is devoted to explore and study.
Summary of the invention
Disappearance in view of above-mentioned existing electron beam lithography; The object of the invention aims to provide a kind of electron beam exposure method of processing limit nano pattern on silicon material of insulator; When overcoming processing limit nano level figure, need carry out approach effect complicated and that cost is high simultaneously and proofread and correct, even and overcome through approach effect and proofread and correct; Still be difficult to prepare the defective of part limit gauge special graph, break through the technology barriers of electron beam lithography on limit nano graph generates.
The technical scheme that the object of the invention is achieved is:
The electron beam exposure method of the processing limit nano pattern on silicon material of insulator, the silicon materials on the wherein said insulator are layered laminate, comprise the buried regions SiO of positive top layer Si, centre
2Bottom Si (silicon materials in this educational circles on this insulator all refer to SOI, so the terseness for explaining all refers to this silicon materials with SOI with the lower part) with the back side.Owing to electron backscattered coefficient along with material thickness reduces, the electronics approach effect also correspondingly drops to extremely low degree.The principal character of this electron beam exposure method is: utilize the buried regions SiO in the SOI material
2As etching stop layer certainly, the film Si material that etching obtains self-supporting carries out e-beam direct-writing exposure to this Si material again, just obtains required limit nano-scale pattern.Its method step is summarized as follows:
I, the bottom Si at the SOI back side carried out thickness is cut down and polishing;
II, to the positive top layer Si of SOI and the bottom Si surface coverage etching barrier layer at the back side;
III, the bottom Si at the SOI back side is carried out photoetching or combines etching, form etching window;
IV, the bottom Si to the SOI back side is etched to buried regions SiO again
2, form based on buried regions SiO
2The self supporting structure of back side deep hole and front film;
The etching barrier layer of V, removal top layer Si and bottom Si;
VI, then at SOI front surface coated electron sensitive resist;
VII, the SOI that the completion electron sensitive resist is applied carry out e-beam direct-writing exposure;
VIII, development, photographic fixing obtain required limit nano-scale pattern.
Further; The electron beam exposure method of the processing limit nano pattern on silicon material of aforementioned dielectric body, wherein reduction of the thickness of this bottom Si and polishing are to utilize the mode of one of cmp, the polishing of pure physics or other correlation means to process among the step I.And the thickness of its reduction is determined by etching barrier layer among Step II and the step IV and etching mode.
Further, the electron beam exposure method of the processing limit nano pattern on silicon material of aforementioned dielectric body, wherein this covering etching barrier layer is meant and utilizes plasma-reinforced chemical vapor phase epitaxial growth or thermal oxide SiO in the Step II
2Layer, or directly apply photoresist.
Further; The electron beam exposure method of the processing limit nano pattern on silicon material of aforementioned dielectric body; Wherein the size of this bottom Si formation etching window depends on the graphics area of on top layer Si, processing among the Step II I; Its generation type is directly to remove the etching barrier layer of photoresist type in the window area through photoetching, or combines dry etching, wet etching to remove SiO in the window area
2The etching barrier layer of type.
Further, the electron beam exposure method of the processing limit nano pattern on silicon material of aforementioned dielectric body wherein adopts the mode of dark silicon ICP etching or wet etching, and utilizes buried regions SiO among the step IV
2Etching from stopping property, form based on buried regions SiO
2The structure of back side deep hole and front film.
Further, the electron beam exposure method of the processing limit nano pattern on silicon material of aforementioned dielectric body, the wherein top layer Si of this SOI and buried regions SiO
2Gross thickness less than 10 microns.
The electron beam exposure method of the processing limit nano pattern on silicon material of insulator of the present invention, the beneficial effect of its application implementation is embodied in:
Employing generates the pre-prepared technology that deep etching is carried out at the regional back side to SOI towards required figure; Greatly reduced the adverse effect of electronics approach effect; Make that this material is carried out electron beam exposure to be generated limit nano graph and no longer need approach effect to proofread and correct, so provide a kind of and be easy to implement on semi-conducting material, generating limit nano-scale pattern, pattern precision is high and electron beam exposure method with low cost.
Below in conjunction with embodiment and flow process accompanying drawing thereof, experimental data chart, the electron beam exposure method of the processing limit nano pattern on silicon material of insulator of the present invention is done further nonrestrictive detailed description
Description of drawings
Fig. 1～Fig. 8 is the process structure sketch map of each step of electron beam exposure method of the present invention;
Fig. 9 is the backscattering coefficient curve synoptic diagram that the present invention adopts the 50KV electron beam incident different-thickness Si layer of monte carlo method simulation;
Figure 10 is the processing flow figure of electron beam exposure method of the present invention.
The specific embodiment
Like Fig. 1 to Fig. 8 and combine shown in Figure 10ly, be each the process structural representation and the processing flow figure of the electron beam exposure method of the present invention's processing limit nano pattern on SOI.Visible by above accompanying drawing: the applied semiconductor object structure of this electron beam lithography is the silicon materials (SOI) on the insulator, and its cross section is the layered laminate structure, comprises the buried regions SiO of positive top layer Si, centre
2With the bottom Si at the back side, wherein top layer Si and buried regions SiO
2Gross thickness less than 10 microns; And through the CMP mode; The thickness value of SOI back side bottom Si after cutting down, polishing can be between 100～150 microns (as shown in Figure 1), and the actual value of its thickness depends on etching barrier layer and the etching mode that this electron beam exposure method adopts.SOI after the reduction of the completion back side, the polishing is through the conventional thermal oxide or the mode of plasma-reinforced chemical vapor phase epitaxial growth (PECVD), and the layer thickness of on its positive and negative, growing respectively is about 1 micron and the high more good more SiO of density
2Etching barrier layer (as shown in Figure 2) is mainly used in and in the subsequent etching operation, protects the SOI material not by accidental destruction.And then, be that the bottom Si at the SOI back side is combined dry etching through photoetching, remove the SiO in the window area
2Etching barrier layer, the etching window (as shown in Figure 3) at the formation back side.The size of this etching window depends on the area of required graphics processing on top layer Si, generally in hundreds of square micron scopes.
After the formation of etching window, with SiO
2Etching barrier layer is as mask, to this SOI through dark silicon ICP mode etching dorsal pore, until the buried regions SiO of SOI
2(as shown in Figure 4).At this moment, utilize SiO
2And very high etching selection ratio between the Si is with this buried regions SiO
2As etching stop layer certainly, obtain bigger process allowance, form based on buried regions SiO
2The structure of back side deep hole and front film.
Then, remove the remaining SiO in the positive and negative surface of SOI through the wet etching mode
2Etching barrier layer (as shown in Figure 5), and at the high-resolution electron sensitive resist of its front surface coated (as shown in Figure 6).Wherein this wet etching mode is a routine techniques, as long as the various SiO that make
2Etching barrier layer is all capable of using from the test solution that SOI breaks away from; In addition, this electron sensitive resist can comprise one of them of PMMA, HSQ, ZEP520 or other similar materials.
After accomplishing above-mentioned preparation section in advance, just can carry out e-beam direct-writing exposure to the SOI front.As shown in Figure 7, figure is generated the zone, e-beam direct-writing exposure is carried out in promptly corresponding with back side deep hole film zone, front.After exposure is accomplished, again resist is carried out conventional development, photographic fixing processing (as shown in Figure 8), just can obtain required limit nano-scale pattern.
As shown in Figure 9, be the backscattering coefficient curve synoptic diagram that the present invention adopts the 50KV electron beam incident different-thickness Si layer of monte carlo method simulation.What the x axle referred among the figure is the Si layer thickness, and what the y axle referred to is backscattering coefficient, this shows, along with the continuous attenuate of Si layer thickness, its backscattering coefficient also decreases, and the approach effect of electron beam exposure reduces greatly.Facts have proved, to have better inhibited approach effect effect on silicon materials, carrying out electron beam exposure through attenuate Si layer thickness.
Exemplary detailed introduction to the electron beam exposure method of the processing limit nano pattern on silicon material of insulator of the present invention.Be intended to deepen understanding to essence of the present invention and beneficial effect.Be not to limit its multifarious embodiment and application protection domain with this; Therefore simple modification and the equivalence replacement carried out for the foregoing description in every case; Can realize the technical scheme of the creation purpose identical, all belong within the scope that this patent asks for protection with the present invention.
Claims (7)
1. the electron beam exposure method of the processing limit nano pattern on silicon material of insulator, the silicon materials on the wherein said insulator are layered laminate, comprise positive top layer Si, middle buried regions SiO
2Bottom Si with the back side is characterized in that: the step of said electron beam exposure method is:
I, said bottom Si carried out thickness is cut down and polishing;
II, to said top layer Si and bottom Si surface coverage etching barrier layer;
III, said bottom Si is carried out photoetching or combines etching, form etching window;
IV, said bottom Si is etched to buried regions SiO
2, the self supporting structure of formation back side deep hole and front film;
The etching barrier layer of V, the said top layer Si of removal and bottom Si;
VI, at said top layer Si surface-coated electron sensitive resist;
VII, e-beam direct-writing exposure is carried out in the front of said self supporting structure;
VIII, step VII write directly self supporting structure after the exposure develops, photographic fixing, obtain required limit nano-scale pattern.
2. the electron beam exposure method of the processing limit nano pattern on silicon material of insulator according to claim 1 is characterized in that: the thickness of the Si of bottom described in the step I is cut down and polishing is to utilize the mode of one of cmp or the polishing of pure physics to process.
3. the electron beam exposure method of the processing limit nano pattern on silicon material of insulator according to claim 1 is characterized in that: the thickness of among the step I said bottom Si being cut down is determined by etching barrier layer and etching mode.
4. the electron beam exposure method of the processing limit nano pattern on silicon material of insulator according to claim 1 is characterized in that: cover etching barrier layer described in the Step II and be meant and utilize plasma-reinforced chemical vapor phase epitaxial growth or thermal oxide SiO
2Layer, or directly apply photoresist.
5. the electron beam exposure method of the processing limit nano pattern on silicon material of insulator according to claim 1; It is characterized in that: the size that the Si of bottom described in the Step II I forms etching window depends on the graphics area of on top layer Si, processing; Its generation type is for directly to remove the photoresist in the window area through photoetching, or SiO in combination dry etching and the wet etching removal window area
2The etching barrier layer of type.
6. the electron beam exposure method of the processing limit nano pattern on silicon material of insulator according to claim 1 is characterized in that: adopt the mode of dark silicon ICP etching or wet etching among the step IV, and utilize buried regions SiO
2Etching from stopping property, form based on buried regions SiO
2The self supporting structure of back side deep hole and front film.
7. the electron beam exposure method of the processing limit nano pattern on silicon material of insulator according to claim 1 is characterized in that: the silicon materials described in the step I on the insulator, its top layer Si and buried regions SiO
2Gross thickness less than 10 microns.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1884043A (en) * | 2006-07-07 | 2006-12-27 | 南京大学 | Graphics compensation method for electron beam direct-writing graphics in preparation of nano dot structure |
| CN101041414A (en) * | 2006-07-25 | 2007-09-26 | 南京大学 | Method for preparing silicon nanostructure based on nonaqueous etching and wet corrosion technique |
| CN101246817A (en) * | 2008-02-29 | 2008-08-20 | 南京大学 | Method for producing silicon quantum wire on insulating layer |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1884043A (en) * | 2006-07-07 | 2006-12-27 | 南京大学 | Graphics compensation method for electron beam direct-writing graphics in preparation of nano dot structure |
| CN101041414A (en) * | 2006-07-25 | 2007-09-26 | 南京大学 | Method for preparing silicon nanostructure based on nonaqueous etching and wet corrosion technique |
| CN101246817A (en) * | 2008-02-29 | 2008-08-20 | 南京大学 | Method for producing silicon quantum wire on insulating layer |
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