CN101651116A - Method for forming contact hole - Google Patents
Method for forming contact hole Download PDFInfo
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- CN101651116A CN101651116A CN200810118409A CN200810118409A CN101651116A CN 101651116 A CN101651116 A CN 101651116A CN 200810118409 A CN200810118409 A CN 200810118409A CN 200810118409 A CN200810118409 A CN 200810118409A CN 101651116 A CN101651116 A CN 101651116A
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Abstract
The invention discloses a method for forming a contact hole. The method comprises the following steps of: providing a semiconductor structure comprising a semiconductor substrate, an electrically conducting layer, an etching blocking layer and a medium layer from the top to the bottom; carrying out first etching to the semiconductor structure by fluorine-containing first gas, and making the etching stop on the boundary between the medium layer and the etching blocking layer; carrying out second etching to the semiconductor structure by fluorine-containing second gas, and making the etching stop in the etching blocking layer; and carrying out third etching to the semiconductor structure by fluorine-containing third gas, and forming the contact hole, wherein the etching selection ratio, obtained by using the second gas for etching, of the medium layer and the etching blocking layer is larger than that obtained by using the third gas for etching, and the etching selection ratio, obtainedby using the second gas for etching, of the medium layer and the etching blocking layer is less than that obtained by using the first gas for etching. The method makes the medium layer and the etchingblocking layer fully opened and the contact hole communicated with the electrically conducting layer.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of formation method of contact hole.
Background technology
In the manufacturing technology of semiconductor device, utilize the batch process technology usually, just on semi-conductive substrate, form a large amount of various types of devices, and it is connected to each other to have complete electric function.The quality of the contact hole that forms when therefore wherein being used for interface unit directly has influence on the yield of Devices Characteristics and product.
A kind of semiconductor structure before forming contact hole comprises Semiconductor substrate, conductive layer, etching barrier layer and dielectric layer from bottom to up.When interconnecting, to dielectric layer and etching barrier layer etching, form the contact hole that connects etching barrier layer and dielectric layer, fully expose the conductive layer of contact hole bottom.In contact hole, fill metal, form plain conductor.Wherein, in to dielectric layer and etching barrier layer etch step, the ratio of the etch rate of dielectric layer and etching barrier layer is called the etching selection ratio of dielectric layer and etching barrier layer.
A kind of formation method of contact hole is in the prior art: with reference to figure 1, at first semiconductor structure 100 is carried out first etching, described first etching is to dielectric layer 106 etchings, and the etching selection ratio of this step etching medium layer 106 and etching barrier layer 104 is greater than 1; Then carry out second etching, described second etching is to etching barrier layer 104 etchings, in this step etching conductive layer 102 and the etching selection ratio of etching barrier layer 104 less than 1, thereby form the contact hole that connects at dielectric layer 106 and etching barrier layer 104.The contact hole that etching forms is tested, found the phenomenon that exists dielectric layer 106 or etching barrier layer 104 not to be fully opened.In other words, after the etching contact hole, the contact hole bottom can not expose conductive layer, thereby fills after the metal in contact hole, can not form the plain conductor of connecting conductive layer, therefore makes circuit obstructed.
In the day for announcing is on May 14th, 2008, and Granted publication number is: in the Chinese patent of CN100388437C, disclose a kind of lithographic method that is used for 0.18 micron contact hole, as shown in Figure 2, comprised the first step, top silicon oxynitride 206 is carried out etching; In second step, upper strata oxide-film 204 is carried out main etching, and append 50% over etching; The 3rd step, reaction product at the bottom of use nitrogen and the oxygen mixed gas removal hole; In the 4th step, lower floor's silicon oxynitride 202 is carried out main etching.In the said method, the second step etching fully is opened in order to guarantee oxide-film 204, requires in this step etching, and oxide-film 204 is greater than 15 with the etching selection ratio of lower floor's silicon oxynitride 102, therefore slow to the etching speed of 102 layers of lower floor's silicon oxynitrides, make that the etching efficient of this method is low.
Summary of the invention
The invention provides a kind of formation method of contact hole, make etching barrier layer and dielectric layer in the process of etching, fully are opened, make contact hole be communicated with conductive layer.
The invention provides a kind of formation method of contact hole, comprise step: semiconductor structure is provided, and described semiconductor structure comprises from bottom to up: Semiconductor substrate-conductive layer-etching barrier layer-dielectric layer; With the first fluorine-containing gas semiconductor structure is carried out first etching, etching stopping is at the intersection of dielectric layer and etching barrier layer; With the second fluorine-containing gas semiconductor structure is carried out second etching, etching stopping is in etching barrier layer; With the 3rd fluorine-containing gas semiconductor structure is carried out the 3rd etching, etching barrier layer is carved to the greatest extent, form contact hole, the bottom-exposed conductive layer of described contact hole; Wherein, during with described second gas etching greater than with the 3rd gas etching the time, the etching selection ratio of dielectric layer and etching barrier layer; And, during with described second gas etching less than with first gas etching time, the etching selection ratio of dielectric layer and etching barrier layer.
Optionally, use first gas etching, the etching selection ratio of dielectric layer and etching barrier layer is 12 to 15.
Optionally, with the 3rd gas etching, the etching selection ratio of dielectric layer and etching barrier layer is 3 to 5.
Optionally, use second gas etching, the etching selection ratio of dielectric layer and etching barrier layer is 0.5 to 1.
Optionally, second gas of described second etching comprises: difluoromethane, oxygen and nitrogen.
Optionally, the flow ratio of difluoromethane and oxygen is 1.5 to 2 in described second gas.
Optionally, pressure is 50mTorr ± 10mTorr in the reative cell of described second etching.
Optionally, the 3rd gas of described the 3rd etching comprises: difluoromethane, oxygen and argon gas.
Optionally, the flow-rate ratio of difluoromethane, oxygen and argon gas is 2: 1: 5 in described the 3rd gas.
Optionally, the material of described etching barrier layer comprises at least a or its combination in silicon nitride, silicon oxynitride, the carbonitride of silicium.
Optionally, the material of described dielectric layer comprises at least a or its combination in silica, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, black diamond, the fluorine silex glass.
The advantage of technique scheme is: the present invention adopts 3 step etchings, wherein, during with described second gas etching greater than with the 3rd gas etching the time, the etching selection ratio of dielectric layer and etching barrier layer; And during with described second gas etching less than with first gas etching time, the etching selection ratio of dielectric layer and etching barrier layer.In second etching, the dielectric layer that first etching is not fully opened fully can be opened like this, but also can continue etching to etching barrier layer, therefore reduced the possibility that dielectric layer or etching barrier layer can not be fully opened, made contact hole be communicated with conductive layer, and improved etching efficient.
Description of drawings
Fig. 1 is a kind of schematic diagram of contact hole formation method of prior art;
Fig. 2 is the flow chart of embodiment of the method for formation contact hole of the present invention;
Fig. 3 is to figure
Schematic diagram for the embodiment of the method for formation contact hole of the present invention;
Figure
For the method for utilizing conventional method to form contact hole is carried out after the etching, the end view that the contact hole on the silicon chip is tested;
Figure
Be depicted as the method for utilizing formation contact hole of the present invention and carry out after the etching, the end view that the contact hole on the silicon chip is tested.
Embodiment
Below in conjunction with accompanying drawing the specific embodiment of the present invention is described in detail.
A lot of details have been set forth in the following description so that fully understand the present invention.But the present invention can implement much to be different from alternate manner described here, and those skilled in the art can do similar popularization under the situation of intension of the present invention, so the present invention is not subjected to the restriction of following public concrete enforcement.
Secondly, the present invention utilizes schematic diagram to be described in detail, when the embodiment of the invention is described in detail in detail; for ease of explanation; the profile of expression device architecture can be disobeyed general ratio and be done local the amplification, and described schematic diagram is example, and it should not limit the scope of protection of the invention at this.The three dimensions size that in actual fabrication, should comprise in addition, length, width and the degree of depth.
In the manufacture process of semiconductor device, the formation method of existing a kind of contact hole is: at first the dielectric layer to semiconductor structure carries out first etching, and in this step etching, the etching selection ratio of dielectric layer and etching barrier layer is greater than 1; Then the etching barrier layer to semiconductor structure carries out second etching, and the etching selection ratio of conductive layer and etching barrier layer is less than 1 in this step etching.The semiconductor device that utilizes this method manufacturing is tested the phenomenon that the back discovery exists dielectric layer or etching barrier layer not to be fully opened.Think after the present inventor's research: in the method, because in second etching, the etch rate of dielectric layer and conductive layer is close, because in order conductive layer not to be caused damage, the etching selection ratio of conductive layer and etching barrier layer is less than 1 in second etching, make like this in second etching, the etching selection ratio of dielectric layer and etching barrier layer is also less than 1, if the step of first etching is not carved dielectric layer fully and is worn like this, so because in second etching, the etching selection ratio of dielectric layer and etching barrier layer is less than 1; Therefore difficult remaining dielectric layer is carved worn, and so just makes that dielectric layer or etching barrier layer are not easy to be carved to wear, thereby makes the final contact hole that forms can not be communicated with conductive layer, therefore makes that the contact hole circuit is obstructed.
Therefore the invention provides a kind of formation method of contact hole, comprise step: semiconductor structure is provided, and described semiconductor structure comprises from bottom to up: Semiconductor substrate-conductive layer-etching barrier layer-dielectric layer; With the first fluorine-containing gas semiconductor structure is carried out first etching, etching stopping is at the intersection of dielectric layer and etching barrier layer; With the second fluorine-containing gas semiconductor structure is carried out second etching, etching stopping is in etching barrier layer; With the 3rd fluorine-containing gas semiconductor structure is carried out the 3rd etching, etching barrier layer is carved to the greatest extent, form contact hole, the bottom-exposed conductive layer of described contact hole; Wherein, during with described second gas etching greater than with the 3rd gas etching the time, the etching selection ratio of dielectric layer and etching barrier layer; And, during with described second gas etching less than with first gas etching time, the etching selection ratio of dielectric layer and etching barrier layer.
Wherein, use first gas etching, the etching selection ratio of dielectric layer and etching barrier layer is 12 to 15.
Wherein, with the 3rd gas etching, the etching selection ratio of dielectric layer and etching barrier layer is 3 to 5.
Wherein, use second gas etching, the etching selection ratio of dielectric layer and etching barrier layer is 0.5 to 1.
Wherein, second gas of described second etching comprises: difluoromethane CH
2F
2, oxygen O
2And nitrogen N
2
Wherein, difluoromethane CH in described second gas
2F
2With oxygen O
2Flow ratio be 1.5 to 2.
Wherein, pressure is 50mTorr ± 10mTorr in the reative cell of described second etching.
Wherein, the 3rd gas of described the 3rd etching comprises: difluoromethane CH
2F
2, oxygen O
2And argon Ar.
Wherein, difluoromethane CH in described the 3rd gas
2F
2, oxygen O
2And the flow-rate ratio of argon Ar is 2: 1: 5.
Wherein, the material of described etching barrier layer comprises at least a or its combination among silicon nitride SiN, silicon oxynitride SiON, the carbonitride of silicium SiCN.
Wherein, the material of described dielectric layer comprises silicon oxide sio
2, at least a or its combination among phosphorosilicate glass PSG, Pyrex BSG, boron-phosphorosilicate glass PBSG, black diamond BD, the fluorine silex glass FSG.
Embodiment below in conjunction with the formation method of 2 pairs of contact holes of the present invention of accompanying drawing is described in detail.
With reference to figure 2 in the present embodiment, the formation step of contact hole comprises:
S1: semiconductor structure is provided, and described semiconductor structure comprises from bottom to up: Semiconductor substrate-conductive layer-etching barrier layer-dielectric layer.
As shown in Figure 3, described Semiconductor substrate 200 can be monocrystalline silicon, polysilicon or amorphous silicon; Described Semiconductor substrate 200 also can be silicon, germanium, GaAs or silicon Germanium compound; This Semiconductor substrate can also have epitaxial loayer or epitaxial loayer silicon-on; Described Semiconductor substrate 200 can also be other semi-conducting material, enumerates no longer one by one here.
Have conductive layer 202 on Semiconductor substrate 200, described conductive layer 202 can be the laminated construction of source area or source area and the metal silicide layer on it; It also can be the laminated construction of drain region or drain region and the metal silicide layer on it; It also can be the laminated construction of grid or grid and the metal silicide layer on it.Described metal silicide can be a kind of or its combination among nickel silicon NiSi, the cobalt silicon CoSi.Described metal silicide layer can access good low resistance contact, reduces the contact hole of interconnection structure and the contact resistance of each utmost point of transistor.
Having etching barrier layer 204 on described conductive layer 202, for example can be at least a or its combination among silicon nitride SiN, silicon oxynitride SiON, the carbonitride of silicium SiCN.This etching barrier layer 204 is fine and close usually, is used for protecting in the process of etching contact hole the conductive layer 202 of its lower floor.
Having dielectric layer 206 on described etching barrier layer 204, for example can be silicon oxide sio
2, at least a or its combination among phosphorosilicate glass PSG, Pyrex BSG, boron-phosphorosilicate glass PBSG, black diamond BD, the fluorine silex glass FSG.This dielectric layer 206 has low-k usually, is used for the insulation between the different metal layer.
Said structure can adopt those skilled in the art's technology known to form, and repeats no more here.
S2: with the first fluorine-containing gas semiconductor structure is carried out first etching, etching stopping is at the intersection of dielectric layer 206 and etching barrier layer 204.
First etching adopts dry etching.In the present embodiment, be example, semiconductor structure 200 upper stratas are applied photoresist layer (not shown) with the plasma dry etching, and graphical photoresist layer (not shown), mask pattern 208 formed.The semiconductor structure 200 that will have mask pattern 208 places in the reative cell, and when utilizing first gas to carry out first etching, dielectric layer 206 is 12 to 15 with the etching selection ratio of etching barrier layer 204, and for example 12,13 or 15.For example first etching is specially, and feeds the first fluorine-containing gas, and described first gas can be C
4F
8, O
2With the mist of Ar, also can be C
5F
8, O
2With the mist of Ar, also can be C
4F
6, O
2Mist with Ar.In the present embodiment, first gas is C
4F
6, O
2Mist with Ar.Feed C
4F
6Flow be 40sccm; Feed O
2Flow be 20sccm; The flow that feeds Ar is 800sccm.Pressure is 40mTorr in the reative cell.
During first etching, utilize radio-frequency power supply with C
4F
6, O
2With the mist ionization of Ar be plasma.First etching adopts anisotropic etching, by the electric field in the reative cell, makes the thickness direction bombardment dielectric layer 206 of the plasma of first gas along dielectric layer 206, and and dielectric layer 206 chemical reactions take place, thereby dielectric layer 206 is etched along thickness direction.Known, different semiconductor fabrication process needs the dielectric layer 206 of different-thickness, power and etch period according to the THICKNESS CONTROL etching of dielectric layer 206, therefore the thickness of dielectric layer, the power and the etch period of first etching can adopt those skilled in the art's method known to draw, and repeat no more here.
As shown in Figure 4, first etching stopping is at the intersection of dielectric layer 206 and etching barrier layer 204, and first etching can have certain error, for example keeps thin-layered medium layer 206 and carved to the greatest extent.When utilizing first gas to carry out first etching in the present embodiment, dielectric layer 206 is 12 to 15 with the etching selection ratio of etching barrier layer 204.Described etching selection ratio has guaranteed that within a short period of time, etching was finished dielectric layer 206, and because the etch rate of etching barrier layer 204 is much smaller than the etch rate of dielectric layer 206 in first etching, even therefore etching exists error also can not cause too big infringement to etching barrier layer 204.
S3: with the second fluorine-containing gas semiconductor structure is carried out second etching, etching stopping is in etching barrier layer 204.
As shown in Figure 4, second etching adopts dry etching.In the present embodiment, be example, semiconductor structure 200 is placed in the reative cell with the plasma dry etching.Described reative cell can be same reative cell with first etching, also can be the differential responses chamber, is same reative cell in the present embodiment.Utilize second gas etching in described second etching, dielectric layer 206 is 0.5 to 1 with the etching selection ratio of etching barrier layer 204, for example is 0.5,0.8 or 1.For example second etching is specially: feed difluoromethane CH
2F
2, oxygen O
2And nitrogen N
2Mist.Wherein, difluoromethane CH
2F
2With oxygen O
2The ratio of flow-rate ratio can be 1.5 to 2, for example 1.5,1.8 or 2, in the present embodiment, difluoromethane CH
2F
2, oxygen O
2, nitrogen N
2Flow-rate ratio can be 6: 3: 8, also can be 4.5: 3: 8.For example, CH
2F
2Flow be 30sccm; O
2Flow be 15sccm; N
2Flow be 40sccm.Pressure in the reative cell is 50mTorr ± 10mTorr.
During second etching, utilize radio-frequency power supply with difluoromethane CH
2F
2, oxygen O
2, nitrogen N
2Mist ionization be plasma, second etching adopts anisotropic etching, by the electric field in the reative cell, make the thickness direction bombardment etching barrier layer 204 of the plasma of second gas along etching barrier layer 204, and and etching barrier layer 204 chemical reactions take place, thereby etching barrier layer 204 is etched along thickness direction.Known, different semiconductor fabrication process needs the etching barrier layer 204 of different-thickness, power and etch period according to the THICKNESS CONTROL etching of etching barrier layer 204, therefore the thickness of etching barrier layer 204, the power and the etch period of second etching can adopt those skilled in the art's method known to draw, and repeat no more here.
As shown in Figure 5, etching stopping is in etching barrier layer 204.In the present embodiment, because when utilizing second gas to carry out second etching, dielectric layer 206 is 1 with the etching selection ratio of etching barrier layer 204.When most thin-layered medium layer 206 was not carved in existence in first etching, second etching can be effectively most 206 quarters with dielectric layer, but also can continue etchings to etching barrier layer 204.
In addition can also select in second etching, dielectric layer 206 is 0.5 to 1 with the etching selection ratio of etching barrier layer 204; Perhaps greater than with the 3rd gas etching, the etching selection ratio of dielectric layer 206 and etching barrier layer 204; Less than using first gas etching, the etching selection ratio of dielectric layer 206 and etching barrier layer 204.So both guaranteed effectively dielectric layer to be use up for 206 quarters, guaranteed to continue downward etching etching barrier layer 204 again, therefore guaranteed the efficient of etching.
S4: with the 3rd fluorine-containing gas semiconductor structure is carried out the 3rd etching, form contact hole, the bottom-exposed conductive layer 202 of contact hole.
In the present embodiment, conductive layer 202 comprises metal silicide layer 203.As shown in Figure 5, the 3rd etching adopts dry etching.In the present embodiment, be example, semiconductor structure 200 placed in the reative cell that described reative cell can be same reative cell with second etching, also can be the differential responses chamber, is same reative cell in the present embodiment with the plasma dry etching.During described the 3rd gas etching, etching barrier layer 204 is 3 with the etching selection ratio of dielectric layer 206.For example feed the 3rd fluorine-containing gas, described the 3rd gas can be difluoromethane CH
2F
2, oxygen O
2Mist with argon Ar.
In the 3rd etching, utilize radio-frequency power supply that the 3rd gas ionization is plasma, the 3rd etching adopts anisotropic etching, by electric field, makes the thickness direction etching of the plasma of the 3rd gas along etching barrier layer 204.In the present embodiment, etching barrier layer 204 lower floors have metal silicide layer 203, in described the 3rd etching, the etch rate of etching barrier layer 204 is greater than the etch rate of metal silicide layer 203, during for example described the 3rd gas etching, etching barrier layer 204 is 3 with the etching selection ratio of metal silicide layer 203.Therefore with the 3rd gas etching, the etch rate of dielectric layer 206 and metal silicide layer 203 is close, and during the 3rd etching, etching barrier layer 204 also is 3 with the etching selection ratio of dielectric layer 206.As shown in Figure 6, the 3rd etching stops at the boundary of etching barrier layer 204 and metal silicide layer 203.Because the 3rd etching, etching barrier layer 204 is 3 with metal silicide layer 203 etching selection ratio, and therefore the 3rd etching can fully be opened etching barrier layer 204, forms contact hole 210, and can not cause overetch to metal silicide layer 203.
The 3rd etching is that the gas flow of this step etching, power, etch period can adopt those skilled in the art's method known to draw, and repeat no more here with most 204 quarters to remaining etching barrier layer.
The 3rd gas etching in the present embodiment, etching barrier layer 204 is 3 to 5 with the selection ratio of metal silicide layer 203, because with the 3rd gas etching, the etch rate of dielectric layer 204 and metal silicide layer 203 is close, therefore etching barrier layer 204 is 3 to 5 with the etching selection ratio of dielectric layer 206, for example 3,4 or 5, so the 3rd gas etching, etch rate to dielectric layer 206 is lower, if dielectric layer 206 is not opened in first etching fully like this, and do not have second etching, then can influence this etch step, thereby etching barrier layer 204 can not be opened fully.And technical scheme of the present invention is because in second etching, guaranteed dielectric layer 206 is fully opened, and etching barrier layer 204 has also been carried out the etching of segment thickness, therefore just can be in the 3rd etching to the etch rate of etching barrier layer 204 greater than etch rate to metal silicide layer 203, open etching barrier layer 204 fully, and can not cause overetch metal silicide layer 203.
Figure 7 shows that and utilize conventional method to form after the contact hole, the end view that contact hole on the semiconductor structure is tested, Figure 8 shows that the method for utilizing formation contact hole of the present invention carries out after the etching, the end view that contact hole on the semiconductor structure is tested, the zone that stain among Fig. 7 and Fig. 8 is not opened for the test contact hole, the contact hole that utilizes method of the present invention to form as can be seen from Figures 7 and 8, Billy obviously rises with the qualification rate of the contact hole that conventional method forms.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (11)
1, a kind of formation method of contact hole is characterized in that, comprises step:
Semiconductor structure is provided, and described semiconductor structure comprises from bottom to up: Semiconductor substrate-conductive layer-etching barrier layer-dielectric layer;
With the first fluorine-containing gas semiconductor structure is carried out first etching, etching stopping is at the intersection of dielectric layer and etching barrier layer;
With the second fluorine-containing gas semiconductor structure is carried out second etching, etching stopping is in etching barrier layer;
With the 3rd fluorine-containing gas semiconductor structure is carried out the 3rd etching, etching barrier layer is carved to the greatest extent, form contact hole, the bottom-exposed conductive layer of described contact hole;
Wherein, during with described second gas etching greater than with the 3rd gas etching the time, the etching selection ratio of dielectric layer and etching barrier layer; And,
During with described second gas etching less than with first gas etching time, the etching selection ratio of dielectric layer and etching barrier layer.
2, the formation method of contact hole as claimed in claim 1 is characterized in that, uses first gas etching, and the etching selection ratio of dielectric layer and etching barrier layer is 12 to 15.
3, the formation method of contact hole as claimed in claim 2 is characterized in that, with the 3rd gas etching, the etching selection ratio of etching barrier layer and dielectric layer is 3 to 5.
4, the formation method of contact hole as claimed in claim 3 is characterized in that, uses second gas etching, and the etching selection ratio of dielectric layer and etching barrier layer is 0.5 to 1.
5, the formation method of contact hole as claimed in claim 1 is characterized in that, second gas of described second etching comprises: difluoromethane, oxygen and nitrogen.
6, the formation method of contact hole as claimed in claim 5 is characterized in that, the flow ratio of difluoromethane and oxygen is 1.5 to 2 in described second gas.
7, the formation method of contact hole as claimed in claim 6 is characterized in that, pressure is 50mTorr ± 10mTorr in the reative cell of described second etching.
8, the formation method of contact hole as claimed in claim 3 is characterized in that, the 3rd gas of described the 3rd etching comprises: difluoromethane, oxygen and argon gas.
9, the formation method of contact hole as claimed in claim 7 is characterized in that, the flow-rate ratio of difluoromethane, oxygen and argon gas is 2: 1: 5 in described the 3rd gas.
10, the formation method of contact hole as claimed in claim 1 is characterized in that, described etching barrier layer comprises at least a or its combination in silicon nitride, silicon oxynitride, the carbonitride of silicium.
11, the formation method of contact hole as claimed in claim 1 is characterized in that, described dielectric layer comprises at least a or its combination in silica, phosphorosilicate glass, Pyrex, boron-phosphorosilicate glass, black diamond, the fluorine silex glass.
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|---|---|---|---|
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|---|---|---|---|
| CN2008101184098A CN101651116B (en) | 2008-08-14 | 2008-08-14 | Method for forming contact hole |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101593692B (en) * | 2008-05-29 | 2011-05-04 | 中芯国际集成电路制造(北京)有限公司 | Etching method |
| CN108807209A (en) * | 2018-06-08 | 2018-11-13 | 武汉新芯集成电路制造有限公司 | A kind of the Performance Prediction model and method of contact hole |
| CN111489954A (en) * | 2019-01-25 | 2020-08-04 | 东莞新科技术研究开发有限公司 | Method for removing nitride after semiconductor substrate etching |
| CN114583013A (en) * | 2022-03-10 | 2022-06-03 | 常州时创能源股份有限公司 | BSG removing method |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100468690C (en) * | 2006-07-10 | 2009-03-11 | 中芯国际集成电路制造(上海)有限公司 | Method for reducing contact resistance in high depth ratio self alignment etching |
-
2008
- 2008-08-14 CN CN2008101184098A patent/CN101651116B/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101593692B (en) * | 2008-05-29 | 2011-05-04 | 中芯国际集成电路制造(北京)有限公司 | Etching method |
| CN108807209A (en) * | 2018-06-08 | 2018-11-13 | 武汉新芯集成电路制造有限公司 | A kind of the Performance Prediction model and method of contact hole |
| CN111489954A (en) * | 2019-01-25 | 2020-08-04 | 东莞新科技术研究开发有限公司 | Method for removing nitride after semiconductor substrate etching |
| CN114583013A (en) * | 2022-03-10 | 2022-06-03 | 常州时创能源股份有限公司 | BSG removing method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101651116B (en) | 2011-10-05 |
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