CN101640791A - Decoding method, decoding device and decoder - Google Patents
Decoding method, decoding device and decoder Download PDFInfo
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- CN101640791A CN101640791A CN200910127032A CN200910127032A CN101640791A CN 101640791 A CN101640791 A CN 101640791A CN 200910127032 A CN200910127032 A CN 200910127032A CN 200910127032 A CN200910127032 A CN 200910127032A CN 101640791 A CN101640791 A CN 101640791A
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Abstract
The invention discloses a decoding method, a decoding device and a decoder, relating to the field of video treatment, saving system hardware resources, reducing the decoding complexity by a hardware circuit and obviously enhancing the system performance. The decoding method provided by the embodiment comprises the following steps: receiving the data of an input residual matrix; decoding; and obtaining the data of an output residual matrix by two-time inverse transformation of the same type of the data of the input residual matrix and an inverse transformation matrix. The invention is suitablefor any decoding occasion by inverse integer cosine transformation.
Description
Technical field
The present invention relates to field of video processing, relate in particular to a kind of coding/decoding method, device and decoder.
Background technology
(Audio Video Coding Standard AVS) is the latest digital Audio Video coding Standard with Chinese independent intellectual property right to advanced audio/video encoding standard, has issued benchmark class (jizhunprofile) at present.The code efficiency of AVS has 2～3 times lifting than MPEG-2, apparently higher than baselineprofile H.264.In realization, the complexity of AVS encoder be H.264 70%, the complexity of decoder be H.264 30%.Widely popularize the AVS standard of Chinese independent intellectual property right, have good market prospects and researching value.
The technology of encoding and decoding in the past such as MPEG-2, usually adopt DCT (discrete cosine transform) and inverse discrete cosine transformation (IDCT), but each element of dct transform matrix all is unreasonable decimal, the phenomenon that do not match can appear in its Code And Decode, and the complexity height of floating-point operation, increased hardware cost.AVS has adopted 8 * 8 integer cosine transformation (ICT) and anti-integer cosine transformation (IICT).ICT and DCT have suitable energy compaction property, but each element of ICT transformation matrix all is an integer, so the rounding error that its inverse transformation (decode procedure) produces is little more a lot of than DCT.
According to the regulation in the AVS standard agreement, be CoeffMatrix with the input residual matrix behind the coding, transformation matrix is 8 * 8 matrix T
8Be example, decoder realizes that the process of anti-integer cosine transformation describes, and mainly comprises the steps: during to decoding
Step 1: executive level inverse transformation.According to H '=CoeffMatrix * T
8 TInput matrix is carried out the two-dimensional level inverse transformation, and decoding obtains the H ' as a result of horizontal transformation, T from the bit stream that meets AVS benchmark class
8 TBe T
8Transposed matrix;
Step 2: each coefficient among matrix H ' (result of horizontal transformation) is added 4 move to right 3 again, obtain matrix H ";
Step 3: carry out vertical inverse transformation.According to H=T
8* H ", carry out the vertical inverse transformation of two dimension, obtain inverse transformation H as a result ";
Step 4: calculate residual error sample value matrix R.
According to r
Ij=(h
Ij+ 2
6The element h that)＞＞7 obtains among the matrix R
Ij, i wherein, j=0..7.
Yet, in realizing process of the present invention, the inventor finds that there are the following problems at least in the prior art: when prior art is stated decode procedure in realization, deeply do not consider the internal characteristics of the anti-integer cosine transformation of AVS, decoder needs two types circuit simultaneously, one in order to realizing above-mentioned horizontal inverse transformation process, and one in order to realize above-mentioned vertical inverse transformation process, taken too much hardware resource; And decoder is directly carried out the two-dimensional matrix conversion of twice complexity, and the implementation complexity of hardware circuit is higher, the speed of service is low, and systematic function is relatively poor.
Summary of the invention
For solving problems of the prior art, embodiments of the invention provide a kind of coding/decoding method, device and decoder, are used to save system hardware resources, reduce hardware circuit and realize complexity of decoding, significantly improve systematic function.
For achieving the above object, embodiments of the invention adopt following technical scheme:
Embodiments of the invention provide a kind of coding/decoding method, and described method comprises:
Obtain intermediary matrix according to the input residual matrix that receives;
Utilize described intermediary matrix and inverse transformation matrix by carrying out the inverse transformation of twice same type, decoding obtains the data of output residual matrix.
Further, also comprise:
With the parallel vectorial X of row that is converted to of the serial data of described input residual matrix
m, described row vector constitutes described intermediary matrix; Wherein, X is the label of row vector, and the m value is a positive integer.
Further, comprising: the parallel vectorial C of row that is converted to of the serial data of described inverse transformation matrix
mUtilize the vectorial X of described row
mAnd C
m, according to the displacement addition rule that described alternative types is scheduled to, carry out inverse transformation for the first time, obtain first result, this first result is for comprising the vectorial Y of row
mMatrix;
Utilize described first result and C
m, according to the displacement addition rule that described alternative types is scheduled to, carry out inverse transformation for the second time, obtain the data of described output residual matrix.
Further, the inverse transformation of described same type comprises horizontal inverse transformation or vertical inverse transformation.
Embodiments of the invention provide a kind of decoding device, and described device comprises:
Acquiring unit is used for obtaining intermediary matrix according to the input residual matrix that receives; The inverse transformation unit, the intermediary matrix and the inverse transformation matrix that are used to utilize described acquiring unit to get access to obtain to export the data of residual matrix by carrying out the inverse transformation of twice same type, decoding.
Further, described acquiring unit comprises:
String and modular converter are used for being converted to 8 vectorial X of row with the serial data of described input residual matrix is parallel
m, described row vector constitutes described intermediary matrix; Wherein, X is the label of row vector, and the m value is a positive integer.
Embodiments of the invention provide a kind of decoder, and described decoder comprises:
String changes and processing module, is used for the parallel row vector that is converted to of the serial data of input residual matrix;
The inverse transformation logical block is used to utilize described capable vector sum inverse transformation matrix by carrying out the inverse transformation of twice same type, and decoding obtains the data of output residual matrix.
Further, described decoder also comprises: post-processing module is used for carrying out first reprocessing after described inverse transformation logical block executes the inverse transformation first time; After described inverse transformation logical block executes the inverse transformation second time, carry out second reprocessing;
The transposition module after being used for result to the reprocessing for the first time of described post-processing module and carrying out transposition, is sent data into described inverse transformation logical block.
Described inverse transformation logical block, the data and the inverse transformation matrix that also are used to utilize described transposition module to send are carried out inverse transformation for the second time, and decoding obtains the output residual matrix.
The technical scheme that the embodiment of the invention provides, by analysing in depth the internal characteristics of the anti-integer cosine transformation of AVS, the data of output residual matrix are obtained in utilization by the inverse transformation of carrying out twice same type with a kind of circuit, saved the hardware resource of system greatly, and when decoder is carried out the two-dimensional matrix conversion, utilize predetermined displacement addition rule to realize, significantly reduced the complexity when utilizing hardware circuit to realize decoding, improved systematic function by the displacement addition of several times fixed coefficient.
Description of drawings
The coding/decoding method schematic flow sheet that Fig. 1 provides for the embodiment of the invention;
The data read mode schematic diagram that Fig. 2 provides for the embodiment of the invention;
The decoding device structural representation that Fig. 3 provides for the embodiment of the invention;
A kind of decoder implementation structural representation that Fig. 4 provides for the embodiment of the invention.
Embodiment
In order to be illustrated more clearly in the technical scheme of the embodiment of the invention, below in conjunction with accompanying drawing embodiments of the invention are described in detail, following description only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other execution mode of the present invention according to these embodiment.
The technical scheme that the embodiment of the invention provides, by analysing in depth the internal characteristics of the anti-integer cosine transformation of AVS, in decode procedure, conversion of the prior art two types is converted to twice conversion of same type to be realized, decoder is mainly realized two-dimentional anti-integer cosine transformation by an identical one dimension ICT computing unit and a transposition conversion memory cell, by the time division multiplexing of this ICT computing unit, utilize the displacement addition of the several times fixed coefficient of one dimension to realize the conversion of the above-mentioned type.
Below in conjunction with example the embodiment of the invention is specifically described.
For the clear technical scheme of understanding the embodiment of the invention, at first the technical characterictic of ICT is analysed in depth.Horizontal transformation and vertical conversion in the knot background technology can draw following formula:
If CoeffMatrix carries out transposition to the input residual matrix, and makes M=CoeffMatrix
T, then transformation for mula (1-1) can be write as:
H＝T
8×(T
8×M).
T (1-2)
Perhaps write as,
H＝(M×T
8 T).
T×T
8 T (1-3)
As seen, the two-dimensional matrix conversion among the ICT can for example, can utilize the same matrix T of input residual matrix premultiplication by the inverse transformation (horizontal inverse transformation or vertical inverse transformation) of twice one dimension
8Realize or utilize the input residual matrix right side to take advantage of same matrix T
8 TRealize.
As shown in Figure 1, the coding/decoding method that provides of the embodiment of the invention comprises:
Step T1: the data that receive the input residual matrix;
The data of the input residual matrix that flowing water is come in the system are the inputs of a pixel of a pixel of serial, also receive one by one during reception, and for improving data processing efficiency, the embodiment of the invention also comprises:
With the parallel vectorial X of row that is converted to of the serial data of described input residual matrix
mWherein, X is the label of row vector, and m is the sequence number of row vector, and m is a positive integer, and the value of m is 0 to 7.
With the serial data of input residual matrix earlier string change and become the parallel data of one group of 8 pixel, just input matrix row vector.
Should be noted that in embodiments of the present invention referring to Fig. 2, system when sending to decoder, has adopted a kind of special mode that reads at the pixel value that reads the storage of coding back.RAM memory with 8*8 among Fig. 2 is that example describes, write sequence when the solid arrow of level is depicted as storage pixel, order when vertical dotted arrow is depicted as read pixel, by this order that writes and read, the data that make the input residual matrix that receives are above-mentioned CoeffMatrix transpose of a matrix.
Step T2: utilize the data of described input residual matrix and inverse transformation matrix to obtain to export the data of residual matrix by carrying out the inverse transformation of twice same type, decoding.
By above-mentioned string and conversion, utilize the vectorial X of described row among the step T2 to input residual matrix data
mObtain to export residual matrix with the inverse transformation matrix by carrying out the inverse transformation of twice same type, decoding.
Adopting following formula (1-2) below, is that example illustrates technical scheme of the present invention to carry out two sub-level inverse transformations.
In formula (1-2), in the computing of input residual matrix and inverse transformation matrix, can carry out following processing:
Y
n＝∑∑C
mX
m n，m＝0，...，7
Wherein, X
mBe the row vector of the input residual matrix that gets access among the step T1, Y
nBe operation result matrix, C
mBe matrix inverse transformation matrix T
8Row vector, Y, C are respectively the label of its corresponding line vector, T in the embodiment of the invention
8Be taken as:
First row vector to the operation result matrix has:
Y
0＝8X
0+10X
1+10X
2+9X
3+8X
4+6X
5+4X
6+2X
7
＝[(8X
0+8X
4)+(10X
2+4X
6)]+[(10X
1+6X
5)+(9X
3+2X
7)]
＝[Z
0+Z
6]+[Z
2+Z
8]
To 8 vectorial Y of row
0～Y
7All according to said method handle, can obtain 12 kinds of similar group item Z
0～Z
11:
Z
0＝8X
0+8X
4＝(X
0＜＜3)+(X
4＜＜3)；
Z
1＝8X
0-8X
4＝(X
0＜＜3)-(X
4＜＜3)；
Z
2＝10X
1+6X
5＝[(X
1＜＜3)+(X
1＜＜1)]+[(X
5＜＜2)+(X
5＜＜1)]；
Z
3＝9X
1-10X
5＝[(X
1＜＜3)+X
1]-[(X
5＜＜3)+(X
5＜＜1)]；
Z
4＝6X
1+2X
5＝[(X
1＜＜2)+(X
1＜＜1)]+(X
5＜＜1)；
Z
5＝2X
1+9X
5＝(X
1＜＜1)+[(X
5＜＜3)+X
5]；
Z
6＝10X
2+4X
6＝[(X
2＜＜3)+(X
2＜＜1)]+(X
6＜＜2)；
Z
7＝4X
2-10X
6＝(X
2＜＜2)-[(X
6＜＜3)+(X
6＜＜1)]；
Z
8＝9X
3+2X
7＝[(X
3＜＜3)+X
3]+(X
7＜＜1)；
Z
9＝2X
3+6X
7＝(X
3＜＜1)+[(X
7＜＜2)+(X
7＜＜1)]；
Z
10＝10X
3-9X
7＝[(X
3＜＜3)+(X
3＜＜1)]-[(X
7＜＜3)+X
7]；
Z
11＝6X
3+10X
7＝[(X
3＜＜2)+(X
3＜＜1)]+[(X
7＜＜3)+(X
7＜＜1)]；
For further being convenient to handle, simplify the operation, 8 intermediate variable W are set
0～W
7:
W
0＝Z
0+Z
6；W
1＝Z
2+Z
8；W
2＝Z
1+Z
7；W
3＝Z
3-Z
9；
W
4＝Z
1-Z
7；W
5＝Z
4-Z
10；W
6＝Z
0-Z
6；W
7＝Z
5-Z
11。
The vectorial Y of the operation result matrix that finally obtains
0～Y
7Can be expressed as:
Y
0＝W
0+W
1；Y
1＝W
2+W
3；Y
2＝W
4+W
5；Y
3＝W
6+W
7；
Y
4＝W
6-W
7；Y
5＝W
4-W
5；Y
6＝W
2-W
3；Y
7＝W
0-W
1。
Convert the two-dimensional matrix computing of complexity to some displacement add operations by above-mentioned processing, when utilizing hardware circuit to realize, significantly reduced computational complexity.
In step T2, with the parallel vectorial C of row that is converted to of the serial data of described inverse transformation matrix
m, utilize the vectorial X of described row
mAnd C
m,, carry out inverse transformation according to the displacement addition rule that described alternative types is scheduled to.Above-mentioned processing procedure has been described when change type is horizontal inverse transformation, definite method of described predetermined displacement addition rule.Conspicuous, predetermined displacement addition rule in the time of can utilizing same processing method to determine that alternative types is vertical inverse transformation.
Step T2 can specifically comprise the steps:
Step T21: utilize the vectorial X of described row
mAnd C
m, according to the displacement addition rule that described alternative types is scheduled to, carry out inverse transformation for the first time, obtain first result.
Still, after the execution inverse transformation first time, obtain this first result for comprising 8 vectorial Y of row with above-mentioned example explanation
0～Y
7Matrix.
Step T22: to the vectorial Y of described row
mCarry out first reprocessing;
First reprocessing here comprises the vectorial Y of each row among first result
mDisplacement and clamper, as going vectorial Y
mIn each coefficient add 4 and move to right 3 again.
Step T23: will be through the Y after first reprocessing
mCarry out transposition respectively;
The concrete processing mode of this transposition computing can be referring to transposition conversion read-write mode shown in Figure 2, according to this read-write mode, by the transposition of memory realization matrix data.
Step T24: utilize the Y behind the transposition
mAnd C
m, according to the displacement addition rule that described alternative types is scheduled to, carry out inverse transformation for the second time, obtain second result;
Here, it is identical with mode among the step T21 to carry out the mode of inverse transformation among the step T24, promptly with same circuit by time division multiplexing, can realize the main matrix operation process of ICT.
Step T25: described second result is carried out second reprocessing, obtain described output residual matrix.
Second reprocessing also relates to displacement and clamper is handled, and for example, each element among second result is added 2
6Move to right 7 again.
The final decoding of the processing of the step that process is above-mentioned finishes and has got access to the output residual matrix.
The technical scheme that the embodiment of the invention provides, by analysing in depth the internal characteristics of the anti-integer cosine transformation of AVS, the data of output residual matrix are obtained in utilization by the inverse transformation of carrying out twice same type with a kind of circuit, saved the hardware resource of system greatly, and when decoder is carried out the two-dimensional matrix conversion, utilize predetermined displacement addition rule to realize, significantly reduced the complexity when utilizing hardware circuit to realize decoding, improved systematic function by the displacement addition of several times fixed coefficient.
The embodiment of the invention also provides a kind of decoding device, and as shown in Figure 3, described device comprises:
Receiving element 31 is used to receive the data of importing residual matrix;
Inverse transformation unit 32 is used to utilize the data of the input residual matrix that described receiving element 31 receives and inverse transformation matrix by carrying out the inverse transformation of twice same type, and decoding obtains the data of output residual matrix.
Further, described device also comprises:
String and converting unit 33 are used for the parallel vectorial X of row that is converted to of the serial data of described input residual matrix
m, wherein, m is the label of row vector, m is a positive integer;
Described inverse transformation unit 32 is used to utilize the vectorial X of described row
mObtain to export the data of residual matrix with the inverse transformation matrix by carrying out the inverse transformation of twice same type, decoding.
The specific implementation of each functional module is referring to method embodiment of the present invention in the said apparatus.
Said apparatus utilizes inverse transformation unit 32 to obtain the data of output residual matrix by the inverse transformation of carrying out twice same type, saved the hardware resource of system greatly, and when inverse transformation unit 32 carries out each inverse transformation, utilize predetermined displacement addition rule to realize by the displacement addition of several times fixed coefficient, significantly reduced and utilized hardware circuit to realize complexity of decoding, improved systematic function.
The embodiment of the invention also provides a kind of decoder, and as shown in Figure 4, described decoder comprises:
String changes and processing module (as the S2P module), is used to receive the serial data of input residual matrix and this data parallel is converted to the row vector; Inverse transformation logical block (as the IICT-PROC module) is used to utilize described string changes and processing module obtains capable vector sum inverse transformation matrix by carrying out the inverse transformation of twice same type, and decoding obtains to export residual matrix.
Further, described decoder also comprises:
Post-processing module (as the POST-PROC module) is used for carrying out first reprocessing after described inverse transformation logical block executes the inverse transformation first time; After described inverse transformation logical block executes the inverse transformation second time, carry out second reprocessing;
Transposition module (as the TRANS-MEM module) is used for the result of described post-processing module reprocessing is for the first time carried out transposition.
Described inverse transformation logical block also is used to utilize the result of described transposition module and inverse transformation matrix to carry out inverse transformation for the second time, and decoding obtains the output residual matrix.
Referring to Fig. 4, the S2P module is that string changes and processing module, is responsible for the data of transmitting the picture element matrix that comes from a last processing unit in the AVS system being gone here and there and changing, and the output resultant string changes and data (s2p-data), to carry out matrix operation more efficiently;
Data multiplex (DATA_MUX) module is a control module, can be according to the difference of the enable signal of system, and decision IICT-PROC module is current, and what do is inverse transformation or inverse transformation (twice corresponding different last handling process of inverse transformation) for the first time for the second time;
When the DATA_MUX module determines that current what do is for the first time during inverse transformation to the IICT-PROC module, send instruction (as mux_data), control POST_PROC module receives the result (as iict_proc) of inverse transformation for the first time, this result is carried out first reprocessing to be obtained back result data (post-data) and delivers to the TRANS_MEM module, the TRANS_MEM module is advanced RAM with the post-data storage and is carried out transpose process, carries out the inverse transformation second time by the IICT-PROC module then.
When the DATA_MUX module determines that current what do is for the second time during inverse transformation to the IICT-PROC module, control POST_PROC module receives the result of inverse transformation for the second time, this result is carried out second reprocessing, and output obtains the data (as res_data) of decoded output residual matrix then.
The technical scheme that the embodiment of the invention provides, by analysing in depth the internal characteristics of the anti-integer cosine transformation of AVS, utilization is obtained the output residual matrix with a kind of circuit by the inverse transformation of carrying out twice same type, saved the hardware resource of system greatly, and when decoder is carried out the two-dimensional matrix conversion, utilize predetermined displacement addition rule to realize, significantly reduced and utilized hardware circuit to realize complexity of decoding, improved systematic function by the displacement addition of several times fixed coefficient.
The coding/decoding method that the embodiment of the invention provides, device and decoder, but the video ES of real-time decoding AVS second portion benchmark class stream.By practical proof, can reach desirable effect.And, be easy to be integrated in the AVS high definition decoder because implementation is simple.This technical scheme has been passed through the test of the announced uniformity test code stream of AVS working group, has error detection mechanism, and stable performance is efficient, and is very convenient in the system integration.
One of ordinary skill in the art will appreciate that all or part of step that realizes in the foregoing description, can finish by the program command related hardware.The software of described embodiment correspondence can be stored in a computer and can store in the medium that reads.
The above; only be the specific embodiment of the present invention, but protection scope of the present invention is not limited thereto, anyly is familiar with those skilled in the art in the technical scope that the present invention discloses; can expect easily changing or replacing, all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection range of claim.
Claims (10)
1, a kind of coding/decoding method is characterized in that, described method comprises:
Receive the data of input residual matrix;
Utilize the data and the inverse transformation matrix of described input residual matrix to obtain to export the data of residual matrix by carrying out the inverse transformation of twice same type, decoding.
2, method according to claim 1 is characterized in that, also comprises after the data that receive the input residual matrix:
With the parallel vectorial X of row that is converted to of the serial data of described input residual matrix
m, wherein, X is the label of this row vector, m is a positive integer;
Utilize the vectorial X of described row
mObtain to export the data of residual matrix with the inverse transformation matrix by carrying out the inverse transformation of twice same type, decoding.
3, method according to claim 2 is characterized in that, utilizes the vectorial X of described row
mComprise by carrying out the inverse transformation of twice same type, decode the data that obtain the output residual matrix with the inverse transformation matrix:
With the parallel vectorial C of row that is converted to of the serial data of described inverse transformation matrix
m, C is the label of this row vector;
Utilize the vectorial X of described row
mAnd C
m, the displacement addition rule of being scheduled to according to described alternative types is carried out inverse transformation for the first time, obtains first result, this first result vectorial Y of row that serves as reasons
mThe matrix that constitutes, wherein, Y is the label of this row vector;
Utilize described first result and C
m, according to the displacement addition rule that described alternative types is scheduled to, carry out inverse transformation for the second time, obtain the data of described output residual matrix.
4, method according to claim 3 is characterized in that, utilizes described first result and C
m, according to the displacement addition rule that described alternative types is scheduled to, carry out inverse transformation for the second time, the data of obtaining described output residual matrix comprise:
To the vectorial Y of described row
mCarry out first reprocessing;
Will be through the Y after first reprocessing
mCarry out transposition respectively;
Utilize the Y behind the transposition
mAnd C
m, according to the displacement addition rule that described alternative types is scheduled to, carry out inverse transformation for the second time, obtain second result;
Described second result is carried out second reprocessing, obtain the data of described output residual matrix.
According to the arbitrary described method of claim 1 to 4, it is characterized in that 5, the inverse transformation of described same type comprises horizontal inverse transformation or vertical inverse transformation.
6, a kind of decoding device is characterized in that, described device comprises:
Receiving element is used to receive the data of importing residual matrix;
The inverse transformation unit is used to utilize the data of the input residual matrix that described receiving element receives and inverse transformation matrix by carrying out the inverse transformation of twice same type, and decoding obtains the data of output residual matrix.
7, device according to claim 6 is characterized in that, described device also comprises:
String and converting unit are used for the parallel vectorial X of row that is converted to of the serial data of described input residual matrix
m, wherein, X is the label of row vector, m is a positive integer;
Described inverse transformation unit is used to utilize the vectorial X of described row
mObtain to export the data of residual matrix with the inverse transformation matrix by carrying out the inverse transformation of twice same type, decoding.
8, a kind of decoder is characterized in that, described decoder comprises:
String changes and processing module, is used to receive the serial data of input residual matrix and this data parallel is converted to the row vector;
The inverse transformation logical block is used to utilize described string changes and processing module obtains capable vector sum inverse transformation matrix by carrying out the inverse transformation of twice same type, and decoding obtains to export the data of residual matrix.
9, decoder according to claim 8 is characterized in that, also comprises:
Post-processing module is used for carrying out first reprocessing after described inverse transformation logical block executes the inverse transformation first time; After described inverse transformation logical block executes the inverse transformation second time, carry out second reprocessing;
The transposition module after being used for result to the reprocessing for the first time of described post-processing module and carrying out transposition, is sent data into described inverse transformation logical block.
10, decoder according to claim 9 is characterized in that, also comprises:
Described inverse transformation logical block, the data and the inverse transformation matrix that also are used to utilize described transposition module to send are carried out inverse transformation for the second time, and decoding obtains the data of output residual matrix.
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| CN102256120A (en) * | 2010-05-20 | 2011-11-23 | 炬力集成电路设计有限公司 | Integer inverse transformation device for video decoding |
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| CN106254883A (en) * | 2016-08-02 | 2016-12-21 | 青岛海信电器股份有限公司 | Inverse transform method in the decoding of a kind of video and device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102256120A (en) * | 2010-05-20 | 2011-11-23 | 炬力集成电路设计有限公司 | Integer inverse transformation device for video decoding |
| CN102256120B (en) * | 2010-05-20 | 2013-05-08 | 炬力集成电路设计有限公司 | Integer inverse transformation device for video decoding |
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| CN105516730A (en) * | 2014-09-24 | 2016-04-20 | 晨星半导体股份有限公司 | Video signal coding device and method and video signal decoding device and method |
| CN105516730B (en) * | 2014-09-24 | 2018-04-24 | 晨星半导体股份有限公司 | Video coding device and video decoded device and its coding and coding/decoding method |
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| CN106254883B (en) * | 2016-08-02 | 2021-01-22 | 海信视像科技股份有限公司 | Inverse transformation method and device in video decoding |
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