WO2020060832A1

WO2020060832A1 - Fast implementation of odd one dimensional transforms

Info

Publication number: WO2020060832A1
Application number: PCT/US2019/050759
Authority: WO
Inventors: Karam NASER; Gagan Rath; Edouard Francois
Original assignee: Interdigital Vc Holdings, Inc.
Priority date: 2018-09-17
Filing date: 2019-09-12
Publication date: 2020-03-26

Abstract

Methods and apparatus for fast implementation of odd one-dimensional transforms are implemented by performing matrix multiplication and matrix additions based on Discrete Trigonometric Transforms decomposition of a transform into smaller sub- transforms. In one embodiment, for real valued input values when only real valued coefficients are required, the number of operations can be reduced through decomposition. In another embodiment, for complex valued inputs when imaginary outputs are required, transforms are implemented using additions.

Description

FAST IMPLEMENTATION OF ODD ONE DIMENSIONAL TRANSFORMS

TECHNICAL FIELD

At least one of the present embodiments generally relates to a method or an apparatus for video encoding or decoding, compression or decompression.

BACKGROUND

To achieve high compression efficiency, image and video coding schemes usually employ prediction, including motion vector prediction, and transform to leverage spatial and temporal redundancy in the video content. Generally, intra or inter prediction is used to exploit the intra or inter frame correlation, then the differences between the original image and the predicted image, often denoted as prediction errors or prediction residuals, are transformed, quantized, and entropy coded. To reconstruct the video, the compressed data are decoded by inverse processes corresponding to the entropy coding, quantization, transform, and prediction.

In addition to the core transform of DCT-II, additional transforms are adopted in advanced compression software to improve the coding performance. These transforms usually include some of the odd-types of Discrete Trigonometric Transforms.

SUMMARY

At least one of the present embodiments generally relates to a method or an apparatus for video encoding or decoding, and more particularly, to a method or an apparatus for reducing the number of operations for a video encoder or a video decoder.

According to a first aspect, there is provided a method. The method comprises steps for performing at least a portion of a Discrete Trigonometric Transform on a subset of samples comprising a block; determining transform coefficients for the block using the transformed subset of samples; and, encoding the block.

According to a second aspect, there is provided a method. The method comprises steps for performing at least a portion of an inverse Discrete Trigonometric Transform on a subset of coefficients comprising a block; determining samples for the block using the inverse transformed subset of coefficients; and, decoding the block.

According to another aspect, there is provided an apparatus. The apparatus comprises a processor. The processor can be configured to encode a block of a video or decode a bitstream by executing any of the aforementioned methods. According to another general aspect of at least one embodiment, there is provided a device comprising an apparatus according to any of the decoding embodiments; and at least one of (i) an antenna configured to receive a signal, the signal including the video block, (ii) a band limiter configured to limit the received signal to a band of frequencies that includes the video block, or (iii) a display configured to display an output representative of a video block.

According to another general aspect of at least one embodiment, there is provided a non-transitory computer readable medium containing data content generated according to any of the described encoding embodiments or variants.

According to another general aspect of at least one embodiment, there is provided a signal comprising video data generated according to any of the described encoding embodiments or variants.

According to another general aspect of at least one embodiment, a bitstream is formatted to include data content generated according to any of the described encoding embodiments or variants.

According to another general aspect of at least one embodiment, there is provided a computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out any of the described decoding embodiments or variants.

These and other aspects, features and advantages of the general aspects will become apparent from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 shows an example of prime factor decomposition of DFT of size 2N+1 into N1xN2.

Figure 2 shows an example prime factoring scheme for DCT-VI of size N+1 , where it is decomposed into N1xN2=2N+1 .

Figure 3 shows a prime factoring scheme for DCT-VIII of size N, where it is decomposed into N1xN2=2N+1.

Figure 4 shows a Cooley-Tuckey algorithm for decomposing N length DFT into N1 and N2 DFTs.

Figure 5 shows an example of decomposing DCT-VI of size 32 using Cooley- Tuckey algorithm into 9x7 DFTs, where gray indicates non-zero matrix inputs. Figure 6 shows an example of decomposing DCT-VI of size 32 using Cooley- Tuckey algorithm into 9x7 DFTs, where gray indicates the required output coefficients.

Figure 7 shows an example Cooley-Tuckey algorithm for decomposing N+1 DCT- VI into N1 and N2 DFTs.

Figure 8 shows an example Cooley-Tuckey algorithm for decomposing N DCT-VIII into N1 and N2 DFTs.

Figure 9 shows a standard, generic video compression scheme

Figure 10 shows a standard, generic video decompression scheme.

Figure 1 1 shows an example processor-based subsystem for implementation of general described aspects.

Figure 12 shows one embodiment of a method under the described aspects.

Figure 13 shows another embodiment of a method under the described aspects.

Figure 14 shows an example apparatus under the described aspects.

DETAILED DESCRIPTION

The general aspects described here are in the field of video compression. These aspects are related to transform coding where the enhanced multiple transforms could be used.

In addition to the core transform of DCT-II, additional transforms are adopted in JVET/BMS software to improve the coding performance. These transforms usually include some of the odd-types of Discrete Trigonometric Transforms (DCT-V to DCT-VIII and DST-V to DST-VIII).

Currently, these transforms are implemented by the means of matrix multiplication. However, fast algorithms exist to reduce the number of operations (multiplications, additions and shifts). The adoption of an algorithm for fast implementation can also be driven by its impact on hardware/software complexity. For example, a transform with a few multiplications could be less favored than the one that has larger number of multiplications but implementable with SMID. This is the case for current DCT-II design, that employs a partial butterfly rather than a complete decomposition, to be more hardware/software friendly. At least one of the general aspects described herein enables both reducing the number of operations, as well as enabling SMID computation. It is based on DFT representation of odd-type Discrete Trigonometric Transforms (DTT), where DFT can be decomposed into multiple sub-DFT’s, using prime-factor algorithm or Cooley-Tuckey algorithm, and a matrix multiplication is enabled.

Computing the forward/inverse transform is a task that requires several mathematical operations that are exponentially proportional to transform block size. In the encoder side, several candidate transform pairs are tested to search for the best rate- distortion trade-off. On the decoder side, the inverse transform is employed to recover the residual signal. Thus, fast algorithms are substantially required for both the encoder and decoder side.

In comparison to DCT-II, the new transforms used in the EMT do not have the butterfly decomposition. In addition, little is known about their fast implementation. In the prior art, some algorithms are proposed to reduce the number of operations, but usually they are associated with increased design complexity, because of the complexity of the algorithms themselves. Additionally, each transform size has a different algorithm, which leads to inhomogeneous design of the transform coding process. This is totally the opposite of partial butterfly implementation of DCT-II that is unified for all transform sizes. Thus, it is currently preferred having a matrix multiplication-based approach in order to have a unified implementation.

At least one of the proposed aspects described is a unified one, where only matrix multiplication and matrix addition algorithms are needed. This is based on the DFT decomposition of the transform into smaller sub-transforms.

Concerning DST -VI l/DCT -VI 11 , there are currently two main proposals for the fast implementation of DST-VIII/DCT-VII. The first one is based on the properties of the DST- VII transform matrix. It has been identified that some matrix elements can be computed as the sum of others. There are also some repeated patterns and vectors with a single element that varies with positive and negative signs. Using these properties, the number of operations can be highly reduced.

The second approach, which is based on representing DST-VII of size N by a 2N+1 DFT, and then deriving the optimal design for DFT using prime factor algorithm. For DST- VII sizes of 16 and 32, DFT of 33 and 65 are used, which are decomposed into 3x1 1 and 5x13 FFT respectively. DCT-V, on the other hand, has witnessed less focus. Nevertheless, a method was presented to compute DCT-V for sizes 4x4 and 8x8. This is based on representing DCT- V by a DFT of size 2N-1 (7-point DFT and 15-point DFT resp.) and the fast DFT is then performed.

A 2N+1 DCT-II can be decomposed into N+1 DCT-VI and N DCT-VIII. This can be illustrated with the example given below (for 9-DCT-ll, neglecting the normalization factor):

Table 1 An unnormalized DCT-II matrix of size 9x9, where the DCT-IV of 5x5 and DCT-VIII of size 4x4 are already available in bold and italic font (resp.).

Mathematically, this can be expressed as follow. Define two matrices, / and F, for identity and flipping matrix, respectively, where / contains only 1’s in its diagonal coefficients, while F contains 1’s in its antidiagonal coefficients, the rest are zero. Let DCT-II_2JV+_I be the DCT-II matrix of size 2N+1 , DCT-Vl^^and DCT-Vlll_jv be the matrix of DCT-VI and DCT-VIII of sizes N+1 and N respectively. Then, the relationship can be expressed as:

Where R is a matrix to arrange the resulting coefficients, such that: i is odd and j = i

s even and j=i + N

0 else

Accordingly, the fast implementation of DCT-VI or DCT-VIII is based on the fast implementation of DCT-II of size 2N+1. That is, a fast algorithm for odd-length of DCT-II is used to derive the fast algorithm of DCT-VI or DCT-VIII. From such an algorithm, the DCT-VI transform corresponds to computing the odd-ordered coefficient, while the even ordered coefficients correspond to DCT-VIII. In addition, the other types of DCT and DST transforms of odd lengths (V, VI, VI I & VIII) can be obtained by the simple relationships between them. This is illustrated in Table 2. Thus, the derivation of the algorithms for DCT-VI and DCT-VIII implicitly involves the derivation of other transforms.

Table 2 Intrinsic relationships between odd DCT/DST transforms

The fast algorithm of odd length DCT-I I is based on the fast algorithm of DFT of the same length. Mathematically, the relation between them is expressed as follows:

Where H₂ and

are permutation and sign changing matrices, and

Re(FFT)_N+1 and Im(DFT)_N are the first (N+1 )x(N+1 ) and first NxN (excluding the zeros) of real and imaginary coefficients of DFT matrix. For example, for N=4, gives the following values:

H₂ = [

1 0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 0 -1

0 -1 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1 0

0 0 1 0 0 0 0 0 0

0 0 0 0 0 0 -1 0 0

0 0 0 -1 0 0 0 0 0

0 0 0 0 0 1 0 0 0

0 0 0 0 1 0 0 0 0

]

H =[

0 0 0 0 1 0 0 0 0

0 0 0 1 0 1 0 0 0

0 0 1 0 0 0 1 0 0

0 1 0 0 0 0 0 1 0

1 0 0 0 0 0 0 0 1

0 0 0 1 0 -1 0 0 0

0 0 -1 0 0 0 1 0 0

0 1 0 0 0 0 0 -1 0

-1 0 0 0 0 0 0 0 1

Then, mapping the two equations, generates the following equation for computing DCT-VI and DCT-VIII from DFT as follows:

DCT-VI_W+1 = R_n+1 X Re(DFT_2N+1)_N+1 ^x ^N+I

In summary, computing DCT-VI of size N+1 comprises the following steps:

1. Flipping the input vector, and append the resulting vector with N zeros

2. Performing real DFT transform of the first N+1 basis functions

3. Reversing the sign of the odd-ordered resulting coefficients Whereas DCT-VIII comprises the following steps:

1. Flipping the input vector and reversing the sign of odd-ordered samples.

2. Performing an imaginary DFT transform for the first N basis functions (excluding the first zero basis function)

3. Reversing the sign of odd-ordered coefficients and flipping the order.

Performing a DFT can be made faster by utilizing some fast algorithms. Namely, the prime factor algorithm is considered here, where the N DFT is decomposed into N1xN2 sub- DFT’s so that the overall number of operations are reduced. N1 and N2 should be relatively prime, i.e. the only common divisor between N1 and N2 is one. The decomposition is illustrated in Figure 1 , in which the input samples are permuted such that they are stored in an N2xN1 matrix. Then, N2-times DFT(N1 ) processes are performed in the row direction, and N1 -times DFT(N2) processes are performed on the column direction. The output coefficients are then permuted to extract the coefficients array.

For length N+1 DCT-VI, the same structure is used. However, the pre-processing and post-processing is required (F and R matrices). In addition, the input for 2N+1 length DFT is real data. Thus, the first level of DFT is reduced to real in DFT (DFT_RI in Figure 2). For real input DFT, the second half of the output coefficients are simply the complex conjugate of the first ones. For example, when taking DFT of size N1 of the array N2xN1 in a row-wise manner, the last half of the columns (N 1 th column to 2N column) are redundant. Thus, the second level of DFT (column-wise) will consider only the first N1 (0: N 1 -1 ) rows and neglect the rest.

Furthermore, only the real output coefficients are required, this makes the second level DFT for real output coefficients only (DFT_RO in Figure 2). To further reduce the number of operations, the input of the first DFT of the second level is real data, this reduces the computation to a DFT of real input imaginary output data (DFT_RI_RO in Figure 2).

Like DCT-VI, DCT-VIII of length N requires a DFT of 2N+1 with preprocessing and post processing (R and F matrices). The output is only required for imaginary data. This requires the implementation of DFT for real input (DFT_RI), DFT for imaginary output (DFT_RO) and DFT for real input and imaginary output (DFT_RI_IO). The corresponding structure is provided in Figure 3. When the decomposition is not achievable with two prime numbers, the Cooley- Tuckey algorithm can also be used. The Cooley Tuckey algorithm can decompose an DFT of length N into N1 and N2 DFT’s when N1xN2=N. The decomposition is highlighted in Figure 4, where the input samples are reshaped into N2xN1 matrix. Then a series of row-wise DFT’s of size N1 are performed . After, the first stage coefficients are multiplied by Twiddle factors that are defined as:

. rrm

T (m, n) = e ^{] p} N

Since the twiddle factor equals to one whenever m or n equals to 1 , there are (N1- 1 )^*(N2-1 ) = N-N1-N2+1 complex multiplications.

Then, the second stage row-wise DFT’s of size N2 are applied. The resulting coefficients are then reshaped into an array to extract the resulting coefficients.

Applying Cooley Tuckey algorithm for DCT-VI or DCT-VIII is straightforward. For DCT-VI of size N+1 , a 2N+1 DFT is used with the corresponding pre-processing and postprocessing (F(N) and R(N)).

The 2N+1 length of DFT consists of N+1 input samples followed by N zeros. When reshaping the samples to N2xN1 matrix, this results in many zeros for the first stage DFTs of size (N1 ). This illustrated in Figure 5 for DCT-VI of size 32, which requires the implementation of DFT of size 63 that can be decomposed in 9x7 DFT’s. As can be seen, the first (N2+1 )/2 have only the first (N1 +1 )/2 non-zeros, while the second (N2-1 )/2 have only the first (N1-1 )/2 non-zeros. For this reason, we distinguish two different implementations: DFT_H1 and DFT_H2.

Furthermore, only the output coefficients from 0 to N-1 are required. This will also lead to column wise DFT’s of size N2 whose inputs are either defined from 0 to (N1 +1 )/2 or from 0 to (N1-1 )/2. An example is provided in Figure 6 for the size of 32.

The structure of Cooley Tuckey algorithm for DCT-VI is shown in Figure 6. Since the input to the first stage is real data, a real input DFT is required for both H1 and H2 cases (DFT_RI_H1 and DFT_RI_H2). This is followed by twiddle factors multiplications. Then a second stage of DFT’s for real output for both H1 and H2 cases (DFT_RO_H1 and DFT_RO_H2). Furthermore, the first column input to the second stage has only real coefficients, the corresponding DFT is reduced to DFT_RI_RO_H1. The structure of Cooley Tuckey algorithm for DCT-VIII is very similar to the one of DCT-VI, but the output is required to be imaginary only. As depicted in Figure 8, DFT_RI_IO_H1 , DFT_IO_H1 and DFT_IO_H2 are used instead of DFT_RI_RO_H1 , DFT_RO_H1 and DFT_RO_H2.

At least some of the described embodiments can be implemented in modules are 125, 150 and 250 of Figures 9 and 10.

To describe an implementation of a DFT for real inputs, an N DFT matrix is defined as:

To compute the coefficients C(n), the matrix multiplication can is performed as:

For the first basis function (n=0), the cosine part equals one, and the imaginary part equals zero. Thus, the first basis function can be reduced to N-1 additions.

For the rest of basis functions (n > 0), the symmetric properties of the cosine and sine functions are utilized:

= _ _sjn ^2p ^(th+^^)ch^ Additionally, for m=0, the cosine part equals to

1 and the sine part equal to zeros. The equation then reduces to:

The DFT of real input of length N (N is odd) results in the coefficients where the last (N-1 )/2 coefficients are the complex conjugate of first (N-1 )/2 (neglecting the first DC coefficient). Thus, the above equation needs only to be applied for the coefficients from 1 to (N-1 )/2.

A sample MATLAB code is provided below: function Coef DFT RI ( R, N)

% Overall Multiplications

% (N-l) ^L2/2

% Overall Additions

% N-l + 2* (N-l ) /2 + 2* [ (N-l)/2*( (N-l ) /2-1) + (N-l) /2 ]

% 2* (N-l ) + (N-l) * (N-l) * ( (N-l) /2-1) + (N-l)

% 3* (N-l) + (N-l) * (N-3 ) /2

% (N-l) * (3 + (N-3) /2 )

% (N-l) * ( (N+5) /2)

Coef (1) = sum(R) ; % N-l additions

j = ( 1 : (N-l) 12 ;

i=j ¹ ; % transpose

CosPart = cos ( 2*pi*i*j /N ) ;

SinPart = sin ( 2*pi*i*j /N ) ; cl = R(2:(N+l)/2) + R (N: -1 : (N+l)/2+l) ; % (N-l)/2 additions

c2 = R(2:(N+l)/2) - R (N: -1 : (N+l)/2+l) ; % (N-l)/2 additions tl = R(l) + CosPart*cl;% (N-1)^L2/4 Multiplications and (N-l)/2*( (N-l)/2- l)+(N-l)/2 additions

t2 = SinPart*c2 ; % (N-1)^L2/4 Multiplications and (N—1 ) /2* ( (N-l)/2-l)

additions

Coef (2: (N+l) /2) = tl -lj* t2;

Coef(N:-l: (N+l)/2+l) = conj(Coef(2:(N+l)/2));

Further implication can be done in the case when half of the of the input is used. For both H1 and H2 cases, the symmetric properties are not required as the second half of the coefficients are zeros. The corresponding MATLAB code is provided below: function Coef = DFT_RI_H1 ( R, N)

% Overall Multiplications

% (N-l ) ^L2/2

% Overall Additions

% (N-l ) /2 + (N-l)/2*( (N-l) /2-1) + (N-l) /2 + (N-l)/2*( (N-l)/2-l)

% (N-l ) * (1/2 + 1/2* ( (N-l) /2-1) +1/2 + 1/2* ( (N-l)/2-l))

% (N-l) * (1 + ( (N-l) /2-1) )

% (N-l ) ^L2/2 Coef(l) = sum(R); % (N-l)/2 additions

j = ( 1 : (N-l) 12) ;

i=j ¹ ; % transpose

CosPart = cos ( 2*pi*i*j /N ) ;

SinPart = sin ( 2*pi*i*j /N ) ; cl = R ( 2 : (N+l ) /2) ;

c2 = R ( 2 : (N+l) /2) ; tl = R(l) + CosPart*cl ; % (N-1)^L2/4 Multiplications and (N—1 ) /2* ( (N-l)/2- l)+(N-l)/2 additions

t2 = SinPart*c2 ; % (N-1)^L2/4 Multiplications and (N—1 ) /2* ( (N-l)/2-l) additions

Coef (2: (N+l) /2) = tl -lj* t2;

Coef(N:-l: (N+l)/2+l) = conj(Coef(2:(N+l)/2)); function Coef = DFT_RI_H2 (R,N)

% Overall Multiplications

% ( (N-l) /2-1) * (N-l)

% ( (N-3) * (N-l) /2

% Overall Additions

% (N-l ) /2-1 + (N-l) /2* ( (N-l) /2-2) +(N-1) /2 + (N-l)/2*( (N-l)/2-2)

% (N-l ) * (1/2 + 1/2* ( (N-l) /2-2) + 1/2 + 1/2* ( (N-l)/2-2)) -1

% (N-l ) * ( 1 + ( (N-l ) /2-2) ) -1

% (N-l) * ( ( (N-l) /2-1) ) -1

% (N-l) * (N-3) /2-1

Coef(l) = sum(R); % (N-l)/2-l additions

j = ( 1 : (N-l) /2—1 ) ;

i= ( 1 : (N-l) /2) ¹ ; % transpose

CosPart = cos ( 2*pi*i*j /N ) ;

SinPart = sin ( 2*pi*i*j /N ) ; cl = R ( 2 : (N+l) /2-1) ;

c2 = R ( 2 : (N+l) /2-1) ; tl = R(l) + CosPart*cl;% ( (N-l ) /2-1 ) * (N-l ) /2 Multiplications and (N-1)/2*((N-

1 ) /2-2 ) + (N-l ) /2 additions

t2 = SinPart*c2;% ( (N-l ) /2-1 ) * (N-l ) /2 Multiplications and (N—1 ) /2 * ( (N-l)/2-

2) additions

Coef (2: (N+l) /2) = tl -lj* t2;

Coef(N:-l: (N+l)/2+l) = conj(Coef(2:(N+l)/2));

To describe an implementation of a DFT for real output coefficients, a length N DFT of an input / = R +jl is computed as: N— l

m X n

;sin(2Tr—— ) )

m= 0

Since the real output is only required, the above equation can be simplified to:

N-l

When n=0, it reduces to:

which requires N-1 additions.

= _ _sjn ^2p ^(m+^^xn^ Additionally, for m=0, the cosine part equals to

1 and the sine part equal to zeros. The equation then reduces to:

In addition, the other symmetric properties of the cosine and sine functions are utilized:

This results in N-1 +N-3+2=2N-2 additions and (N-1 ) multiplications per coefficient.

Thus, the two above equations can be computed simultaneously by storing two temporary values:

N—l

/ m X n\

% = N-l + (N-l) + (N-l) /2* (N-3) /2+ (N-l ) /2 + (N-l ) /2* (N-3 ) /2 + (N-l)-l % = (N-l ) * ( 1 + 1 + (N-3)/4+ 1/2 + (N-3)/4 + 1) -1

% = (N-l ) * (7/2 + (N-3)/2) -1

% = (N-l) * (N/2+2 ) -1

Coef (1) = sum(R) ; % N-l additions

j = ( 1 : (N-l) 12) ;

i=j ¹ ; % transpose

CosPart = cos ( 2*pi*i*j /N ) ;

SinPart = sin ( 2*pi*i*j /N ) ; cl = R(2:(N+l)/2) % (N-l)/2 additions

c2 = 1(2: (N+l ) /2 )

% (N-l)/2 additions tl = R(l) + CosPart*cl; % (N-1)^L2/4 Multiplications and (N—l ) /2* ( (N-l)/2- l)+(N-l)/2 additions

t2 = SinPart*c2; % (N-1)^L2/4 Multiplications and (N—l ) /2 * ( (N-l)/2-l) additions

Coef(2:(N+l)/2) = tl + t2 ; % (N-l)/2 additions

Coef (N:-l: (N+l) /2+1) = tl - t2 ; % (N-l)/2-l additions When half of the output coefficients are only needed, the MATLAB code can be simplified for H1 and H2 cases as below: function Coef = DFT_R0_H1 ( R, I , N )

% Overall Multiplications

% (N-l ) ^L2/2

% Overall Additions

% N-l + 2* (N-l ) /2 + (N-l)/2*( (N-l) /2-1 ) + (N-l ) /2 + (N-l)/2*( (N-l)/2-l) +

% (N-l ) /2

% = N-l + (N-l) + (N-l) /2* (N-3) /2+ (N-l ) /2 + (N-l ) /2* (N-3 ) /2 + (N-l)/2 % = (N-l ) * ( 1 + 1 + (N-3)/4+ 1/2 + (N-3)/4 + 1/2)

% = (N-l) * (N+3 ) /2

Coef (1) = sum(R) ; % N-l additions

j = ( 1 : (N-l) 12) ;

i=j ¹ ; % transpose

CosPart = cos ( 2*pi*i*j /N ) ;

SinPart = sin ( 2*pi*i*j /N ) ; % (N-l)/2 additions

% (N-l)/2 additions tl = R(l) + CosPart*cl; % (N-1)^L2/4 Multiplications and (N-l)/2*( (N-l)/2- l)+(N-l)/2 additions

t2 = SinPart*c2; % (N-1)^L2/4 Multiplications and (N—1 ) /2 * ( (N-l)/2-l) additions

Coef(2:(N+l)/2) = tl + t2 ; % (N-l)/2 additions function Coef = DFT_RO_H2 ( R, I , N )

% Overall Multiplications

% (N-l) * ( (N-l) /2-1)

% (N-l) * ( (N-3) /2

% Overall Additions

% N-l + 2* (N-l ) /2 + ( (N-l) /2-1) * ( (N-l) /2-1) +(N-1) /2-1 +

% ( (N-l) /2-1) * ( (N-l) /2-1) + (N-l ) /2-1

% = (N-l ) * ( 1 + 1 + 1/2 + 1/2) + 2* ( (N-l) /2-1) ^L2 -1 - 1

% = 3* (N-l) + ( (N-3 ) ) ^L2/2 - 2

Coef (1) = sum(R) ; % N-l additions

j = ( 1 : (N-l) 12) ;

i= ( 1 : (N-l) /2-1) ¹ ; % transpose

CosPart = cos ( 2*pi*i*j /N ) ;

SinPart = sin ( 2*pi*i*j /N ) ; cl = R(2:(N+l)/2) % (N-l)/2 additions

c2 = 1(2: (N+l ) /2 )

% (N-l)/2 additions tl = R(l) + CosPart*cl; % (N-l ) /2* ( (N-l ) /2-1 ) Multiplications and ( (N—1 ) /2— 1) * ( (N-l) /2-1) + (N-l ) /2-1 additions

t2 = SinPart*c2; % (N-l ) /2* ( (N-l ) /2-1 ) Multiplications and ( (N—l) /2—1) * ( (N— l)/2-l) additions

Coef (2 : (N+l) /2 ) = tl + t2;% (N-l)/2-l additions

To describe an implementation of a DFT for imaginary output coefficients, a length N DFT of an input / = R +jl is computed as:

Since the imaginary output is only required, the above equation can be simplified to:

When n=0, it reduces to:

N—l

C(0) = /

m=0 which requires N-1 additions.

For the rest of basis functions (n > 0), the symmetric properties of the cosine and sine functions are utilized: _anq

= - _sin ₍ 2p ^m+^^xn^ Additionally, for m=0, the cosine part equals to

1 and the sine part equal to zeros. The equation then reduces to:

The MATLAB code is provided below: function Coef = DFT_IO (R, I , N)

% Overall Multiplications

% (N-l ) ^L2/2

% Overall Additions

% (N-l ) /2 + (N-l ) /2-1

% = (N-l ) * ( 1 + 1 + 1/2* ( (N-l) /2-1) +1/2 + 1/2* ( (N-l)/2-l) + 1/2 + l/2)-l

% = (N-l ) * ( 7/2 + ( (N-l) /2-1) ) -1

% = (N-l ) * ( 7/2 + (N-3)/2)-l

% = (N-l) * (N/2+2) -1

Coef (1) = sum(I) ; % N-l additions

j = ( 1 : (N-l) 12 ;

i=j ¹ ; % transpose

CosPart = cos ( 2*pi*i*j /N ) ;

SinPart = sin ( 2*pi*i*j /N ) ; cl = 1(2: (N+l ) /2 ) % (N-l)/2 additions

c2 = R ( 2 : (N+l ) /2 )

% (N-l)/2 additions tl = 1(1) + CosPart*cl ; % (N-1)^L2/4 Multiplications and (N—1 ) /2* ( (N-l)/2- l)+(N-l)/2 additions

t2 = SinPart*c2;% (N-1)^L2/4 Multiplications and (N—1 ) /2* ( (N-l)/2-l) additions

Coef(2:(N+l)/2) = tl - t2;% (N-l)/2 additions

Coef(N:-l: (N+l)/2+l) = tl + t2 ; % (N-l)/2-l additions

In the case of H1 or H2, the MATLAB code is simplified as below: function Coef = DFT_IO_Hl ( R, N)

% Overall Multiplications

% (N-l ) ^L2/2

% Overall Additions

% N-l + (N-l)/2*( (N-l ) /2 -1 ) + (N-l)/2 + (N-l)/2*( (N-l)/2-l) + (N-l)/2 % (N-l ) * ( 1 + 1/2* ( (N-l ) /2 -1 ) + 1/2 + 1/2* ( (N-l)/2-l) + 1/2)

% (N-l) * ( 2 + ( (N-l 2 -1 ) )

% (N-l) * (N+l) /2

% (N^L2-1)/2

Coef (1) = sum(I) ; % N-l additions

j = ( 1 : (N-l) 12 ; i= ( 1 : (N-l) /2) ' ; % transpose

CosPart = cos ( 2*pi*i*j /N ) ;

SinPart = sin ( 2*pi*i*j /N ) ; cl = 1(2: (N+l ) /2 ) % (N-l)/2 additions

c2 = R ( 2 : (N+l ) /2 )

% (N-l)/2 additions tl = 1(1) + CosPart*cl;% (N-1)^L2/4 Multiplications and (N-l)/2*( (N-l)/2- l)+(N-l)/2 additions

Coef(2:(N+l)/2) = tl - t2 ; % (N-l)/2 additions function Coef = DFT_IO_H2 ( R, N)

% Overall Multiplications

% (N-3 ) * (N-l ) /2

% Overall Additions

% N-l + 2* (N-l ) /2 + ( (N-l) /2-1) * ( (N-l) /2-1 ) + (N-l ) /2-1 + ( (N-l) /2-1) * ( (N-

1) /2-1)

% = (N-l ) * ( 1 + 1 + 1/2) + 2* ( (N-l) /2-1) ^L2 - 1

% = (N-l ) *5/2 + ( (N-3 ) ) ^L2/2 - 1

Coef (1) = sum(I) ; % N-l additions

j = ( 1 : (N-l) 12) ;

i= ( 1 : (N-l) /2-1) ¹ ; % transpose

CosPart = cos ( 2*pi*i*j /N ) ;

SinPart = sin ( 2*pi*i*j /N ) ; cl = 1(2: (N+l ) /2 ) % (N-l)/2 additions

c2 = R(2:(N+l)/2)

% (N-l)/2 additions tl = 1(1) + CosPart*cl;% ( (N-l ) /2-1 ) * (N-l ) /2 Multiplications and ( (N—1 ) /2— 1)*( (N-l) /2-1) + (N-l) /2-1 additions

t2 = SinPart*c2 ; % ( (N-l) /2-1 ) * (N-l) /2 Multiplications and ( (N-l ) /2-1 ) * ( (N- l)/2-l) additions

Coef (2 : (N-l) /2 ) = tl - t2 ; % (N-l)/2-l additions

To describe an implementation of a DFT for real inputs, a length N DFT of an input I = R is computed as:

N

å-l

( m X n\ m X n

R X (cos \ 2p——— J +y^'sin(27r———))

m=0

When n=0, it reduces to:

which requires N-1 additions.

For the rest of basis functions (n > 0), the symmetric properties of the cosine function are utilized: Additionally, for m=0, the cosine part

equals to 1 and the sine part equal to zeros. The equation then reduces to:

This results in N-2+1 =N-1 additions and (N-1 )/2 multiplications per coefficient.

The MATLAB code is below: function Coef = DFT_RI_RO ( R, N)

% Overall Multiplications

% (N-1 ) ^L2/ 4

% Overall Additions

% N-1 + (N-1 ) /2 + (N-l)/2*( (N-1) /2-1) + (N-1) /2

% (N-1 ) *2 + (N-1) /2* (N-3) /2

% (N-1) * (5+N) /4

Coef (1) = sum(R) ; % N-1 additions

j = ( 1 : (N-1) /2 ) ;

i=j ' ; % transpose CosPart = cos ( 2*pi*i*j /N ) ; cl = R(2:(N+l)/2) + R (N: -1 : (N+l ) /2+1 ) ; % (N-l)/2 additions

Coef (2 : (N+l) /2 ) = R(l) + CosPart*cl; % (N-1)^L2/4 Multiplications and (N- l)/2*( (N-l )/2-l)+(N-l)/2 additions

%C ( 2 : (N+l) /2 ) = tl;

Coef (N:-l: (N+l) /2+1) = Coef (2 : (N+l) /2) ;

In the case of H1 , the MATLAB code is simplified to: function Coef = DFT_RI_R0_H1 (R,N)

% Overall Multiplications

% (N-l ) ^L2/ 4

% Overall Additions

% N-l + (N-l ) /2 + (N-l)/2*( (N-l) /2-1) + (N-l) /2

% (N-l ) * ( 1 + 1/2 + 1/2* ( (N-l) /2-1) +1/2)

% (N-l) * (2 + 1/4* (N-3 ) )

% (N-l) * (N+5) /4

Coef (1) = sum(R) ; % N-l additions

j = ( 1 : (N-l) 12) ;

i=j ¹ ; % transpose

CosPart = cos ( 2*pi*i*j /N ) ; cl = R ( 2 : (N+l ) /2 ) + R (N : -1 : (N+l ) /2+1 ) ; % (N-l)/2 additions

Coef (2 : (N+l) /2 ) = R(l) + CosPart*cl; % (N-1)^L2/4 Multiplications and (N-

1 ) /2* ( (N-l) /2-1) + (N-l) /2 additions

To describe an implementation of a DFT for real inputs, a length N DFT of an input / = R +jl is computed as:

Nå-l

C(n) = R X (cos

m=0

When n=0, it reduces to:

C(0) = 0

For the rest of basis functions (n > 0), the symmetric properties of the sine function are utilized: sin (in ^{(N 1} _jV ^7n)xn) = - sin ( n ^(Tn+^^xn^ The equation then reduces to:

This results in N-2 additions and (N-1 )/2 multiplications per coefficient.

The corresponding MATLAB code is below: function Coef = DFT_RI_IO ( R, N)

% Overall Multiplications

% (N-1)^L2/4

% Overall Additions

% (N-l ) / 2 + (N-l)/2*( (N-l ) /2-1 )

% = (N-l) /2* (1 + (N-3 ) /2 )

% = (N-l) /2* (N-l) /2

% = (N-l) ^L2/4

Coef ( 1 ) = 0 ;

j = ( 1 : (N-l) 12 ) ;

i=j ¹ ; % transpose

SinPart = sin ( 2*pi*i*j /N ) ;

c2 = R(2:(N+l)/2) - R (N: -1 : (N+l)/2+l) ; % (N-l)/2 additions

Coef (2 : (N+l) /2 ) = -SinPart*c2 ; % (N-1)^L2/4 Multiplications and (N—1 ) /2* ( (N- l)/2-l) additions

Coef (N:-l: (N+l) /2+1) = -Coef (2 : (N+l ) /2 ) ;

In the case of H1 , the code is: function Coef = DFT_RI_IO_Hl (R, N)

% Overall Multiplications

% (N-1)^L2/4

% Overall Additions

% (N-l)/2 + (N-l)/2*( (N-l ) /2-1 )

% (N-l ) * (1/2 + 1/2* ( (N-l ) /2-1 ) )

% (N-l) * (1/2 + 1/4* (N-3 ) )

% (N-l) * (N-l) /4

% (N-l ) ^L2/ 4

Coef ( 1 ) = 0 ;

j = ( 1 : (N-l) 12 ;

i=j ¹ ; % transpose

SinPart = sin ( 2*pi*i*j /N ) ;

c2 = R(2:(N+l)/2) - R (N: -1 : (N+l)/2+l) ; % (N-l)/2 additions

When N1 equals to 3, the DFT_RI_H2 requires 0 multiplications and 0 additions, as described in the MATLAB code below: function Coef = DFT_RI_H2_N3 (R)

% Overall Multiplications

% 0

% Overall Additions

% 0

Coef (1:N) = R(l) ;

In addition, its coefficients are real data. This is interesting in the case of Cooley Tuckey algorithm since it can reduce the number of operations for the Twiddle Factor multiplication. Specifically, the H2 first stage coefficients, which are the coefficients from (N2+1 )/2 to N2-1 , are real values multiplied by complex Twiddle factors. This requires 2 multiplications and one addition, which are half the number of operations for complex multiplications (4 multiplications and 2 additions). function Coef = DFT_RO_H2_3 ( R, I )

% 0

% Overall Additions

% 2

Coef (1) = sum(R) ; % 2 additions function Coef = DFT_IO_H2 ( R, I )

% Overall Multiplications

% 0

% Overall Additions

% 2

Coef (1) = sum(I) ; % N-l additions

The summary of the number of multiplications and additions for each process is given in Table 3: Overall number of operations for each DFT type.

Table 3: Overall number of operations for each DFT type

Once DCT-VI or DCT-VIII is decomposable into N1xN2 sub-DFT’s, the total number of operations can be counted. As illustrated in Figure 2 for the Prime Factor Algorithm, implementing DCT-VI requires:

Table 4: Number of operations required to compute DCT-VI

Whereas DCT-VIII would require the following number of operations:

Table 5: Number of operations required to compute DCT-VIII

For example, when N=32, DCT-VIII is computed from 65 FFT that can be decomposed into 5x13 DFT using prime factor algorithm. The total number of operations is equal to 156 multiplications and 421 additions. This is substantially lower than the total number of operations when direct matrix multiplication is employed in which 1024 multiplications and 992 are additions required.

On the other hand, the Cooley-Tuckey algorithm requires the following operations for DCT-VI:

Table 6: Number of operations required to compute DCT-VI (Cooley Tuckey Algorithm). Neither N1 nor

N2 equals to 3. For DCT-VIII:

Table 7: Number of operations required to compute DCT-VIII (Cooley Tuckey Algorithm). Neither N1 nor N2 equals to 3.

In JEM software, the following transforms are used in the EMT set: DST-I, DST- VII, DCT-V and DCT-VIII for the sizes of 4x4, 8x8, 16x16, 32x32 and 64x64. The general aspects herein apply for DST-VII, DCT-V and DCT-VII. In fact, DST-VII uses the same architecture as DCT-VIII since they can be derived from each other by simple reversing and sign changing operations of Table 2. Similarity, DCT-V is obtained from DCT-VI Table 2. Using the prime factor algorithm gives the total number of operations as detailed in the table below:

Table 8: Number of operations required to implement the transform design in JEM software, using prime factor algorithm.

The table below shows an example of memory requirements:

Table 9: Number of coefficients needed to be stored to implement the transform design.

The current design implements the transform by matrix multiplications. This requires storing the transform matrix for each transform size. As can be seen in the table below, 1 1840 coefficients are required. Thus, 1 -1064/1 1840=91 % of the original memory can be saved.

Table 10: Number of coefficients needed to be stored to implement the original transform design.

An alternative design could be used when the Cooley-Tuckey algorithm is used. The total number of operations are described below:

Table 11: Number of operations required to implement the transform design in JEM software, using

Cooley-Tuckey Algorithm.

The Cooley-Tuckey algorithm requires larger number of operations in comparison with the prime factor algorithm. This is because of the multiplication by complex twiddle factors. However, Cooley-Tuckey algorithm has simpler memory access. This is because it performs input sample/output coefficients reshaping rather than permutation. This is generally preferred in software design as it reduces the overall latency. In terms of memory requirements, further coefficients that correspond to twiddle factors are needed to be stored, as described in Table 12:

Table 12: Additional number of coefficients needed to be stored for the twiddle factors.

It should be noted that other sizes of transforms are not considered here. This is because some requires prime length of DFT, which cannot be factorized in terms of prime factor algorithm or Cooley Tuckey algorithm.

NextSoftware is the proposed video compression technology by the Fraunhofer Institute. It is very complex in terms of transform design as it implements the following transform sizes:

TrSizes = [4 6 8 10 12 16 20 24 32 40 48 64 80 96 128];

The current aspects also apply to some of the transform sizes as described in the table below:

Table 13: Number of operations required to implement the transform design in JEM software using prime factor algorithm and Cooley-Tuckey algorithm (in italic).

The required number of coefficients is 2002 (Table 14), which is about 5% the original number 42840 (Table 15).

Table 14: Additional number of coefficients needed to be stored to implement the transform design in

NextSoftware.

Table 15: Additional number of coefficients needed to be stored to implement the original transform design in NextSoftware.

Commonly, the transform matrices are required to be represented with integer values. To achieve this, both the first stage and last stage DFT matrices need to be upscaled by a proper value, then downscaled respectively. However, since the transform matrices scale is fixed, the second stage matrices need not be downscaled, but rather properly upscaled at first. For example, both NextSoftware and MTT upscales the transform matrices by a scaling factor proportional to the input vector size. This factor must be used for upscaling the second stage matrices, while the first stage could simply be scaled by a binary value so that no multiplications are required.

One embodiment of a method 1200 under the general aspects described here is shown in Figure 12. The method commences at start block 1201 and control proceeds to block 1210 for performing at least a portion of a Discrete Trigonometric Transform on a subset of samples comprising a block. Control proceeds from block 1210 to block 1220 for determining transform coefficients for the block using the transformed subset of samples. Control proceeds from block 1220 to block 1230 for encoding the block.

One embodiment of a method 1300 under the general aspects described here is shown in Figure 13. The method commences at start block 1301 and control proceeds to block 1310 for performing at least a portion of an inverse Discrete Trigonometric Transform on a subset of coefficients comprising a block. Control proceeds from block 1310 to block 1320 for determining samples for the block using the inverse transformed subset of coefficients. Control proceeds from block 1320 to block 1330 for decoding the block.

Figure 14 shows one embodiment of an apparatus 1400 for compressing, encoding or decoding video using improved virtual temporal affine candidates. The apparatus comprises Processor 1410 and can be interconnected to a memory 1420 through at least one port. Both Processor 1410 and memory 1420 can also have one or more additional interconnections to external connections.

Processor 1410 is also configured to either insert or receive information in a bitstream and, either compressing, encoding or decoding using fast implementation of odd one-dimensional transforms. This document describes a variety of aspects, including tools, features, embodiments, models, approaches, etc. Many of these aspects are described with specificity and, at least to show the individual characteristics, are often described in a manner that can sound limiting. However, this is for purposes of clarity in description, and does not limit the application or scope of those aspects. Indeed, all the different aspects can be combined and interchanged to provide further aspects. Moreover, the aspects can be combined and interchanged with aspects described in earlier filings as well.

The aspects described and contemplated in this document can be implemented in many different forms. FIGs. 9, 10 and 1 1 below provide some embodiments, but other embodiments are contemplated and the discussion of FIGs. 9, 10 and 1 1 does not limit the breadth of the implementations. At least one of the aspects generally relates to video encoding and decoding, and at least one other aspect generally relates to transmitting a bitstream generated or encoded. These and other aspects can be implemented as a method, an apparatus, a computer readable storage medium having stored thereon instructions for encoding or decoding video data according to any of the methods described, and/or a computer readable storage medium having stored thereon a bitstream generated according to any of the methods described.

In the present application, the terms“reconstructed” and“decoded” may be used interchangeably, the terms“pixel” and“sample” may be used interchangeably, the terms “image,”“picture” and“frame” may be used interchangeably. Usually, but not necessarily, the term“reconstructed” is used at the encoder side while“decoded” is used at the decoder side.

Various methods are described herein, and each of the methods comprises one or more steps or actions for achieving the described method. Unless a specific order of steps or actions is required for proper operation of the method, the order and/or use of specific steps and/or actions may be modified or combined.

Various methods and other aspects described in this document can be used to modify modules, for example, the intra prediction, entropy coding, and/or decoding modules (160, 360, 145, 330), of a video encoder 100 and decoder 200 as shown in FIG. 9 and FIG. 10. Moreover, the present aspects are not limited to WC or HEVC, and can be applied, for example, to other standards and recommendations, whether pre-existing or future-developed, and extensions of any such standards and recommendations (including VVC and HEVC). Unless indicated otherwise, or technically precluded, the aspects described in this document can be used individually or in combination.

Various numeric values are used in the present document, for example, {{1 ,0}, {3, 1 }, {1 , 1 }}. The specific values are for example purposes and the aspects described are not limited to these specific values.

FIG. 9 illustrates an encoder 100. Variations of this encoder 100 are contemplated, but the encoder 100 is described below for purposes of clarity without describing all expected variations.

Before being encoded, the video sequence may go through pre-encoding processing (101 ), for example, applying a color transform to the input color picture (e.g., conversion from RGB 4:4:4 to YCbCr 4:2:0), or performing a remapping of the input picture components in order to get a signal distribution more resilient to compression (for instance using a histogram equalization of one of the color components). Metadata can be associated with the pre-processing and attached to the bitstream.

In the encoder 100, a picture is encoded by the encoder elements as described below. The picture to be encoded is partitioned (102) and processed in units of, for example, CUs. Each unit is encoded using, for example, either an intra or inter mode. When a unit is encoded in an intra mode, it performs intra prediction (160). In an inter mode, motion estimation (175) and compensation (170) are performed. The encoder decides (105) which one of the intra mode or inter mode to use for encoding the unit, and indicates the intra/inter decision by, for example, a prediction mode flag. Prediction residuals are calculated, for example, by subtracting (1 10) the predicted block from the original image block.

The prediction residuals are then transformed (125) and quantized (130). The quantized transform coefficients, as well as motion vectors and other syntax elements, are entropy coded (145) to output a bitstream. The encoder can skip the transform and apply quantization directly to the non-transformed residual signal. The encoder can bypass both transform and quantization, i.e. , the residual is coded directly without the application of the transform or quantization processes.

The encoder decodes an encoded block to provide a reference for further predictions. The quantized transform coefficients are de-quantized (140) and inverse transformed (150) to decode prediction residuals. Combining (155) the decoded prediction residuals and the predicted block, an image block is reconstructed. In-loop filters (165) are applied to the reconstructed picture to perform, for example, deblocking/SAO (Sample Adaptive Offset) filtering to reduce encoding artifacts. The filtered image is stored at a reference picture buffer (180).

FIG. 10 illustrates a block diagram of a video decoder 200. In the decoder 200, a bitstream is decoded by the decoder elements as described below. Video decoder 200 generally performs a decoding pass reciprocal to the encoding pass as described in FIG. 9. The encoder 100 also generally performs video decoding as part of encoding video data.

The input of the decoder includes a video bitstream, which can be generated by video encoder 100. The bitstream is first entropy decoded (230) to obtain transform coefficients, motion vectors, and other coded information. The picture partition information indicates how the picture is partitioned. The decoder may therefore divide (235) the picture according to the decoded picture partitioning information. The transform coefficients are de-quantized (240) and inverse transformed (250) to decode the prediction residuals. Combining (255) the decoded prediction residuals and the predicted block, an image block is reconstructed. The predicted block can be obtained (270) from intra prediction (260) or motion-compensated prediction (i.e. , inter prediction) (275). In- loop filters (265) are applied to the reconstructed image. The filtered image is stored at a reference picture buffer (280).

The decoded picture can further go through post-decoding processing (285), for example, an inverse color transform (e.g. conversion from YCbCr 4:2:0 to RGB 4:4:4) or an inverse remapping performing the inverse of the remapping process performed in the pre-encoding processing (101 ). The post-decoding processing can use metadata derived in the pre-encoding processing and signaled in the bitstream.

FIG. 1 1 illustrates a block diagram of an example of a system in which various aspects and embodiments are implemented. System 1000 can be embodied as a device including the various components described below and is configured to perform one or more of the aspects described in this document. Examples of such devices include, but are not limited to, various electronic devices such as personal computers, laptop computers, smartphones, tablet computers, digital multimedia set top boxes, digital television receivers, personal video recording systems, connected home appliances, and servers. Elements of system 1000, singly or in combination, can be embodied in a single integrated circuit, multiple ICs, and/or discrete components. For example, in at least one embodiment, the processing and encoder/decoder elements of system 1000 are distributed across multiple ICs and/or discrete components. In various embodiments, the system 1000 is communicatively coupled to other similar systems, or to other electronic devices, via, for example, a communications bus or through dedicated input and/or output ports. In various embodiments, the system 1000 is configured to implement one or more of the aspects described in this document.

The system 1000 includes at least one processor 1010 configured to execute instructions loaded therein for implementing, for example, the various aspects described in this document. Processor 1010 can include embedded memory, input output interface, and various other circuitries as known in the art. The system 1000 includes at least one memory 1020 (e.g., a volatile memory device, and/or a non-volatile memory device). System 1000 includes a storage device 1040, which can include non-volatile memory and/or volatile memory, including, but not limited to, EEPROM, ROM, PROM, RAM, DRAM, SRAM, flash, magnetic disk drive, and/or optical disk drive. The storage device 1040 can include an internal storage device, an attached storage device, and/ora network accessible storage device, as non-limiting examples.

System 1000 includes an encoder/decoder module 1030 configured, for example, to process data to provide an encoded video or decoded video, and the encoder/decoder module 1030 can include its own processor and memory. The encoder/decoder module 1030 represents module(s) that can be included in a device to perform the encoding and/or decoding functions. As is known, a device can include one or both encoding and decoding modules. Additionally, encoder/decoder module 1030 can be implemented as a separate element of system 1000 or can be incorporated within processor 1010 as a combination of hardware and software as known to those skilled in the art.

Program code to be loaded onto processor 1010 or encoder/decoder 1030 to perform the various aspects described in this document can be stored in storage device 1040 and subsequently loaded onto memory 1020 for execution by processor 1010. In accordance with various embodiments, one or more of processor 1010, memory 1020, storage device 1040, and encoder/decoder module 1030 can store one or more of various items during the performance of the processes described in this document. Such stored items can include, but are not limited to, the input video, the decoded video or portions of the decoded video, the bitstream, matrices, variables, and intermediate or final results from the processing of equations, formulas, operations, and operational logic.

In several embodiments, memory inside of the processor 1010 and/or the encoder/decoder module 1030 is used to store instructions and to provide working memory for processing that is needed during encoding or decoding. In other embodiments, however, a memory external to the processing device (for example, the processing device can be either the processor 1010 or the encoder/decoder module 1030) is used for one or more of these functions. The external memory can be the memory 1020 and/or the storage device 1040, for example, a dynamic volatile memory and/or a non-volatile flash memory. In several embodiments, an external non-volatile flash memory is used to store the operating system of a television. In at least one embodiment, a fast, external dynamic volatile memory such as a RAM is used as working memory for video coding and decoding operations, such as for MPEG-2, HEVC, or VVC (Versatile Video Coding).

The input to the elements of system 1000 can be provided through various input devices as indicated in block 1 130. Such input devices include, but are not limited to, (i) an RF portion that receives an RF signal transmitted, for example, over the air by a broadcaster, (ii) a Composite input terminal, (iii) a USB input terminal, and/or (iv) an HDMI input terminal.

In various embodiments, the input devices of block 1 130 have associated respective input processing elements as known in the art. For example, the RF portion can be associated with elements necessary for (i) selecting a desired frequency (also referred to as selecting a signal, or band-limiting a signal to a band of frequencies), (ii) downconverting the selected signal, (iii) band-limiting again to a narrower band of frequencies to select (for example) a signal frequency band which can be referred to as a channel in certain embodiments, (iv) demodulating the downconverted and band-limited signal, (v) performing error correction, and (vi) demultiplexing to select the desired stream of data packets. The RF portion of various embodiments includes one or more elements to perform these functions, for example, frequency selectors, signal selectors, band- limiters, channel selectors, filters, downconverters, demodulators, error correctors, and demultiplexers. The RF portion can include a tuner that performs various of these functions, including, for example, downconverting the received signal to a lower frequency (for example, an intermediate frequency or a near-baseband frequency) or to baseband. In one set-top box embodiment, the RF portion and its associated input processing element receives an RF signal transmitted over a wired (for example, cable) medium, and performs frequency selection by filtering, downconverting, and filtering again to a desired frequency band. Various embodiments rearrange the order of the above-described (and other) elements, remove some of these elements, and/or add other elements performing similar or different functions. Adding elements can include inserting elements in between existing elements, for example, inserting amplifiers and an analog-to-digital converter. In various embodiments, the RF portion includes an antenna.

Additionally, the USB and/or HDMI terminals can include respective interface processors for connecting system 1000 to other electronic devices across USB and/or HDMI connections. It is to be understood that various aspects of input processing, for example, Reed-Solomon error correction, can be implemented, for example, within a separate input processing IC or within processor 1010 as necessary. Similarly, aspects of USB or HDMI interface processing can be implemented within separate interface ICs or within processor 1010 as necessary. The demodulated, error corrected, and demultiplexed stream is provided to various processing elements, including, for example, processor 1010, and encoder/decoder 1030 operating in combination with the memory and storage elements to process the datastream as necessary for presentation on an output device.

Various elements of system 1000 can be provided within an integrated housing, Within the integrated housing, the various elements can be interconnected and transmit data therebetween using suitable connection arrangement 1 140, for example, an internal bus as known in the art, including the I2C bus, wiring, and printed circuit boards.

The system 1000 includes communication interface 1050 that enables communication with other devices via communication channel 1060. The communication interface 1050 can include, but is not limited to, a transceiver configured to transmit and to receive data over communication channel 1060. The communication interface 1050 can include, but is not limited to, a modem or network card and the communication channel 1060 can be implemented, for example, within a wired and/or a wireless medium.

Data is streamed to the system 1000, in various embodiments, using a wireless network, such as IEEE 802.1 1 . The wireless signal of these embodiments is received over the communications channel 1060 and the communications interface 1050 which are adapted for Wi-Fi communications, for example. The communications channel 1060 of these embodiments is typically connected to an access point or router that provides access to outside networks including the Internet for allowing streaming applications and other over-the-top communications. Other embodiments provide streamed data to the system 1000 using a set-top box that delivers the data over the HDMI connection of the input block 1 130. Still other embodiments provide streamed data to the system 1000 using the RF connection of the input block 1 130. The system 1000 can provide an output signal to various output devices, including a display 1 100, speakers 1 1 10, and other peripheral devices 1 120. The other peripheral devices 1 120 include, in various examples of embodiments, one or more of a stand-alone DVR, a disk player, a stereo system, a lighting system, and other devices that provide a function based on the output of the system 1000. In various embodiments, control signals are communicated between the system 1000 and the display 1 100, speakers 1 1 10, or other peripheral devices 1 120 using signaling such as AV.Link, CEC, or other communications protocols that enable device-to-device control with or without user intervention. The output devices can be communicatively coupled to system 1000 via dedicated connections through respective interfaces 1070, 1080, and 1090. Alternatively, the output devices can be connected to system 1000 using the communications channel 1060 via the communications interface 1050. The display 1 100 and speakers 1 1 10 can be integrated in a single unit with the other components of system 1000 in an electronic device, for example, a television. In various embodiments, the display interface 1070 includes a display driver, for example, a timing controller (T Con) chip.

The display 1 100 and speaker 1 1 10 can alternatively be separate from one or more of the other components, for example, if the RF portion of input 1 130 is part of a separate set-top box. In various embodiments in which the display 1 100 and speakers 11 10 are external components, the output signal can be provided via dedicated output connections, including, for example, HDMI ports, USB ports, or COMP outputs.

The embodiments can be carried out by computer software implemented by the processor 1010 or by hardware, or by a combination of hardware and software. As a non-limiting example, the embodiments can be implemented by one or more integrated circuits. The memory 1020 can be of any type appropriate to the technical environment and can be implemented using any appropriate data storage technology, such as optical memory devices, magnetic memory devices, semiconductor-based memory devices, fixed memory, and removable memory, as non-limiting examples. The processor 1010 can be of any type appropriate to the technical environment, and can encompass one or more of microprocessors, general purpose computers, special purpose computers, and processors based on a multi-core architecture, as non-limiting examples.

Various implementations involve decoding.“Decoding”, as used in this application, can encompass all or part of the processes performed, for example, on a received encoded sequence to produce a final output suitable for display. In various embodiments, such processes include one or more of the processes typically performed by a decoder, for example, entropy decoding, inverse quantization, inverse transformation, and differential decoding. In various embodiments, such processes also, or alternatively, include processes performed by a decoder of various implementations described in this application, for example, extracting an index of weights to be used for the various intra prediction reference arrays.

As further examples, in one embodiment “decoding” refers only to entropy decoding, in another embodiment“decoding” refers only to differential decoding, and in another embodiment “decoding” refers to a combination of entropy decoding and differential decoding. Whether the phrase “decoding process” is intended to refer specifically to a subset of operations or generally to the broader decoding process will be clear based on the context of the specific descriptions and is believed to be well understood by those skilled in the art.

Various implementations involve encoding. In an analogous way to the above discussion about“decoding”,“encoding” as used in this application can encompass all or part of the processes performed, for example, on an input video sequence to produce an encoded bitstream. In various embodiments, such processes include one or more of the processes typically performed by an encoder, for example, partitioning, differential encoding, transformation, quantization, and entropy encoding. In various embodiments, such processes also, or alternatively, include processes performed by an encoder of various implementations described in this application, for example, weighting of intra prediction reference arrays.

As further examples, in one embodiment “encoding” refers only to entropy encoding, in another embodiment“encoding” refers only to differential encoding, and in another embodiment“encoding” refers to a combination of differential encoding and entropy encoding. Whether the phrase“encoding process” is intended to refer specifically to a subset of operations or generally to the broader encoding process will be clear based on the context of the specific descriptions and is believed to be well understood by those skilled in the art.

Note that the syntax elements as used herein are descriptive terms. As such, they do not preclude the use of other syntax element names.

When a figure is presented as a flow diagram, it should be understood that it also provides a block diagram of a corresponding apparatus. Similarly, when a figure is presented as a block diagram, it should be understood that it also provides a flow diagram of a corresponding method/process. Various embodiments refer to rate distortion calculation or rate distortion optimization. During the encoding process, the balance or trade-off between the rate and distortion is usually considered, often given the constraints of computational complexity. The rate distortion optimization is usually formulated as minimizing a rate distortion function, which is a weighted sum of the rate and of the distortion. There are different approaches to solve the rate distortion optimization problem. For example, the approaches may be based on an extensive testing of all encoding options, including all considered modes or coding parameters values, with a complete evaluation of their coding cost and related distortion of the reconstructed signal after coding and decoding. Faster approaches may also be used, to save encoding complexity, in particular with computation of an approximated distortion based on the prediction or the prediction residual signal, not the reconstructed one. Mix of these two approaches can also be used, such as by using an approximated distortion for only some of the possible encoding options, and a complete distortion for other encoding options. Other approaches only evaluate a subset of the possible encoding options. More generally, many approaches employ any of a variety of techniques to perform the optimization, but the optimization is not necessarily a complete evaluation of both the coding cost and related distortion.

The implementations and aspects described herein can be implemented in, for example, a method or a process, an apparatus, a software program, a data stream, or a signal. Even if only discussed in the context of a single form of implementation (for example, discussed only as a method), the implementation of features discussed can also be implemented in other forms (for example, an apparatus or program). An apparatus can be implemented in, for example, appropriate hardware, software, and firmware. The methods can be implemented, for example, in a processor, which refers to processing devices in general, including, for example, a computer, a microprocessor, an integrated circuit, or a programmable logic device. Processors also include communication devices, such as, for example, computers, cell phones, portable/personal digital assistants ("PDAs"), and other devices that facilitate communication of information between end- users.

Reference to“one embodiment” or“an embodiment” or“one implementation” or “an implementation”, as well as other variations thereof, means that a particular feature, structure, characteristic, and so forth described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase“in one embodiment” or“in an embodiment” or“in one implementation” or“in an implementation”, as well any other variations, appearing in various places throughout this document are not necessarily all referring to the same embodiment.

Additionally, this document may refer to “determining” various pieces of information. Determining the information can include one or more of, for example, estimating the information, calculating the information, predicting the information, or retrieving the information from memory.

Further, this document may refer to“accessing” various pieces of information. Accessing the information can include one or more of, for example, receiving the information, retrieving the information (for example, from memory), storing the information, moving the information, copying the information, calculating the information, determining the information, predicting the information, or estimating the information.

Additionally, this document may refer to“receiving” various pieces of information. Receiving is, as with“accessing”, intended to be a broad term. Receiving the information can include one or more of, for example, accessing the information, or retrieving the information (for example, from memory). Further,“receiving” is typically involved, in one way or another, during operations such as, for example, storing the information, processing the information, transmitting the information, moving the information, copying the information, erasing the information, calculating the information, determining the information, predicting the information, or estimating the information.

It is to be appreciated that the use of any of the following 7”,“and/or”, and“at least one of”, for example, in the cases of“A/B”,“A and/or B” and“at least one of A and B”, is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of both options (A and B). As a further example, in the cases of“A, B, and/or C” and“at least one of A, B, and C”, such phrasing is intended to encompass the selection of the first listed option (A) only, or the selection of the second listed option (B) only, or the selection of the third listed option (C) only, or the selection of the first and the second listed options (A and B) only, or the selection of the first and third listed options (A and C) only, or the selection of the second and third listed options (B and C) only, or the selection of all three options (A and B and C). This may be extended, as is clear to one of ordinary skill in this and related arts, for as many items as are listed.

Also, as used herein, the word“signal” refers to, among other things, indicating something to a corresponding decoder. For example, in certain embodiments the encoder signals a particular one of a plurality of weights to be used for intra prediction reference arrays. In this way, in an embodiment the same parameter is used at both the encoder side and the decoder side. Thus, for example, an encoder can transmit (explicit signaling) a particular parameter to the decoder so that the decoder can use the same particular parameter. Conversely, if the decoder already has the particular parameter as well as others, then signaling can be used without transmitting (implicit signaling) to simply allow the decoder to know and select the particular parameter. By avoiding transmission of any actual functions, a bit savings is realized in various embodiments. It is to be appreciated that signaling can be accomplished in a variety of ways. For example, one or more syntax elements, flags, and so forth are used to signal information to a corresponding decoder in various embodiments. While the preceding relates to the verb form of the word“signal”, the word“signal” can also be used herein as a noun.

As will be evident to one of ordinary skill in the art, implementations can produce a variety of signals formatted to carry information that can be, for example, stored or transmitted. The information can include, for example, instructions for performing a method, or data produced by one of the described implementations. For example, a signal can be formatted to carry the bitstream of a described embodiment. Such a signal can be formatted, for example, as an electromagnetic wave (for example, using a radio frequency portion of spectrum) or as a baseband signal. The formatting can include, for example, encoding a data stream and modulating a carrier with the encoded data stream. The information that the signal carries can be, for example, analog or digital information. The signal can be transmitted over a variety of different wired or wireless links, as is known. The signal can be stored on a processor-readable medium.

Embodiments may include one or more of the following features or entities, alone or in combination, across various different claim categories and types:

• A bitstream or signal that includes one or more of the described syntax elements, or variations thereof.

• Creating and/or transmitting and/or receiving and/or decoding a bitstream or signal that includes one or more of the described syntax elements, or variations thereof.

• A TV, set-top box, cell phone, tablet, or other electronic device that performs in-loop filtering according to any of the embodiments described.

• A TV, set-top box, cell phone, tablet, or other electronic device that performs in-loop filtering according to any of the embodiments described, and that displays (e.g. using a monitor, screen, or other type of display) a resulting image. • A TV, set-top box, cell phone, tablet, or other electronic device that tunes (e.g. using a tuner) a channel to receive a signal including an encoded image, and performs in-loop filtering according to any of the embodiments described.

• A TV, set-top box, cell phone, tablet, or other electronic device that receives (e.g. using an antenna) a signal over the air that includes an encoded image, and performs in-loop filtering according to any of the embodiments described.

Various other generalized, as well as particularized, inventions and claims are also supported and contemplated throughout this disclosure.

Claims

1. A method for video encoding, comprising:

performing at least a portion of a Discrete Trigonometric Transform on a subset of samples comprising a block;

determining transform coefficients for the block using the transformed subset of samples; and,

encoding the block.

2. An apparatus, comprising:

a processor, configured to:

perform at least a portion of a Discrete Trigonometric Transform on a subset of samples comprising a block;

determine transform coefficients for the block using the transformed subset of samples; and,

encode the block.

3. A method, comprising:

performing at least a portion of an inverse Discrete Trigonometric Transform on a subset of coefficients comprising a block;

determining samples for the block using the inverse transformed subset of coefficients; and,

decoding the block.

4. An apparatus, comprising:

a processor, configured to:

perform at least a portion of an inverse Discrete Trigonometric Transform on a subset of coefficients comprising a block;

determine samples for the block using the inverse transformed subset of coefficients; and,

decode the block.

5. The method of claim 1 or claim 3, or the apparatus of claim 2 or claim 4, wherein said transform is applied for half of said coefficients when there are real valued inputs.

6. The method of claim 1 or claim 3, or the apparatus of claim 2 or claim 4, wherein said transform has reduced complexity by storing temporary values when there are complex valued inputs and real valued coefficients are computed.

7. The method of claim 1 or claim 3, or the apparatus of claim 2 or claim 4, wherein said transform is performed for real valued inputs and real valued coefficients by adding real valued inputs.

8. The method or the apparatus of claim 7, wherein half of said coefficients are computed.

9. The method of claim 1 or claim 3, or the apparatus of claim 2 or claim 4, wherein for real valued inputs and imaginary valued coefficients, half of coefficients are computed.

10. The method of claim 1 or claim 3, or the apparatus of claim 2 or claim 4, wherein half of operations are performed for implementing a Cooley-Tuckey transform by multiplying real values by complex Twiddle factors.

1 1. The method of claim 1 or claim 3, or the apparatus of claim 2 or claim 4, wherein a larger transform is decomposed into a plurality of smaller transforms using a prime factor approach.

12. A device comprising:

an apparatus according to any of claims 4 through 1 1 ; and at least one of (i) an antenna configured to receive a signal, the signal including the video block, (ii) a band limiter configured to limit the received signal to a band of frequencies that includes the video block, and (iii) a display configured to display an output representative of a video block.

13. A non-transitory computer readable medium containing data content generated according to the method of any one of claims 1 and 5 to 1 1 , or by the apparatus of any one of claims 2 and 5 to 1 1 , for playback using a processor.

14. A signal comprising video data generated according to the method of any one of claims 1 and 5 to 1 1 , or by the apparatus of any one of claims 2 and 5 to 1 1 , for playback using a processor.

15. A computer program product comprising instructions which, when the program is executed by a computer, cause the computer to carry out the method of any one of claim 1 , 3 and 5 to 1 1 .