CN105163126A - Hardware decoding method and device based on HEVC protocol - Google Patents
Hardware decoding method and device based on HEVC protocol Download PDFInfo
- Publication number
- CN105163126A CN105163126A CN201510559531.9A CN201510559531A CN105163126A CN 105163126 A CN105163126 A CN 105163126A CN 201510559531 A CN201510559531 A CN 201510559531A CN 105163126 A CN105163126 A CN 105163126A
- Authority
- CN
- China
- Prior art keywords
- module
- frame
- bit stream
- data
- processing module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
The invention discloses a hardware decoding method and device based on an HEVC protocol. The device comprises a processing module, a buffer module, an AMBA bus and a decoding module; the decoding module comprises an entropy decoding module, a decoding control module, a frame prediction module, a frame processing module, a data reconstruction module and a filtering processing module; the decoding control module is used for distributing code stream data obtained after entropy decoding according to an operation command to the frame prediction module and the frame processing module, and saving the distributed code stream data in the units of frame. When one frame of code stream data is wrong, the decoding control module is capable of recovering the frame of cached code stream data and re-transmitting the frame of code stream data; as a result, the security of video decoding is improved; in short, the hardware decoding device has wide market prospect in the field of integrated circuit design.
Description
Technical field
The present invention relates to integrated circuit (IC) design field, particularly relate to a kind of hardware decode method and apparatus based on HEVC agreement.
Background technology
Along with the development of science and technology and the progress of society, integrated circuit (IC) design is widely applied, increasing electronic equipment enters daily life, not only to have taken facility to daily life, also further promotes innovation and the research and development of science and technology simultaneously.In integrated circuit (IC) design field, coding and decoding video is wherein important one.
High efficiency Video coding HEVC (HighEfficiencyVideoCodec) is the International video coding standard of future generation of being combined by International Telecommunication Union (ITU) and Motion Picture Experts Group (MPEG) at present in formulation.With present international video standard H.264/AVC compared with, the code check of video, under the prerequisite ensureing identical image quality, can be reduced by 50%, that is reach the code efficiency of H.264 twice by HEVC.For realizing this goal, the computational complexity of HEVC improves 2 to 3 times.
The decoder of HEVC is resolve bit stream data in units of frame at decode procedure, but existing HEVC decoder can not realize controling effectively to each frame data, bit stream data control logic and arithmetic logic in decode procedure is all comparatively complicated, very easily occurs mistake.Simultaneously, existing HEVC decoder cannot manage in time to the bit stream data of mistake, carrying out resolving making a mistake once a certain frame data, data due to next frame need to use this frame data, then chain reaction can be caused, the whole mistake of data of resolving after causing, and then cause decoding unsuccessfully.
Summary of the invention
For this reason, need the technical scheme that a kind of hardware decode based on HEVC agreement is provided, cannot control effectively to each frame data in order to solve existing HEVC decoder, decoding error easily occur and the problem of effectively management cannot be carried out the bit stream data of mistake.
For achieving the above object, inventor provide a kind of hardware decoder based on HEVC agreement, described device comprises processing module, cache module, AMBA bus and decoder module, described processing module is connected with AMBA bus, and described AMBA bus is connected with register module, described cache module is connected with AMBA bus, and described AMBA bus is connected with decoder module; Described decoder module comprises entropy decoder module, decoding control block, frame prediction module, frame processing module, data reconstruction module, filtering processing module; Described entropy decoder module is connected with decoding control block, and described decoding control block is connected with frame prediction module, described frame processing module and data reconstruction model calling; Described decoding control block is connected with frame processing module, described frame processing module and data reconstruction model calling; Described data reconstruction module is connected with filtering processing module;
Described processing module is used for configuration register;
Described decoder module for initiating reading command, and passes through AMBA bus from described cache module readout code flow data;
Described entropy decoder module is used for carrying out entropy decoding to bit stream data, obtains the decoded bit stream data of entropy and operational order thereof;
Described decoding control block is used for, according to operational order, decoded for entropy bit stream data is distributed to frame prediction module and frame processing module, and stores in units of frame the bit stream data sent;
Described frame prediction module is used for carrying out frame predicted operation to the decoded bit stream data of entropy;
Described frame processing module is used for carrying out frame process operation to the decoded bit stream data of entropy;
Described data reconstruction module is used for the bit stream data after to frame prediction and frame process and is reconstructed;
Described filtering processing module is used for the data after to reconstruct and carries out filtering process;
Described decoder module writes instruction for initiating, and by AMBA bus, decoded bit stream data is write described cache module.
Further, described frame prediction module comprises intra-framed prediction module and Inter prediction module, and described intra-framed prediction module is used for carrying out infra-frame prediction operation to the decoded bit stream data of entropy; Described Inter prediction module is used for carrying out inter prediction operation to the decoded bit stream data of entropy.
Further, described bit stream data comprises colmv data, then described AMBA bus is also connected with described Inter prediction module, and described AMBA bus is used for colmv transfer of data to Inter prediction module.
Further, described frame processing module comprises residual noise reduction module, and described residual noise reduction module is used for carrying out inverse quantization and inverse transformation to residual error data.
Further, described frame prediction module, frame processing module, data reconstruction module, filtering processing module also have feedback function, whether described feedback function refers to that frame prediction module, frame processing module, data reconstruction module, filtering processing module verify present frame bit stream data respectively correct, if incorrect, sends rub-out signal to decoding control block; Described decoding control block also for receiving rub-out signal, and recovers the bit stream data that this frame stores.
Inventor additionally provides a kind of hardware decode method based on HEVC agreement, and described method is applied to the hardware decoder based on HEVC agreement; Described device comprises processing module, cache module, AMBA bus and decoder module, described processing module is connected with AMBA bus, described AMBA bus is connected with register module, and described cache module is connected with AMBA bus, and described AMBA bus is connected with decoder module; Described decoder module comprises entropy decoder module, decoding control block, frame prediction module, frame processing module, data reconstruction module, filtering processing module; Described entropy decoder module is connected with decoding control block, and described decoding control block is connected with frame prediction module, described frame processing module and data reconstruction model calling; Described decoding control block is connected with frame processing module, described frame processing module and data reconstruction model calling; Described data reconstruction module is connected with filtering processing module; Then said method comprising the steps of:
Processing module configuration register;
Decoder module initiates reading command, and by AMBA bus from described cache module readout code flow data, and bit stream data is decoded;
Decoder module initiates write instruction, and by AMBA bus, decoded bit stream data is write described cache module;
Decoder module carries out decoding to bit stream data and comprises the steps:
Entropy decoder module carries out entropy decoding to bit stream data, obtains the decoded bit stream data of entropy and operational order thereof;
Decoding control block is distributed to frame prediction module and frame processing module according to operational order to the decoded bit stream data of entropy, and stores in units of frame the bit stream data sent;
Frame prediction module carries out frame predicted operation to the decoded bit stream data of entropy, and frame processing module carries out frame process operation to the decoded bit stream data of entropy;
Data reconstruction module is reconstructed the bit stream data after frame prediction and frame process;
Filtering processing module carries out filtering process to the data after reconstruct.
Further, described frame prediction module comprises intra-framed prediction module and Inter prediction module, then described method comprises:
Intra-framed prediction module carries out infra-frame prediction operation to the decoded bit stream data of entropy;
Inter prediction module carries out inter prediction operation to the decoded bit stream data of entropy.
Further, described bit stream data comprises colmv data, then described AMBA bus is also connected with described Inter prediction module, then described method comprises:
AMBA bus by colmv transfer of data to Inter prediction module.
Further, described frame processing module comprises residual noise reduction module, then described method comprises:
Residual noise reduction module carries out inverse quantization and inverse transformation to residual error data.
Further, described frame prediction module, frame processing module, data reconstruction module, filtering processing module also has feedback function, then described method comprises step:
Whether described frame prediction module, frame processing module, data reconstruction module, filtering processing module verify present frame bit stream data respectively correct, if incorrect, send rub-out signal to decoding control block;
Decoding control block receives rub-out signal, and recovers the bit stream data that this frame stores.
Be different from prior art, the hardware decode method and apparatus based on HEVC agreement described in technique scheme, described device comprises processing module, cache module, AMBA bus and decoder module, described processing module is connected with AMBA bus, and described AMBA bus is connected with register module, described cache module is connected with AMBA bus, and described AMBA bus is connected with decoder module; Described decoder module comprises entropy decoder module, decoding control block, frame prediction module, frame processing module, data reconstruction module, filtering processing module; Described entropy decoder module is connected with decoding control block, and described decoding control block is connected with frame prediction module, described frame processing module and data reconstruction model calling; Described decoding control block is connected with frame processing module, described frame processing module and data reconstruction model calling; Described data reconstruction module is connected with filtering processing module; Then said method comprising the steps of: processing module configuration register; Decoder module initiates reading command, and by AMBA bus from described cache module readout code flow data, and bit stream data is decoded; Decoder module initiates write instruction, and by AMBA bus, decoded bit stream data is write described cache module; Decoder module carries out decoding to bit stream data and comprises the steps: that entropy decoder module carries out entropy decoding to bit stream data, obtains the decoded bit stream data of entropy and operational order thereof; Decoding control block is distributed to frame prediction module and frame processing module according to operational order to the decoded bit stream data of entropy, and stores in units of frame the bit stream data sent; Frame prediction module carries out frame predicted operation to the decoded bit stream data of entropy, and frame processing module carries out frame process operation to the decoded bit stream data of entropy; Data reconstruction module is reconstructed the bit stream data after frame prediction and frame process; Filtering processing module carries out filtering process to the data after reconstruct.Owing to being provided with decoding control block, thus distribution scheduling can be carried out to the bit stream data of entropy decoding, and in units of frame, buffer memory is carried out to bit stream data, when there is mistake in this frame bit stream data, just can recover data cached and again transmit, thus greatly reducing decode procedure complexity, and effective management and control can be carried out to the bit stream data of mistake, improve the fail safe of video decode, thus in integrated circuit (IC) design field, there are wide market prospects.
Accompanying drawing explanation
Fig. 1 for described in one embodiment of the invention the schematic diagram of the hardware decoder based on HEVC agreement;
Fig. 2 for described in one embodiment of the invention decoder module carry out the flow chart of decode procedure;
Fig. 3 for described in one embodiment of the invention the flow chart of the hardware decode method based on HEVC agreement.
Description of reference numerals:
101, processing module;
102, cache module;
103, decoder module;
104, entropy decoder module;
105, decoding control block;
106, frame prediction module; 116, Inter prediction module; 126, intra-framed prediction module;
107, frame processing module;
108, data reconstruction module;
109, filtering processing module.
Embodiment
By describe in detail technical scheme technology contents, structural feature, realized object and effect, coordinate accompanying drawing to be explained in detail below in conjunction with specific embodiment.
Refer to Fig. 1, for described in one embodiment of the invention the schematic diagram of the hardware decoder based on HEVC agreement; Described device comprises processing module 101, cache module 102, AMBA bus and decoder module 103, described processing module 101 is connected with AMBA bus, described AMBA bus is connected with register module, and described cache module 102 is connected with AMBA bus, and described AMBA bus is connected with decoder module 103; Described decoder module 103 comprises entropy decoder module 104, decoding control block 105, frame prediction module 106, frame processing module 107, data reconstruction module 108, filtering processing module 109; Described entropy decoder module is connected with decoding control block, and described decoding control block is connected with frame prediction module, and described frame processing module 107 is connected with data reconstruction module 108; Described decoding control block 105 is connected with frame processing module 107, and described frame processing module 107 is connected with data reconstruction module 108; Described data reconstruction module 108 is connected with filtering processing module 109;
Described processing module 101 is for configuration register;
Described decoder module 103 for initiating reading command, and passes through AMBA bus from described cache module 102 readout code flow data;
Described entropy decoder module 104, for carrying out entropy decoding to bit stream data, obtains the decoded bit stream data of entropy and operational order thereof;
Described decoding control block 105 for decoded for entropy bit stream data being distributed to frame prediction module and frame processing module according to operational order, and stores in units of frame the bit stream data sent;
Described frame prediction module 106 is for carrying out frame predicted operation to the decoded bit stream data of entropy;
Described frame processing module 107 is for carrying out frame process operation to the decoded bit stream data of entropy;
Described data reconstruction module 108 is for being reconstructed the bit stream data after frame prediction and frame process;
Described filtering processing module 109 is for carrying out filtering process to the data after reconstruct;
Described decoder module 110 writes instruction for initiating, and by AMBA bus, decoded bit stream data is write described cache module.
Use based on the hardware decoder of HEVC agreement, video is decoded time, first processing module configuration register.Described processing module is the electronic component with data processing function, such as CPU.Then decoder module initiates reading command, and by AMBA bus from described cache module readout code flow data.Described cache module is that any one has the electronic equipment of memory function.Data to be decoded are stored in cache module before the decoding, and decoder module can read bit stream data to be decoded by AMBA bus, then decodes again.After decoder module has been decoded to bit stream data, can initiate to write instruction, and by AMBA bus, decoded bit stream data be write described cache module, thus complete decode operation.
Decoder module carries out decode procedure to bit stream data, specifically comprises the following steps: first entropy decoder module carries out entropy decoding to bit stream data, obtains the decoded bit stream data of entropy and operational order thereof.Bit stream data, before carrying out entropy decoding, in order to save memory space, is stored in cache module often after overcompression.Thus carrying out needing in decode procedure first to carry out entropy decoding to the bit stream data in cache module, the decoded bit stream data of entropy and operational order thereof is obtained.
Then decoded for entropy bit stream data is distributed to frame prediction module and frame processing module according to operational order by decoding control block, and stores in units of frame the bit stream data sent.Video, in decode procedure, is decoded in units of frame.In order to when decoding makes a mistake, can recover the current frame data made a mistake in time, thus decoding control block is when being sent to frame prediction module and frame processing module by decoded for entropy bit stream data, can store the bit stream data sent.Preferably, in the present embodiment, described frame prediction module, frame processing module, data reconstruction module, filtering processing module also have feedback function, whether described feedback function refers to that frame prediction module, frame processing module, data reconstruction module, filtering processing module verify present frame bit stream data respectively correct, if incorrect, sends rub-out signal to decoding control block; ; Described decoding control block also for receiving rub-out signal, and recovers the bit stream data that this frame stores.The mode of decoding control block memory code flow data can adopt the mode of buffer memory, namely a memory space is opened up, for storing the bit stream data of present frame, if present frame decoding is correct, namely rub-out signal is not received, after then next frame data cover is stored in this memory space, proceed the decoding of next frame data; If current frame data is incorrect, namely there is some or multiple transmission rub-out signal in frame prediction module, frame processing module, data reconstruction module, filtering processing module to decoding control block, decoding control block is after receiving rub-out signal, first suspend and next frame bit stream data is transferred to frame prediction module and frame processing module, the present frame then resend in spatial cache is pre-stored in the bit stream data in memory space, proceed the decoding of this frame, after present frame decoding is correct, carries out the decode operation of next frame again.
Then frame prediction module carries out frame predicted operation to the decoded bit stream data of entropy.Preferably, in the present embodiment, described frame prediction module 106 comprises intra-framed prediction module 116 and Inter prediction module 126, and described intra-framed prediction module 116 is for carrying out infra-frame prediction operation to the decoded bit stream data of entropy; Described Inter prediction module 126 is for carrying out inter prediction operation to the decoded bit stream data of entropy.Inter prediction operation refers to that first the prediction data exported according to entropy decoding sub-module rebuilds motion vector, then reads in reference pixel according to motion vector, builds prediction signal eventually through interpolation, and specific algorithm is with reference to HEVC standard.In the present embodiment, described bit stream data comprises colmv data, then described AMBA bus is also connected with described Inter prediction module, and described AMBA bus is used for colmv transfer of data to Inter prediction module.Cache module needs to carry out except storing except the data of entropy decoding, and also stored for colmv data, described colmv data are reference image data, and described reference image data is supplied to inter prediction submodule and builds prediction signal.Infra-frame prediction operation refers to that first the prediction data exported according to entropy decoding sub-module determines the pattern of infra-frame prediction, and then utilize the boundary pixel in current predictive region to form prediction signal, specific algorithm is with reference to HEVC standard.
Decoding control block distribution is transferred to the bit stream data of frame processing module, frame processing module carries out frame process operation to the decoded bit stream data of entropy.In the present embodiment, described frame processing module comprises reorder module and residual noise reduction module.Described bit stream data comprises quantization parameter and quantizing factor.The module that reorders then derives scan pattern for the prediction data exported according to decoding control block, then rearranges order according to scan pattern to the quantization parameter that decoding control block exports.Described scan pattern comprises diagonal model, horizontal pattern and vertical mode three kinds, and specific algorithm is with reference to HEVC standard.The quantization parameter that described residual noise reduction module is used for the quantizing factor reorder module of decoding control block transmission exports carries out inverse quantization, then carries out inverse transformation, and specific algorithm is with reference to HEVC standard.
Then data reconstruction module is reconstructed the bit stream data after frame prediction and frame process.The input of data reconstruction module comprises the residual signals after inverse transformation and passes through the infra-frame prediction after predicting or Inter prediction signals, and data reconstruction module carries out Image Reconstruction according to the algorithm defined in HEVC standard.
And post filtering processing module carries out filtering process to the data after reconstruct.Because video is decoded at decode procedure in units of frame, between frame and frame, there is blocking effect, thus need the data after to reconstruct to carry out filtering process.Particularly, block elimination effect filter can be adopted to carry out filtering and the skew of pixel self adaptation, and the skew of pixel self adaptation is carried out after block-eliminating effect filtering, and specific algorithm is with reference to HEVC standard.Filtering processing module is functionally independent of foregoing prediction, inverse transformation and reconstruct submodule, therefore the maximum process data size supported can set more flexibly, in order to the expense of saving local storage improves operation efficiency simultaneously, the maximum process data size that can set the support of filtering processing module is identical with Image data reconstruction module.
So far, present frame bit stream data has been decoded, and then decoder module initiates write instruction, and by AMBA bus, decoded bit stream data is write described cache module.The Image Reconstruction signal being input as the output of data reconstruction module of filtering processing module, the final output image generated after block-eliminating effect filtering and pixel self adaptation migration processing, output image can be written to the reference image data of cache module as inter prediction simultaneously, namely as the inter prediction of colmv market demand in next frame image.
Refer to Fig. 2 and Fig. 3, and inventor additionally provides a kind of hardware decode method based on HEVC agreement, described method is applied to the hardware decoder based on HEVC agreement; Described device comprises processing module, cache module, AMBA bus and decoder module, described processing module is connected with AMBA bus, described AMBA bus is connected with register module, and described cache module is connected with AMBA bus, and described AMBA bus is connected with decoder module; Described decoder module comprises entropy decoder module, decoding control block, frame prediction module, frame processing module, data reconstruction module, filtering processing module; Described entropy decoder module is connected with decoding control block, and described decoding control block is connected with frame prediction module, described frame processing module and data reconstruction model calling; Described decoding control block is connected with frame processing module, described frame processing module and data reconstruction model calling; Described data reconstruction module is connected with filtering processing module; Then said method comprising the steps of:
First step S301 processing module configuration register is entered.Described processing module is the electronic component with data processing function, such as CPU.Then enter step S302 decoder module and initiate reading command, and by AMBA bus from described cache module readout code flow data, and bit stream data is decoded.Described cache module is that any one has the electronic equipment of memory function.Data to be decoded are stored in cache module before the decoding, and decoder module can read bit stream data to be decoded by AMBA bus, then decodes again.Then enter step S303 decoder module and initiate write instruction, and by AMBA bus, decoded bit stream data is write described cache module.
As shown in Figure 2, decoder module carries out decoding to bit stream data and comprises the steps:
First enter step S201 entropy decoder module and entropy decoding is carried out to bit stream data, obtain the decoded bit stream data of entropy and operational order thereof.Bit stream data, before carrying out entropy decoding, in order to save memory space, is stored in cache module often after overcompression.Thus carrying out needing in decode procedure first to carry out entropy decoding to the bit stream data in cache module, the decoded bit stream data of entropy and operational order thereof is obtained.
Then enter step S202 decoding control block, according to operational order, frame prediction module and frame processing module are distributed to the decoded bit stream data of entropy, and the bit stream data sent is stored in units of frame.Video, in decode procedure, is decoded in units of frame.In order to when decoding makes a mistake, can recover the current frame data made a mistake in time, thus decoding control block is when being sent to frame prediction module and frame processing module by decoded for entropy bit stream data, can store the bit stream data sent.Preferably, in the present embodiment, described frame prediction module, frame processing module, data reconstruction module, filtering processing module also have feedback function, whether described feedback function refers to that frame prediction module, frame processing module, data reconstruction module, filtering processing module verify present frame bit stream data respectively correct, if incorrect, sends rub-out signal to decoding control block; Described decoding control block also for receiving rub-out signal, and recovers the bit stream data that this frame stores.The mode of decoding control block memory code flow data can adopt the mode of buffer memory, namely a memory space is opened up, for storing the bit stream data of present frame, if present frame decoding is correct, namely rub-out signal is not received, after then next frame data cover is stored in this memory space, proceed the decoding of next frame data; If current frame data is incorrect, namely there is some or multiple transmission rub-out signal in frame prediction module, frame processing module, data reconstruction module, filtering processing module to decoding control block, decoding control block is after receiving rub-out signal, first suspend and next frame bit stream data is transferred to frame prediction module and frame processing module, the present frame then resend in spatial cache is pre-stored in the bit stream data in memory space, proceed the decoding of this frame, after present frame decoding is correct, carries out the decode operation of next frame again.
Then enter step S03 frame prediction module and carry out frame predicted operation to the decoded bit stream data of entropy, frame processing module carries out frame process operation to the decoded bit stream data of entropy.Preferably, in the present embodiment, described frame prediction module 106 comprises intra-framed prediction module 116 and Inter prediction module 126, and described intra-framed prediction module 116 is for carrying out infra-frame prediction operation to the decoded bit stream data of entropy; Described Inter prediction module 126 is for carrying out inter prediction operation to the decoded bit stream data of entropy.Inter prediction operation refers to that first the prediction data exported according to entropy decoding sub-module rebuilds motion vector, then reads in reference pixel according to motion vector, builds prediction signal eventually through interpolation, and specific algorithm is with reference to HEVC standard.In the present embodiment, described bit stream data comprises colmv data, then described AMBA bus is also connected with described Inter prediction module, and described AMBA bus is used for colmv transfer of data to Inter prediction module.Cache module needs to carry out except storing except the data of entropy decoding, and also stored for colmv data, described colmv data are reference image data, and described reference image data is supplied to inter prediction submodule and builds prediction signal.Infra-frame prediction operation refers to that first the prediction data exported according to entropy decoding sub-module determines the pattern of infra-frame prediction, and then utilize the boundary pixel in current predictive region to form prediction signal, specific algorithm is with reference to HEVC standard.
Decoding control block distribution is transferred to the bit stream data of frame processing module, frame processing module carries out frame process operation to the decoded bit stream data of entropy.In the present embodiment, described frame processing module comprises reorder module and residual noise reduction module.Described bit stream data comprises quantization parameter and quantizing factor.The module that reorders then derives scan pattern for the prediction data exported according to decoding control block, then rearranges order according to scan pattern to the quantization parameter that decoding control block exports.Described scan pattern comprises diagonal model, horizontal pattern and vertical mode three kinds, and specific algorithm is with reference to HEVC standard.The quantization parameter that described residual noise reduction module is used for the quantizing factor reorder module of decoding control block transmission exports carries out inverse quantization, then carries out inverse transformation, and specific algorithm is with reference to HEVC standard.
Then enter step S204 data reconstruction module to be reconstructed the bit stream data after frame prediction and frame process.The input of data reconstruction module comprises the residual signals after inverse transformation and passes through the infra-frame prediction after predicting or Inter prediction signals, and data reconstruction module carries out Image Reconstruction according to the algorithm defined in HEVC standard.
Then enter step S205 filtering processing module and filtering process is carried out to the data after reconstruct.Because video is decoded at decode procedure in units of frame, between frame and frame, there is blocking effect, thus need the data after to reconstruct to carry out filtering process.Particularly, block elimination effect filter can be adopted to carry out filtering and the skew of pixel self adaptation, and the skew of pixel self adaptation is carried out after block-eliminating effect filtering, and specific algorithm is with reference to HEVC standard.Filtering processing module is functionally independent of foregoing prediction, inverse transformation and reconstruct submodule, therefore the maximum process data size supported can set more flexibly, in order to the expense of saving local storage improves operation efficiency simultaneously, the maximum process data size that can set the support of filtering processing module is identical with Image data reconstruction module.
So far, present frame bit stream data has been decoded, and then can enter step S303 decoder module and initiate write instruction, and by AMBA bus, decoded bit stream data be write described cache module.The Image Reconstruction signal being input as the output of data reconstruction module of filtering processing module, the final output image generated after block-eliminating effect filtering and pixel self adaptation migration processing, output image can be written to the reference image data of cache module as inter prediction simultaneously, namely as the inter prediction of colmv market demand in next frame image.
The hardware decode method and apparatus based on HEVC agreement described in technique scheme, described device comprises processing module, cache module, AMBA bus and decoder module, described processing module is connected with AMBA bus, described AMBA bus is connected with register module, and described cache module is connected with AMBA bus, and described AMBA bus is connected with decoder module; Described decoder module comprises entropy decoder module, decoding control block, frame prediction module, frame processing module, data reconstruction module, filtering processing module; Described entropy decoder module is connected with decoding control block, and described decoding control block is connected with frame prediction module, described frame processing module and data reconstruction model calling; Described decoding control block is connected with frame processing module, described frame processing module and data reconstruction model calling; Described data reconstruction module is connected with filtering processing module; Then said method comprising the steps of: processing module configuration register; Decoder module initiates reading command, and by AMBA bus from described cache module readout code flow data, and bit stream data is decoded; Decoder module initiates write instruction, and by AMBA bus, decoded bit stream data is write described cache module; Decoder module carries out decoding to bit stream data and comprises the steps: that entropy decoder module carries out entropy decoding to bit stream data, obtains the decoded bit stream data of entropy and operational order thereof; Decoding control block is distributed to frame prediction module and frame processing module according to operational order to the decoded bit stream data of entropy, and stores in units of frame the bit stream data sent; Frame prediction module carries out frame predicted operation to the decoded bit stream data of entropy, and frame processing module carries out frame process operation to the decoded bit stream data of entropy; Data reconstruction module is reconstructed the bit stream data after frame prediction and frame process; Filtering processing module carries out filtering process to the data after reconstruct.Owing to being provided with decoding control block, thus distribution scheduling can be carried out to the bit stream data of entropy decoding, and in units of frame, buffer memory is carried out to bit stream data, when there is mistake in this frame bit stream data, just can recover data cached and again transmit, thus greatly reducing decode procedure complexity, and effective management and control can be carried out to the bit stream data of mistake, improve the fail safe of video decode, thus in integrated circuit (IC) design field, there are wide market prospects.
It should be noted that, in this article, the such as relational terms of first and second grades and so on is only used for an entity or operation to separate with another entity or operating space, and not necessarily requires or imply the relation that there is any this reality between these entities or operation or sequentially.And, term " comprises ", " comprising " or its any other variant are intended to contain comprising of nonexcludability, thus make to comprise the process of a series of key element, method, article or terminal equipment and not only comprise those key elements, but also comprise other key elements clearly do not listed, or also comprise by the intrinsic key element of this process, method, article or terminal equipment.When not more restrictions, the key element limited by statement " comprising ... " or " comprising ... ", and be not precluded within process, method, article or the terminal equipment comprising described key element and also there is other key element.In addition, in this article, " be greater than ", " being less than ", " exceeding " etc. be interpreted as and do not comprise this number; " more than ", " below ", " within " etc. be interpreted as and comprise this number.
Those skilled in the art should understand, the various embodiments described above can be provided as method, device or computer program.These embodiments can adopt the form of complete hardware embodiment, completely software implementation or the embodiment in conjunction with software and hardware aspect.The hardware that all or part of step in the method that the various embodiments described above relate to can carry out instruction relevant by program has come, described program can be stored in the storage medium that computer equipment can read, for performing all or part of step described in the various embodiments described above method.Described computer equipment, includes but not limited to: personal computer, server, all-purpose computer, special-purpose computer, the network equipment, embedded device, programmable device, intelligent mobile terminal, intelligent home device, wearable intelligent equipment, vehicle intelligent equipment etc.; Described storage medium, includes but not limited to: the storage of RAM, ROM, magnetic disc, tape, CD, flash memory, USB flash disk, portable hard drive, storage card, memory stick, the webserver, network cloud storage etc.
The various embodiments described above describe with reference to the flow chart of method, equipment (system) and computer program according to embodiment and/or block diagram.Should understand can by the combination of the flow process in each flow process in computer program instructions realization flow figure and/or block diagram and/or square frame and flow chart and/or block diagram and/or square frame.These computer program instructions can being provided to the processor of computer equipment to produce a machine, making the instruction performed by the processor of computer equipment produce device for realizing the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
These computer program instructions also can be stored in can in the computer equipment readable memory that works in a specific way of vectoring computer equipment, the instruction making to be stored in this computer equipment readable memory produces the manufacture comprising command device, and this command device realizes the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
These computer program instructions also can be loaded on computer equipment, make to perform sequence of operations step on a computing device to produce computer implemented process, thus the instruction performed on a computing device is provided for the step realizing the function of specifying in flow chart flow process or multiple flow process and/or block diagram square frame or multiple square frame.
Although be described the various embodiments described above; but those skilled in the art are once obtain the basic creative concept of cicada; then can make other change and amendment to these embodiments; so the foregoing is only embodiments of the invention; not thereby scope of patent protection of the present invention is limited; every utilize specification of the present invention and accompanying drawing content to do equivalent structure or equivalent flow process conversion; or be directly or indirectly used in other relevant technical fields, be all in like manner included within scope of patent protection of the present invention.
Claims (10)
1. the hardware decoder based on HEVC agreement, it is characterized in that, described device comprises processing module, cache module, AMBA bus and decoder module, described processing module is connected with AMBA bus, and described AMBA bus is connected with register module, described cache module is connected with AMBA bus, and described AMBA bus is connected with decoder module; Described decoder module comprises entropy decoder module, decoding control block, frame prediction module, frame processing module, data reconstruction module, filtering processing module; Described entropy decoder module is connected with decoding control block, and described decoding control block is connected with frame prediction module, described frame processing module and data reconstruction model calling; Described decoding control block is connected with frame processing module, described frame processing module and data reconstruction model calling; Described data reconstruction module is connected with filtering processing module;
Described processing module is used for configuration register;
Described decoder module for initiating reading command, and passes through AMBA bus from described cache module readout code flow data;
Described entropy decoder module is used for carrying out entropy decoding to bit stream data, obtains the decoded bit stream data of entropy and operational order thereof;
Described decoding control block is used for, according to operational order, decoded for entropy bit stream data is distributed to frame prediction module and frame processing module, and stores in units of frame the bit stream data sent;
Described frame prediction module is used for carrying out frame predicted operation to the decoded bit stream data of entropy;
Described frame processing module is used for carrying out frame process operation to the decoded bit stream data of entropy;
Described data reconstruction module is used for the bit stream data after to frame prediction and frame process and is reconstructed;
Described filtering processing module is used for the data after to reconstruct and carries out filtering process;
Described decoder module writes instruction for initiating, and by AMBA bus, decoded bit stream data is write described cache module.
2. as claimed in claim 1 based on the hardware decoder of HEVC agreement, it is characterized in that, described frame prediction module comprises intra-framed prediction module and Inter prediction module, and described intra-framed prediction module is used for carrying out infra-frame prediction operation to the decoded bit stream data of entropy; Described Inter prediction module is used for carrying out inter prediction operation to the decoded bit stream data of entropy.
3. as claimed in claim 2 based on the hardware decoder of HEVC agreement, it is characterized in that, described bit stream data comprises colmv data, then described AMBA bus is also connected with described Inter prediction module, and described AMBA bus is used for colmv transfer of data to Inter prediction module.
4. as claimed in claim 1 based on the hardware decoder of HEVC agreement, it is characterized in that, described frame processing module comprises residual noise reduction module, and described residual noise reduction module is used for carrying out inverse quantization and inverse transformation to residual error data.
5. as claimed in claim 1 based on the hardware decoder of HEVC agreement, it is characterized in that, described frame prediction module, frame processing module, data reconstruction module, filtering processing module also have feedback function, whether described feedback function refers to that frame prediction module, frame processing module, data reconstruction module, filtering processing module verify present frame bit stream data respectively correct, if incorrect, sends rub-out signal to decoding control block; Described decoding control block also for receiving rub-out signal, and recovers the bit stream data that this frame stores.
6. based on a hardware decode method for HEVC agreement, it is characterized in that, described method is applied to the hardware decoder based on HEVC agreement; Described device comprises processing module, cache module, AMBA bus and decoder module, described processing module is connected with AMBA bus, described AMBA bus is connected with register module, and described cache module is connected with AMBA bus, and described AMBA bus is connected with decoder module; Described decoder module comprises entropy decoder module, decoding control block, frame prediction module, frame processing module, data reconstruction module, filtering processing module; Described entropy decoder module is connected with decoding control block, and described decoding control block is connected with frame prediction module, described frame processing module and data reconstruction model calling; Described decoding control block is connected with frame processing module, described frame processing module and data reconstruction model calling; Described data reconstruction module is connected with filtering processing module; Then said method comprising the steps of:
Processing module configuration register;
Decoder module initiates reading command, and by AMBA bus from described cache module readout code flow data, and bit stream data is decoded;
Decoder module initiates write instruction, and by AMBA bus, decoded bit stream data is write described cache module;
Decoder module carries out decoding to bit stream data and comprises the steps:
Entropy decoder module carries out entropy decoding to bit stream data, obtains the decoded bit stream data of entropy and operational order thereof;
Decoding control block is distributed to frame prediction module and frame processing module according to operational order to the decoded bit stream data of entropy, and stores in units of frame the bit stream data sent;
Frame prediction module carries out frame predicted operation to the decoded bit stream data of entropy, and frame processing module carries out frame process operation to the decoded bit stream data of entropy;
Data reconstruction module is reconstructed the bit stream data after frame prediction and frame process;
Filtering processing module carries out filtering process to the data after reconstruct.
7., as claimed in claim 6 based on the hardware decode method of HEVC agreement, it is characterized in that, described frame prediction module comprises intra-framed prediction module and Inter prediction module, then described method comprises:
Intra-framed prediction module carries out infra-frame prediction operation to the decoded bit stream data of entropy;
Inter prediction module carries out inter prediction operation to the decoded bit stream data of entropy.
8., as claimed in claim 6 based on the hardware decode method of HEVC agreement, it is characterized in that, described bit stream data comprises colmv data, then described AMBA bus is also connected with described Inter prediction module, then described method comprises:
AMBA bus by colmv transfer of data to Inter prediction module.
9., as claimed in claim 6 based on the hardware decode method of HEVC agreement, it is characterized in that, described frame processing module comprises residual noise reduction module, then described method comprises:
Residual noise reduction module carries out inverse quantization and inverse transformation to residual error data.
10., as claimed in claim 6 based on the hardware decode method of HEVC agreement, it is characterized in that, described frame prediction module, frame processing module, data reconstruction module, filtering processing module also have feedback function, then described method comprises step:
Whether frame prediction module, frame processing module, data reconstruction module, filtering processing module verify present frame bit stream data respectively correct, if incorrect, send rub-out signal to decoding control block;
Decoding control block receives rub-out signal, and recovers the bit stream data that this frame stores.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510559531.9A CN105163126B (en) | 2015-09-06 | 2015-09-06 | A kind of hardware coding/decoding method and device based on HEVC agreements |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510559531.9A CN105163126B (en) | 2015-09-06 | 2015-09-06 | A kind of hardware coding/decoding method and device based on HEVC agreements |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN105163126A true CN105163126A (en) | 2015-12-16 |
| CN105163126B CN105163126B (en) | 2018-05-25 |
Family
ID=54803866
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201510559531.9A Active CN105163126B (en) | 2015-09-06 | 2015-09-06 | A kind of hardware coding/decoding method and device based on HEVC agreements |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105163126B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105472390A (en) * | 2015-12-25 | 2016-04-06 | 福州瑞芯微电子股份有限公司 | video decoding method and system |
| CN105554507B (en) * | 2016-03-01 | 2018-10-02 | 福州瑞芯微电子股份有限公司 | A kind of HEVC SAO hardware computing device and method |
| CN109936746A (en) * | 2016-12-30 | 2019-06-25 | 深圳市大疆创新科技有限公司 | Image processing method and equipment |
| CN110381323A (en) * | 2018-04-12 | 2019-10-25 | 福州瑞芯微电子股份有限公司 | Frame motion vector information lossless compressibility and method are assisted based on inter-prediction |
| US11070732B2 (en) | 2016-12-30 | 2021-07-20 | SZ DJI Technology Co., Ltd. | Method for image processing, device, unmanned aerial vehicle, and receiver |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103024389A (en) * | 2012-12-24 | 2013-04-03 | 芯原微电子(北京)有限公司 | HEVC (high efficiency video coding) decoding device and method |
| US20130188881A1 (en) * | 2012-01-19 | 2013-07-25 | Sharp Laboratories Of America, Inc. | Reducing reference picture set signal overhead on an electronic device |
| CN103873861A (en) * | 2014-02-24 | 2014-06-18 | 西南交通大学 | Coding mode selection method for HEVC (high efficiency video coding) |
| CN104410864A (en) * | 2014-11-07 | 2015-03-11 | 太原科技大学 | Residual energy-based error hiding method in HEVC (High Efficiency Video Coding) |
-
2015
- 2015-09-06 CN CN201510559531.9A patent/CN105163126B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130188881A1 (en) * | 2012-01-19 | 2013-07-25 | Sharp Laboratories Of America, Inc. | Reducing reference picture set signal overhead on an electronic device |
| CN103024389A (en) * | 2012-12-24 | 2013-04-03 | 芯原微电子(北京)有限公司 | HEVC (high efficiency video coding) decoding device and method |
| CN103873861A (en) * | 2014-02-24 | 2014-06-18 | 西南交通大学 | Coding mode selection method for HEVC (high efficiency video coding) |
| CN104410864A (en) * | 2014-11-07 | 2015-03-11 | 太原科技大学 | Residual energy-based error hiding method in HEVC (High Efficiency Video Coding) |
Non-Patent Citations (1)
| Title |
|---|
| KIM TAEHONG，HONG JUNG-HYUN，CHUNG KI-SEOK: "AN EFFICIENT HARDWARE AND SOFTWARE CO-VERIFICATION METHOD FOR HEVC DECODERS", 《2014 4TH IEEE INTERNATIONAL CONFERENCE ON NETWORK INFRASTRUCTURE AND DIGITAL CONTENT》 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105472390A (en) * | 2015-12-25 | 2016-04-06 | 福州瑞芯微电子股份有限公司 | video decoding method and system |
| CN105472390B (en) * | 2015-12-25 | 2018-05-25 | 福州瑞芯微电子股份有限公司 | A kind of video encoding/decoding method and system |
| CN105554507B (en) * | 2016-03-01 | 2018-10-02 | 福州瑞芯微电子股份有限公司 | A kind of HEVC SAO hardware computing device and method |
| CN109936746A (en) * | 2016-12-30 | 2019-06-25 | 深圳市大疆创新科技有限公司 | Image processing method and equipment |
| US10924745B2 (en) | 2016-12-30 | 2021-02-16 | SZ DJI Technology Co., Ltd. | Image processing method and device |
| CN109936746B (en) * | 2016-12-30 | 2021-07-16 | 深圳市大疆创新科技有限公司 | Image processing method and apparatus |
| US11070732B2 (en) | 2016-12-30 | 2021-07-20 | SZ DJI Technology Co., Ltd. | Method for image processing, device, unmanned aerial vehicle, and receiver |
| CN110381323A (en) * | 2018-04-12 | 2019-10-25 | 福州瑞芯微电子股份有限公司 | Frame motion vector information lossless compressibility and method are assisted based on inter-prediction |
| CN110381323B (en) * | 2018-04-12 | 2021-10-26 | 福州瑞芯微电子股份有限公司 | Inter-frame prediction-based lossless compression system and method for assisting frame motion vector information |
Also Published As
| Publication number | Publication date |
|---|---|
| CN105163126B (en) | 2018-05-25 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105163126A (en) | Hardware decoding method and device based on HEVC protocol | |
| US11949868B2 (en) | Method and device for selecting context model of quantization coefficient end flag bit | |
| CN107277505B (en) | AVS-2 video decoder device based on software and hardware partition | |
| KR20120090756A (en) | Codeword assignment for intra chroma mode signaling for hevc | |
| US20220279224A1 (en) | Systems and methods for video processing | |
| CN111405289B (en) | Partial decoding circuit and partial encoding circuit | |
| CN106162192A (en) | Process the method and apparatus of video data | |
| GB2519289A (en) | Method and apparatus for displacement vector component transformation in video coding and decoding | |
| CN109379591A (en) | Picture code-transferring method, electronic device and computer readable storage medium | |
| CN103327340A (en) | Method and device for searching integer | |
| US11902524B2 (en) | Decoding method and device for quantization block, video decoding method, and electronic device | |
| CN116389763B (en) | Video coding method and device based on multiple encoders | |
| CN110933444B (en) | Bit width value storage method and device | |
| CN110933413A (en) | Video frame processing method and device | |
| CN112449185B (en) | Video decoding method, video encoding device, video encoding medium, and electronic apparatus | |
| US20220094984A1 (en) | Unrestricted intra content to improve video quality of real-time encoding | |
| CN101583035B (en) | Access method, device and system of audio frequency and video file | |
| Silveira et al. | A real-time architecture for reference frame compression for high definition video coders | |
| CN117528118A (en) | Decoding method and device, encoding and decoding system and storage medium | |
| CN110677681A (en) | Video coding and decoding method and device and terminal equipment | |
| CN114598888A (en) | Method, apparatus and medium for encoding and decoding string vector | |
| US9866844B2 (en) | Method, system and device for image and video coding | |
| CN115086659A (en) | Image encoding and decoding method, encoding device, decoding device, and storage medium | |
| WO2020078253A1 (en) | Transform and inverse transform methods and devices for image block | |
| CN105472398A (en) | Video in-loop filtering and decoding method and apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 350003 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee after: Ruixin Microelectronics Co., Ltd Address before: 350003 building, No. 89, software Avenue, Gulou District, Fujian, Fuzhou 18, China Patentee before: Fuzhou Rockchips Electronics Co.,Ltd. |
|
| CP01 | Change in the name or title of a patent holder |