CN101636828B - Active matrix substrate - Google Patents
Active matrix substrate Download PDFInfo
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- CN101636828B CN101636828B CN2008800085892A CN200880008589A CN101636828B CN 101636828 B CN101636828 B CN 101636828B CN 2008800085892 A CN2008800085892 A CN 2008800085892A CN 200880008589 A CN200880008589 A CN 200880008589A CN 101636828 B CN101636828 B CN 101636828B
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- film transistor
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- matrix substrate
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- 239000000758 substrate Substances 0.000 title claims abstract description 128
- 239000011159 matrix material Substances 0.000 title claims abstract description 123
- 239000004065 semiconductor Substances 0.000 claims description 99
- 239000010408 film Substances 0.000 claims description 47
- 239000010409 thin film Substances 0.000 claims description 43
- 230000002093 peripheral effect Effects 0.000 claims description 8
- 238000005247 gettering Methods 0.000 abstract description 34
- 239000010410 layer Substances 0.000 description 84
- 238000005530 etching Methods 0.000 description 29
- 230000007547 defect Effects 0.000 description 23
- 230000000052 comparative effect Effects 0.000 description 20
- 239000003054 catalyst Substances 0.000 description 19
- 238000000034 method Methods 0.000 description 13
- 239000012535 impurity Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 8
- 239000004020 conductor Substances 0.000 description 7
- 238000010586 diagram Methods 0.000 description 7
- 239000004973 liquid crystal related substance Substances 0.000 description 7
- 238000002425 crystallisation Methods 0.000 description 6
- 239000000654 additive Substances 0.000 description 4
- 230000000996 additive effect Effects 0.000 description 4
- 230000008025 crystallization Effects 0.000 description 4
- 230000008676 import Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 229910052759 nickel Inorganic materials 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 230000002950 deficient Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 230000001314 paroxysmal effect Effects 0.000 description 3
- 229910052698 phosphorus Inorganic materials 0.000 description 3
- 239000011574 phosphorus Substances 0.000 description 3
- 230000033228 biological regulation Effects 0.000 description 2
- 239000011248 coating agent Substances 0.000 description 2
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- 230000005764 inhibitory process Effects 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- MQRWBMAEBQOWAF-UHFFFAOYSA-N acetic acid;nickel Chemical compound [Ni].CC(O)=O.CC(O)=O MQRWBMAEBQOWAF-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
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- 239000012467 final product Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 229940078494 nickel acetate Drugs 0.000 description 1
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- 229910052710 silicon Inorganic materials 0.000 description 1
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- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1277—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor using a crystallisation promoting species, e.g. local introduction of Ni catalyst
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Abstract
The present invention provides an active matrix substrate (100), which satisfies d2 > d1, and d2 + A1/2 > d3 + L1/2, if the length, which is made by projecting the shortest segment joining a channel region (134) and a gettering region (112) on the straight line joining the channel region (134) of a TFT (130) and a source contact portion, is designated by d1, if the length from the channel region (134) to a source contact portion (132c) is designated by d2, if the length from the channel region (134) to a first end portion (110a) is designated by d3, if the length of the first end portion (110a) is designated by L1, and if the length of the source contact portion (132c) is designated by A1.
Description
Technical field
The present invention relates to the active-matrix substrate that in liquid crystal indicator etc., uses.
Background technology
In recent years, studied widely by the technology of the semiconductor layer (hereinafter referred to as crystalline semiconductor layer) that the amorphous semiconductor layer crystallization that forms on insulated substrates such as glass substrate made have crystalline texture.Crystalline semiconductor layer for example is many crystalline semiconductor layer, micro-crystallization attitude semiconductor layer, the thin-film transistor (Thin FilmTransistor:TFT) that utilizes crystalline semiconductor layer to make is compared with the TFT that utilizes the manufacturing of amorphous semiconductor layer, has very high charge carrier degree of excursion.Therefore, the pixel that is applicable to the viewing area of the active-matrix substrate that the driver of display unit (for example liquid crystal indicator) is one-piece type is utilized the crystalline semiconductor layer manufacturing with the drive circuit of TFT and neighboring area with TFT.
As the method that makes the crystallization of amorphous semiconductor layer, known have a CGS (continuous grainsilicon: method continuous crystallisation silicon) that adds catalyst elements (for example nickel) and carry out heat treated in the amorphous semiconductor layer, by this method, can form the good crystalline semiconductor layer of the orientation unanimity of crystallization with the heat treated of low temperature, short time.But, residual when catalyst elements is arranged in the channel region under the situation of utilizing CGS manufactured crystalline semiconductor layer, the situation that exists the turn-off current of TFT to increase abruptly.Therefore, known have be provided for the getter area of catalyst elements gettering technology (for example, with reference to patent documentation 1) with the paroxysmal increase that suppresses turn-off current.
Figure 13 is illustrated in disclosed semiconductor device 800 in the patent documentation 1.The crystalline semiconductor layer 810 of semiconductor device 800 has getter area 812,814 in its end.Getter area 812 and source region 832 adjacent settings make and guarantee from the source region 832 paths to the electric charge of channel region 834, and source region 832 is connected with source electrode 872 near the source electrode contact site 832c that is positioned at the centre wherein.In addition, getter area 814 and drain region 836 adjacent settings make and guarantee path from channel region 834 electric charge of 836 to the drain region, and drain region 836 is connected with drain electrode 882 near the source electrode contact site 836c that is positioned at the centre wherein.In getter area 812,814, import VA family elements such as phosphorus is arranged,, make the catalyst elements that remains in channel region 834 move (gettering), thereby suppress the sudden increase of the turn-off current of TFT by heating.
Patent documentation 1: TOHKEMY 2006-128469 communique
Summary of the invention
Even as patent documentation 1 disclosed semiconductor device, be provided with under the situation of getter area, when the gettering of the catalyst elements in the channel region is abundant inadequately, also there is the situation of the sudden increase of turn-off current of TFT.
In addition, (Gate-drain Overlapped LightlyDoped Drain: grid leak overlapping lightly doped drain) TFT of the structure drive circuit that is suitable as active-matrix substrate uses with TFT the good GOLDD of long-term reliability, relative therewith, (Lightly Doped Drain: lightly doped drain) TFT of structure is suitable as pixel and uses with TFT to be suitable for the reduction of turn-off current and the LDD of withstand voltage stabilisation.Semiconductor layer at the TFT of LDD structure, not to be provided with the low concentration impurity zone with the overlapping mode of gate electrode, therefore, longer than the drive circuit of neighboring area with the pixel of viewing area with TFT with gate electrode overlapping areas (that is channel region) in the semiconductor layer of TFT and the distance between the getter area.Therefore, pixel becomes insufficient easily with the gettering of TFT.When pixel increases abruptly with the turn-off current among the TFT, can in display unit, produce point defect.For example, if display unit is normal black liquid crystal indicator, then carrying out grey middle gray that potential difference the most easily is identified when showing, can produce the point of light/dark balance with respect to surrounding pixel, in addition, when display unit is the liquid crystal indicator of Chang Bai, can produce the bright spot of light color with respect to surrounding pixel.
For the sudden increase of the turn-off current that suppresses TFT, consider getter area is configured near the of channel region and mode that the gettering performance is improved.But the application's inventor finds, is just merely shortening under the situation of the distance between getter area and the channel region, produces between grid bus and the source bus line and leaks, and produces line defect in display unit.
The present invention finishes in view of the above problems, and its purpose is, provide the turn-off current that can suppress TFT sudden increase and can the suppressor grid bus and source bus line between the active-matrix substrate of generation of leakage.
Active-matrix substrate of the present invention comprises: semiconductor layer; Thin-film transistor element, it comprises the first film transistor, above-mentioned the first film transistor has source region, channel region and the drain region that is arranged at above-mentioned semiconductor layer; Grid bus; Source bus line; And pixel electrode, the transistorized source region of above-mentioned the first film comprises the source electrode contact site, above-mentioned semiconductor layer has first getter area adjacent with the transistorized source region of above-mentioned the first film, above-mentioned semiconductor layer comprises first end, the second end and the central portion between above-mentioned first end and above-mentioned the second end, above-mentioned first end has the width bigger than above-mentioned central portion, be provided with a part and above-mentioned first getter area of the transistorized source region of above-mentioned the first film that comprises above-mentioned source electrode contact site at above-mentioned first end, above-mentioned first getter area is positioned at the outer peripheral portion of the above-mentioned first end except the path from above-mentioned source electrode contact site to the electric charge of the transistorized above-mentioned channel region of above-mentioned the first film, makes making that to connect the length that the line segment of transistorized channel region of above-mentioned the first film and above-mentioned first getter area is projected on the straight line that is connected transistorized channel region of above-mentioned the first film and above-mentioned source electrode contact site with beeline be d
1, making the length from the transistorized channel region of above-mentioned the first film to above-mentioned source electrode contact site of above-mentioned semiconductor layer is d
2, making the length from the transistorized above-mentioned channel region of above-mentioned the first film to above-mentioned first end of above-mentioned semiconductor layer is d
3, order is L along the length of the above-mentioned first end of the straight line that connects transistorized channel region of above-mentioned the first film and above-mentioned source electrode contact site
1, order is A along the length of the above-mentioned source electrode contact site of the straight line that connects transistorized channel region of above-mentioned the first film and above-mentioned source electrode contact site
1, then satisfy d
2＞d
1〉=d
3And d
2+ A
1/ 2＞d
3+ L
1/ 2.
In one embodiment, satisfy d
2-d
1＞L
1/ 6.
In one embodiment, satisfy L
1＞1.5 * A
1.
In one embodiment, d
1And d
2Satisfy 3 μ m≤d
1≤ 13 μ m, 8 μ m≤d
2≤ 30 μ m.
In one embodiment, at least a portion of above-mentioned central portion is to extend abreast with overlapping mode and the above-mentioned source bus line of above-mentioned source bus line.
In one embodiment, at least a portion of above-mentioned first end and above-mentioned source bus line are overlapping.
In one embodiment, above-mentioned active-matrix substrate also possesses auxiliary capacitance line, and the distance that makes above-mentioned grid bus and above-mentioned auxiliary capacitance line is B, then satisfies B 〉=2d
2+ A
1
In one embodiment, above-mentioned thin-film transistor element also comprises second thin-film transistor, above-mentioned second thin-film transistor has source region, channel region and the drain region that is arranged at above-mentioned semiconductor layer, above-mentioned the first film transistor and the above-mentioned second thin-film transistor arranged in series, above-mentioned the first film transistor is positioned at an end, above-mentioned second thin-film transistor is positioned at the other end, and the drain region of above-mentioned second thin-film transistor comprises the drain electrode contact site.
In one embodiment, above-mentioned semiconductor layer has second getter area adjacent with the drain region of above-mentioned second thin-film transistor.
In one embodiment, above-mentioned the second end has the width bigger than above-mentioned central portion, be provided with a part and above-mentioned second getter area of the drain region of above-mentioned second thin-film transistor that comprises above-mentioned drain electrode contact site at above-mentioned the second end, above-mentioned second getter area is positioned at the outer peripheral portion of the above-mentioned the second end except the path of the electric charge from the above-mentioned channel region of above-mentioned second thin-film transistor to above-mentioned drain electrode contact site, and making the length on the straight line of the channel region that the line segment that connects the channel region of above-mentioned second thin-film transistor and above-mentioned second getter area with beeline is projected in be connected above-mentioned second thin-film transistor and above-mentioned drain electrode contact site is d
4, making the length from the above-mentioned channel region of above-mentioned second thin-film transistor to above-mentioned drain electrode contact site of above-mentioned semiconductor layer is d
5, making the length from the above-mentioned channel region of above-mentioned second thin-film transistor to above-mentioned the second end of above-mentioned semiconductor layer is d
6, order is L along the length of the above-mentioned the second end of the straight line of channel region that connects above-mentioned second thin-film transistor and above-mentioned drain electrode contact site
2, order is A along the length of the above-mentioned drain electrode contact site of the straight line of channel region that connects above-mentioned second thin-film transistor and above-mentioned drain electrode contact site
2, then satisfy d
5＞d
4〉=d
6And d
5+ A
2/ 2＞d
6+ L
2/ 2.
In one embodiment, d
4And d
5Satisfy 3 μ m≤d
4≤ 13 μ m, 8 μ m≤d
5≤ 30 μ m.
In one embodiment, be provided with the part of drain region of the part of the transistorized source region of above-mentioned the first film and drain region, above-mentioned second thin-film transistor and the channel region of source region and above-mentioned the first film transistor and above-mentioned second thin-film transistor at above-mentioned central portion.
In one embodiment, also have the adjacent source bus adjacent with above-mentioned source bus line, making grid bus corresponding with the channel region of above-mentioned second thin-film transistor and the distance between the above-mentioned adjacent source bus is C, then satisfies d
5＜C-A
2
In one embodiment, above-mentioned the first film transistor drain zone comprises the drain electrode contact site, and above-mentioned semiconductor layer has and the second adjacent getter area of above-mentioned the first film transistor drain zone.
In one embodiment, be provided with a part and above-mentioned second getter area in the above-mentioned the first film transistor drain zone that comprises above-mentioned drain electrode contact site at above-mentioned the second end, be provided with a part and the getter area of transistorized source region of above-mentioned the first film and drain region at above-mentioned central portion.
Adopt the present invention, can provide a kind of turn-off current that can suppress TFT sudden increase and can the suppressor grid bus and source bus line between the active-matrix substrate of generation of leakage.
Description of drawings
Fig. 1 is the figure of structure of first execution mode of expression active-matrix substrate of the present invention, (a) is schematic plane graph, (b) is the first end of semiconductor layer and near enlarged drawing thereof, (c) is the schematic sectional view along the A-A ' line of (a).
Fig. 2 is the first end of the semiconductor layer in the active-matrix substrate of comparative example 1 and near enlarged drawing thereof.
Fig. 3 is expression d
1, d
2And the chart of the relation between the bad incidence.
Fig. 4 (a)～(h) is respectively the schematic diagram of each operation of manufacture method of the active-matrix substrate of expression first execution mode.
Fig. 5 is illustrated in the manufacture method of active-matrix substrate of first execution mode shape of the Etching mask that uses and the schematic diagram of configuration in the doping operation of gettering element.
Fig. 6 is illustrated in the manufacture method of active-matrix substrate of first execution mode shape of the Etching mask of other that uses and the schematic diagram of configuration in the doping operation of gettering element.
Fig. 7 is the figure of structure of second execution mode of expression active-matrix substrate of the present invention, (a) is schematic plane graph, (b) is the first end of semiconductor layer and near enlarged drawing thereof.
Fig. 8 is the first end of the semiconductor layer in the active-matrix substrate of comparative example 2 and near enlarged drawing thereof.
Fig. 9 is illustrated in the manufacture method of active-matrix substrate of second execution mode shape of the Etching mask that uses and the schematic diagram of configuration in the doping operation of gettering element.
Figure 10 is illustrated in the manufacture method of active-matrix substrate of second execution mode shape of the Etching mask of other that uses and the schematic diagram of configuration in the doping operation of gettering element.
Figure 11 is the schematic plane graph of variation of second execution mode of expression active-matrix substrate of the present invention.
Figure 12 is other the schematic plane graph of variation of second execution mode of expression active-matrix substrate of the present invention.
Figure 13 is the schematic plane graph of expression existing semiconductor devices.The explanation of symbol
100 active-matrix substrates
110 semiconductor layers
112,114 getter areas
The 120TFT element
130、140、150TFT
132,142,152 source regions
132c source electrode contact site
134,144,154 channel regions
136,146,156 drain regions
136c, the 146c contact site that drains
160 grid buss
162,164,166 gate electrodes
170 source bus line
172 source electrodes
180 pixel electrodes
182 drain electrodes
Embodiment
Below, with reference to the execution mode of description of drawings active-matrix substrate of the present invention.And the present invention is not limited in following execution mode.
(execution mode 1)
At first, first execution mode to active-matrix substrate of the present invention describes.
In Fig. 1, the schematic diagram of the active-matrix substrate 100 of expression present embodiment.Fig. 1 (a) is the schematic plane graph of active-matrix substrate 100, and Fig. 1 (b) is the first end 110a of the semiconductor layer 110 in the active-matrix substrate 100 and near enlarged drawing thereof, and Fig. 1 (c) is the schematic sectional view along A-A ' line of Fig. 1 (a).
Active-matrix substrate 100 has: semiconductor layer 110, have as pixel with the first film transistor 130 of TFT and thin-film transistor element (hereinafter referred to as the TFT element) 120, grid bus 160, source bus line 170 and the pixel electrode 180 of second thin-film transistor 140.In addition, auxiliary capacitance line 190 is provided with abreast with grid bus 160.The TFT130 of TFT element 120,140 all has the LDD structure.In addition, TFT130,140 arranged in series, thus, the turn-off current of TFT element 120 is suppressed.
The source region 132 of TFT130, channel region 134 and drain region 136, and the source region 142 of TFT140, channel region 144 and drain region 146 are arranged on the semiconductor layer 110.The source region 132 of TFT130 has the source electrode contact site 132c that joins with source electrode 172, and wherein, source electrode 172 is electrically connected with source bus line 170; The drain region 146 of TFT140 has the grid contact site 146c that joins with drain electrode 182, and wherein, drain electrode 182 is electrically connected with pixel electrode 180.In addition, the source region 142 of the drain region 136 of TFT130 and TFT140 is continuous.
Herein, the length on the straight line of the order channel region 134 that the line segment that connects the channel region 134 of TFT130 and getter area 112 with beeline is projected in be connected TFT130 and source electrode contact site 132c is d
1, making the length from the channel region 134 of TFT130 to source electrode contact site 132c of semiconductor layer 110 is d
2Wherein, d
2Be equivalent to the grid bus on the channel region 134 160 and and the source electrode 172 that joins of source electrode contact site 132c between distance.Source electrode contact site 132c is arranged on the position that the limit with channel region 134 1 sides of first end 110a separates, d
2Compare d
1Greatly.
In addition, making the length from the channel region 134 of TFT130 to first end 110a of semiconductor layer 110 is d
3Herein, first getter area 112 is provided with d in the mode that the limit with channel region 134 1 sides of first end 110a joins
3With d
1Equate.In addition, order is L along the length of the first end 110a of the straight line of channel region 134 that connects TFT130 and source electrode contact site 132c
1, order is A along the length of the source electrode contact site 132c of the straight line of channel region 134 that connects TFT130 and source electrode contact site 132c
1
The application's inventor finds, if reduce d for the sudden increase of the turn-off current that suppresses TFT
1, d then
2Also diminish thereupon, consequently, can increase the generation of the leakage between grid bus and the source bus line.So the active-matrix substrate 100 of present embodiment is provided with and makes d
2The source electrode contact site 132c that increases, thus, the sudden increase of the turn-off current of inhibition TFT130 and the generation of the leakage between suppressor grid bus 160 and the source bus line 170.
Below, compare with the active-matrix substrate 500 of comparative example 1, the advantage of the active-matrix substrate 100 of present embodiment is described.In Fig. 2, the first end 510a of the semiconductor layer 510 in the active-matrix substrate 500 of expression comparative example 1 and near schematic plane graph thereof.The active-matrix substrate 500 of comparative example 1 is except d
2And L
1In addition, have the structure identical with active-matrix substrate shown in Figure 1 100.
The same with active-matrix substrate 100, in the active-matrix substrate 500 of comparative example 1, the length on channel region 534 that order is projected in the line segment that connects the channel region 534 of TFT530 and getter area 512 with beeline to be connected TFT530 and the straight line of source electrode contact site 532c is d
1, making the length from the channel region 534 of TFT530 to source electrode contact site 532c of semiconductor layer 510 is d
2In addition, order is L along the length of the first end 510a of the straight line of channel region 534 that connects TFT530 and source electrode contact site 532c
1, order is A along the length of the source electrode contact site 532c of the straight line of channel region 534 that connects TFT530 and source electrode contact site 532c
1
In the active-matrix substrate 500 of comparative example 1, with the length L of first end 510a
1Reduce.Thus, can reduce the amount of the foreign matter of sneaking into first end 510a.For example, L
1Be 6 μ m.
On the other hand, for first end 510a and the source electrode 572 that makes semiconductor layer 510 is electrically connected reliably, make the length A of source electrode contact site 532c
1Bigger.In addition, thus, it is big that the sectional area of source electrode 572 becomes, and resistance reduces.For example, A
1Be 4 μ m.In addition, consider the dislocation that pattern forms, design in the mode that source electrode contact site 532c is configured in the center of first end 510a.In addition, the width of the first end 510a around the source electrode contact site 532c is 1.0 μ m, and this is the surplus of source electrode contact site 532c.Consider dislocation, etching skew that pattern forms, guarantee the surplus of 1.0 μ m.In addition, the width of getter area 512 is 1.0 μ m.In addition, it is not overlapping with source electrode contact site 532c to it is desirable to first getter area 512, makes source electrode contact site resistance can deviation not take place because of the deviation of gettering concentration of element.
In addition, in the active-matrix substrate 500 of comparative example 1, reduce d
1, shorten the distance between the channel region 534 and first getter area 512.Reduce d like this
1, then the catalyst elements in the channel region 534 can be passed through getter area 512 gettering fully, thereby can suppress the sudden increase of the turn-off current of TFT530.For example, d
1Be 5 μ m.
But, in active-matrix substrate 500, because reduce L
1And make A
1Bigger, so d
2Also along with d
1Diminish, the distance between grid bus 560 and the source electrode 572 is short.For example, as mentioned above, at L
1Be 6 μ m, A
1Be 4 μ m, d
1Be under the situation of 5 μ m, d
2Be 6 μ m.Therefore, in the active-matrix substrate 500 of comparative example 1, if form by pattern (pattering) when forming grid bus 560 conductive material remain in around it, then exist by residual conductive material and source electrode 572, between grid bus 560 and source bus line 570, produce and leak, produce the situation of line defect.
To this, from the channel region 134 of the TFT130 of active-matrix substrate 100, source electrode contact site 132c is centered close to the position far away than the center of first end 110a.Therefore, little d can kept
1The time increase d
2, with the distance lengthening between grid bus 160 and the source bus line 170, thus can suppressor grid bus 160 and source bus line 170 between the generation of leakage.
In addition, active-matrix substrate 100 is being kept little d because constitute
1The time increase d
2So, d
2And d
1Difference with respect to L
1Become bigger.Particularly, active-matrix substrate 100 satisfies d
2-d
1＞L
1/ 6.For example, the L of active-matrix substrate 100
1Be 9 μ m, A
1Be 4 μ m, d
1Be 5 μ m, d
2Be 9 μ m.In addition, though the distance between the source electrode contact site 132c and first getter area 112 is 0 μ m ideally, also can be 0.5 μ m～1.0 μ m.
In addition, L
1To A
1Ratio big, satisfy L
1＞1.5 * A
1Thus, can improve the degree of freedom with respect to the design of the source electrode contact site 132c of first end 110a.
In addition, be B if make the main part 160a of grid bus 160 and the distance between the auxiliary capacitance line 190, then the active-matrix substrate 100 of present embodiment satisfies B 〉=2d
2+ A
1Thus, 172 distance also becomes and compares d from auxiliary capacitance line 190 to source electrode
2Long, not only can suppress the leakage between source electrode 172 and the grid bus 160, can also suppress the generation of the leakage between source electrode 172 and the auxiliary capacitance line 190.For example, the A of active-matrix substrate 100
1Be that 4 μ m, B are 64 μ m.
In addition, shown in Fig. 1 (a), in semiconductor layer 110, if will be called width with respect to the direction of the mobile quadrature of electric charge from source electrode contact site 132c to the contact site 146c that drains, then the width of first end 110a (promptly, length along the x direction of first end 110a) and the width of the second end 110b length of the y direction of the second end 110b (that is, along) be respectively 8.5 μ m.In addition, central portion 110c is that its width is 3 μ m along the L word shape of x direction and the extension of y direction.Like this, the width of first end 110a, the second end 110b is also bigger than the width of central portion 110c.Owing to the width of the central portion 110c that comprises channel region 134,144 is little, so can suppress the turn-off current of TFT120.
In addition, the x direction of source electrode contact site 132c, the length of y direction are respectively 4 μ m, and the x direction of drain electrode contact site 146c, the length of y direction are respectively 4 μ m.In addition, the width of first, second getter area 112,114 that is arranged on the outer peripheral portion of first, second end 110a, 110b is 1.0 μ m.
Like this, active-matrix substrate 100 can be with d
1Be maintained with the active-matrix substrate 500 of comparative example 1 similarly for a short time, and can make d
2Active-matrix substrate 500 than comparative example 1 is longer.Thus, active-matrix substrate 100 can suppress the sudden increase of the turn-off current among the TFT130 and can prevent the generation of the leakage between grid bus 160 and the source bus line 170, thereby can suppress the point defect in the display unit and the generation of line defect.
The d of the active-matrix substrate 100 of present embodiment
1Scope for example be 3 μ m≤d
1≤ 13 μ m.Work as d
1During greater than 13 μ m, even getter area 112 is set, the concentration gradient of catalyst elements diminishes, also can the residual catalyst element in channel region, and the turn-off current of TFT increases easily abruptly.Therefore, make the d of active-matrix substrate 100
1Be below the 13 μ m.In addition, TFT130 has the LDD structure, though be provided with low concentration impurity zone (not shown) between channel region 134 and getter area 112, works as d
1During less than 3 μ m, the low concentration impurity zone can't be set suitably.Therefore, make the d of active-matrix substrate 100
1Be more than the 3 μ m.In addition, three limits and the distance between first getter area 112 of rectangular-shaped source electrode contact site 132c are all less and fixing, can realize high gettering performance thus.
In addition, d
2Scope be 8 μ m≤d
2≤ 30 μ m.Work as d
2During less than 8 μ m, be easy to generate leakage between grid bus 160 and the source bus line 170.Therefore, make the d of active-matrix substrate 100
2Be more than the 8 μ m.In addition, between grid bus 160 and auxiliary capacitance line 190 is under the situation of 64 μ m apart from B, works as d
2During greater than 30 μ m, the distance between auxiliary capacitance line 190 and the source electrode 172 shortens, and exists in and produces the problem of leaking between auxiliary capacitance line 190 and the source electrode 172.Therefore, make the d of active-matrix substrate 100
2Be below the 30 μ m.In addition, d
1And d
2Can utilize light microscope determining.
In addition, the semiconductor layer 110 in the active-matrix substrate 100 forms linearity from channel region 134 to source electrode contact site 132c in the mode parallel with source bus line 170.Thus, can suitably dwindle d
1And increase d
2Thereby, can inhibition point defective and line defect.In addition, channel region 134 is covered by source bus line 170, and the light shielding part that needn't be provided for covering channel region 134 in addition just can suppress misoperation.
In addition, in the above description, the L of active-matrix substrate 100
1, A
1Satisfy L
1＞1.5 * A
1, improved the degree of freedom of the configuration of source electrode contact site 132c thus, consider design error etc., further preferably satisfy L
1＞2 * A
1
Fig. 3 is expression d
1Relation and d with bad generation rate
2Chart with the relation of bad generation rate.In Fig. 3, solid line is represented d
1With the relation of bad generation rate, dotted line is represented d
2Relation with bad generation rate.Herein, about d
1Bad be to result from the point defect of turn-off current, in addition, about d
2Bad be line defect.The display unit decision-point defective and the line defect that have active-matrix substrate by directly detecting by an unaided eye.
Can understand d from Fig. 3
1Big more, then the point defect generation rate is high more.This be because, d
1Big more, then the gettering of catalyst elements becomes insufficient more, meeting residual a large amount of catalyst elements in channel region.As shown in Figure 3, by making d
1Be below the 13 μ m, can make the point defect generation rate be roughly 0%.Therefore, preferably make d
1Be below the 13 μ m.But, strict in fact, even with d
1Be designed under the situation of 13 μ m actual d
1Also there is deviation, can produces point defect.
In addition, d
2More little, be easy to generate the leakage between grid bus and the source bus line more, thereby be easy to generate line defect more.As shown in Figure 3, about below 3% for the line defect generation rate is suppressed at, be necessary to make d
2Be more than the 8 μ m.Above-mentioned active-matrix substrate 100 constitutes with d
1Be maintained d under the less state
2Become big, thus, can carry out gettering, suppress the sudden increase of turn-off current the catalyst elements that remain in the channel region 134, and can suppressor grid bus 160 and source bus line 170 between the generation of leakage.
In addition, in the above description, carry out the judgement of point defect and line defect by Direct observation display unit with the naked eye, but the present invention is not limited to this.Can also reduce the ND of (for example, make through light and be reduced to 10%) through light (Neutral Density: neutral density) filter is with the naked eye observed, according to bad number, brightness decision-point defective and line defect by making.
In addition, in Fig. 1, the viewing area of expression active-matrix substrate 100, active-matrix substrate is that driver is one-piece type, can also form gate drivers, the drain driver that possesses TFT in the neighboring area.In addition, the semiconductor layer that is used for the TFT (drive circuit TFT) of this driver also can be the same with the viewing area, utilizes the CGS method to make.For example, at drive circuit with among the TFT, in the semiconductor layer from the gate electrode overlapping areas to the length of first end (that is, with d
1Corresponding length) be 1～3 μ m, from the gate electrode overlapping areas to the length of grid contact site (that is, with d
2Corresponding length) be 1.5～3.5 μ m.Like this, the drive circuit d of TFT
1And d
2Shorter than pixel respectively with TFT.
In addition, in the above description, the width of getter area 112,114 is 1.0 μ m, but fully take into account dislocation, etching skew that pattern forms, the width of preferred getter area 112,114 is further greater than 1 μ m, and for example, the width of preferred getter area 112,114 is 1.75 μ m.In addition, in this case, can also be the length d from channel region 134 to first end 110a of semiconductor layer 110
1Be 5 μ m, along the length L of the first end 110a of y direction
1Be 11.75 μ m, wherein, from the limit of channel region 134 1 sides of first end 110a to length (that is d, of source electrode contact site 132c
2And d
1Poor) be 5.5 μ m, the length with limits channel region 134 opposite sides from source electrode contact site 132c to first end 110a is 2.25 μ m.Source electrode contact site 132c compares the limit of more approaching a side opposite with channel region 134 at first end 110a and is provided with the limit of channel region 134 sides.In addition, L
1To A
1The following 1.5 μ m that are limited to of ratio, its upper limit for example is (B-d
3)/A
1This is because L
1Maximum be B-d
3More than such active-matrix substrate 100 be used for for example liquid crystal indicator.
Below, with reference to Fig. 4, the manufacture method of the active-matrix substrate 100 of present embodiment is described.In addition, Fig. 4 (a)～Fig. 4 (h) is corresponding with the cross section of Fig. 1 (b).
At first, shown in Fig. 4 (a), prepare insulated substrate 192.Insulated substrate 192 for example is a glass substrate.
Then, shown in Fig. 4 (b), on insulated substrate 192, form bottom coating (not shown), on bottom coating, form semiconductor layer 110.Herein, semiconductor layer is an amorphous semiconductor.
Then, shown in Fig. 4 (c), add catalyst elements to semiconductor layer 110.Catalyst elements for example is a nickel.The interpolation of nickel for example makes its dry carrying out by nickel acetate soluble in water is layered on equably on the semiconductor layer 110.Then, by heating, make semiconductor layer 110 crystallizations.Thus, semiconductor layer 110 becomes crystalline semiconductor layer.Then, form, form end 110a, 110b and the central portion 110c of the semiconductor layer 110 shown in Fig. 1 (a) by semiconductor layer 110 being carried out pattern.
Then, shown in Fig. 4 (d), on semiconductor layer 110, form gate insulating film 194.Then, after piling up conductive material on the gate insulating film 194, form, form grid bus 160 by pattern.
Then, shown in Fig. 4 (e), utilize grid bus 160, in semiconductor layer 110, import impurity as mask.Thus, the source region 142 of the source region 132 of the TFT130 shown in Fig. 1 in semiconductor layer 110 (a), drain region 136 and TFT140, drain region 146 import impurity.Making under the situation of N channel-type TFT element as TFT element 120, impurity for example is phosphorus.In addition, making under the situation of P channel-type TFT element as TFT element 120, impurity for example is boron.Impurity concentrations in TFT130,140 source region 132,142 and the drain region 136,146 for example are 2～3 * 10
20Atoms/cm
3In addition, the impurity concentration in low concentration impurity zone (not shown) is about its 1/600 times.
Then, shown in Fig. 4 (f), after forming the Etching mask 310 of peristome on the semiconductor layer 110, at the regulation region doping gettering element of end 110a, the 110b shown in Fig. 1 (a) with regulation.The gettering element for example is a phosphorus.By this doping, form getter area 112,114 at end 110a, 110b.The concentration of the gettering element in the getter area 112,114 for example is 6 * 10
20～1 * 10
21Atoms/cm
3
Then, by heating semiconductor layer 110, carry out gettering and handle.Catalyst elements in source region 132 shown in Fig. 1 (a), channel region 134 and the drain region 136, mainly by gettering at getter area 112, catalyst elements in the source region 142 of TFT140, channel region 144 and the drain region 146, mainly by gettering at getter area 114.
Then, shown in Fig. 4 (g), after peeling off Etching mask 310, form interlayer dielectric 196, and carry out etching, thus, the source electrode contact site 132c of the semiconductor layer 110 shown in Fig. 1 (a) and drain electrode contact site 146c expose.
Then, shown in Fig. 4 (h), after piling up conductive material, form, form source electrode 172 and source bus line 170 by pattern.At this moment, the part of drain electrode 182 (with reference to Fig. 1 (a)) also is formed.Then, film between cambium layer (not shown), and on it, form the remainder and the pixel electrode 180 of the drain electrode 182 shown in Fig. 1 (a).Active-matrix substrate 100 is made as described above.
In addition, as mentioned above, utilize Etching mask to carry out the doping of gettering element, if still use a large amount of anticorrosive additive materials in order to form Etching mask, the amount that then remains in the anticorrosive additive material of semiconductor layer 110 grades after peeling off Etching mask also increases, and can bring bad influence.In addition, in using the doping operation of Etching mask, because the amount of the gas that produces from the surface of Etching mask increases, so the deterioration in accuracy of mixing.Therefore, so that the purpose that the use amount of anticorrosive additive material reduces also can form Etching mask according to the mode in the zone that does not cover no semiconductor layer 110.
For example, as shown in Figure 5, can also form Etching mask 310, this Etching mask 310 not only is provided with the peristome 310a corresponding to getter area 112, and be provided with peristome 310b, this peristome 310b and peristome 310a are continuous, corresponding to getter area 112 adjacent areas.In addition, in Fig. 5, in order to make the structure under the Etching mask 310 clear and definite, encirclement represents that as peristome 310a, the 310b of the Etching mask 310 in the zone that imports the gettering element perspective representation covers the Etching mask 310 and the gate insulating film 194 of semiconductor layer 110.
But, under the situation of using Etching mask 310 shown in Figure 5, because corresponding to the peristome 310a of getter area 112 with corresponding to continuous with the peristome 310b of getter area 112 adjacent areas, therefore, when doping gettering element, in the active-matrix substrate 100 that finally is made into, exist by source electrode 172 to produce the situation of the leakage between grid bus 160 and the source bus line 170.
So, as shown in Figure 6, if use the Etching mask 320 that separates with peristome 320b corresponding to the peristome 320a of getter area 112 as Etching mask corresponding to its near zone, the use amount that then can suppress anticorrosive additive material, and can suppress to suppress the generation of the line defect in the display unit thus by the leakage between source electrode 172 generation grid buss 160 and the source bus line 170.
In addition, because remain in the active-matrix substrate 100 by the gettering element behind the peristome of Etching mask, so, can determine the shape of the peristome of the Etching mask that when doping gettering element, uses by using sweep type electric capacity microscope (Scanning CapacitanceMicroscope:SCM) to detect the doping of gettering element.Perhaps, because carry out become regional thin than other of gate insulating film 194 after the doping of gettering element, so, can determine the shape of the peristome of the Etching mask that when doping gettering element, uses by using scanning electron microscope (Scanning Electron Microscope:SEM) to carry out the panel cross-section.
In addition, in the above description, to the length d that is associated with source region 132
1, d
2, d
3, L
1, A
1Be illustrated, but the present invention is not limited to this.It is d that order connects the length that the line segment of the channel region 144 of TFT140 and second getter area 114 is projected on the straight line (that is the straight line along the x direction among Fig. 1 (a)) that is connected channel region 144 and drains contact site 146c with beeline
4, making the length from channel region 144 to drain electrode contact site 146c of semiconductor layer 110 is d
5, the length from the channel region 144 of TFT140 to the second end 110b of semiconductor layer 110 is d
6In addition, order is A along the length of the drain electrode contact site 146c of the straight line of channel region 144 that connects TFT140 and drain electrode contact site 146c
2, order is L along the length of the second end 110b of the straight line of channel region 144 that connects TFT140 and drain electrode contact site 146c
2Active-matrix substrate 100 satisfies d
5+ A
2/ 2＞d
6+ L
2/ 2, thus, can suppress the generation of the paroxysmal increase of turn-off current and the leakage between grid bus 160 and pixel electrode 180 by drain electrode 182.In addition, d
4And d
5Satisfy 3 μ m≤d
4≤ 13 μ m, 8 μ m≤d
5≤ 30 μ m.In addition, be C if make the channel region 144 of TFT140 and the distance between the adjacent source bus 170c adjacent with source bus line 170, then satisfy d
5＜C-A
2, thus, and adjacent source bus 170c between drain electrode 182 can be set.
In addition, in the structure shown in Fig. 1 (a), the branching portion 160b of grid bus 160 and the distance between the drain electrode 182 are than the main part 160a of grid bus 160 and the distance between the drain electrode 182, but, because the amount of the conductive material around remaining in when forming branching portion 160b by pattern is more than main part 160a, so by increasing d
5, can suppress generation by the leakage between grid bus 160 and pixel electrode 180 of drain electrode 182.
In addition, in the above description, with the adjacent respectively getter area 112,114 that is provided with in source region 132 and drain region 146, but the present invention is not limited to this.Being provided with getter area 112 gets final product.This be because, if produce leakage between grid bus and the source bus line, then in display unit, produce line defect, big to the influence of the rate of finished products of display unit.
In addition, in the above description, getter area 112,114 is provided with d in the mode that the limit with channel region 134,144 1 sides of rectangular-shaped end 110a, 110b joins separately
1, d
4Respectively with semiconductor layer 110 (be d from TFT130,140 channel region 134,144 length to end 110a, 110b
3, d
6) equate, but the present invention is not limited to this.Can also getter area 112,114 do not join d with the limit of channel region 134,144 1 sides of end 110a, 110b separately
1, d
4Respectively than d
3, d
6Long.
(execution mode 2)
The TFT element of the active-matrix substrate of above-mentioned execution mode 1 has two TFT, but active-matrix substrate of the present invention is not limited in this.The TFT element of active-matrix substrate can also have three TFT.
The schematic diagram of second execution mode of expression active-matrix substrate of the present invention in Fig. 7.Fig. 7 (a) is the schematic plane graph of the active-matrix substrate 100 of present embodiment, (b) is the first end 110a of the semiconductor layer 110 in the active-matrix substrate 100 and near enlarged drawing thereof.
The active-matrix substrate 100 of present embodiment has three TFT (promptly except TFT120, the first film transistor 130, second thin-film transistor 140 and the 3rd thin-film transistor 150) beyond this point, have the structure identical with the active-matrix substrate of execution mode shown in Figure 11, tediously long for fear of article, the repetitive description thereof will be omitted.In addition, three TFT130 of TFT element 120,140,150 arranged in series, TFT130 is positioned at an end, and TFT140 is positioned at the other end.Therefore, the TFT130 of TFT element 120,140,150 presses the order of TFT130, TFT150, TFT140 from the direction arrangement of source electrode contact site 132c to drain electrode contact site 146c.
Herein, to connect the length that the line segment of the channel region 134 of TFT130 and first getter area 112 is projected on the straight line that is connected channel region 134 and source electrode contact site 132c with beeline be d in order
1, making the length from channel region 134 to source electrode contact site 132c of semiconductor layer 110 is d
2, order is L along the length of the first end 110a of the straight line of channel region 134 that connects TFT130 and source electrode contact site 132c
1The active-matrix substrate 100 of present embodiment constitutes with the active-matrix substrate of above-mentioned execution mode 1 the samely and satisfies d
2+ A
1/ 2＞d
3+ L
1/ 2.In addition, the active-matrix substrate 100 of present embodiment satisfies d
2-d
1＞L
1/ 6 relation and L
1＞1.5 * A
1
In addition, in the active-matrix substrate 100 of present embodiment also as illustrated with reference to Fig. 3, be roughly 0% in order to make the bad generation rate of point defect, make d
1Be below the 13 μ m.For example be 3 μ m≤d
1≤ 13 μ m, 8 μ m≤d
2≤ 30 μ m.
Below, compare with the active-matrix substrate 600 of comparative example 2, the advantage of the active-matrix substrate 100 of present embodiment is described.In Fig. 8, the first end 610a of the semiconductor layer 610 in the active-matrix substrate 600 of expression comparative example 2 and near enlarged drawing thereof.Except d
2And L
1Beyond the different this point, the active-matrix substrate 600 of comparative example 2 has the structure identical with active-matrix substrate shown in Figure 7 100.
The same with active-matrix substrate 100, in the active-matrix substrate 600 of comparative example 2, the length on channel region 634 that order is projected in the line segment that connects the channel region 634 of TFT630 and getter area 612 with beeline to be connected TFT630 and the straight line of source electrode contact site 632c is d
1, making the length from the channel region 634 of TFT630 to source electrode contact site 632c of semiconductor layer 610 is d
2In addition, order is L along the length of the first end 610a of the straight line of channel region 634 that connects TFT630 and source electrode contact site 632c
1, order is A along the length of the source electrode contact site 632c of the straight line of channel region 634 that connects TFT630 and source electrode contact site 632c
1
In the active-matrix substrate 600 of comparative example 2, make the length L of first end 610a
1Reduce.The amount of the impurity element of sneaking into first end 610a is reduced, in addition, also suppress the first end 610a of semiconductor layer 610 and the parasitic capacitance between the source bus line 670.For example, L
1Be 6 μ m.On the other hand, reliable for the electrical connection of the first end 610a that makes semiconductor layer 610 and source electrode 672, make the length A of source electrode contact site 632c
1Bigger.In addition, thus, it is big that the sectional area of source electrode 672 becomes, and resistance reduces.For example, A
1Be 4 μ m.In addition, consider the dislocation that pattern forms, design in the mode that source electrode contact site 632c is configured in the center of first end 610a.In addition, the width of the first end 610a around the source electrode contact site 632c is 1.0 μ m, and this is the surplus of source electrode contact site 632c.Consider dislocation, etching skew that pattern forms, guarantee the surplus of 1.0 μ m.In addition, the width of getter area 612 is 1.0 μ m.
In addition, in the active-matrix substrate 600 of comparative example 2, reduce d
1, shorten the distance between the channel region 634 and first getter area 612.Reduce d like this
1, the catalyst elements in the channel region 634 can be passed through getter area 612 gettering fully, thereby can suppress the sudden increase of the turn-off current among the TFT630.For example, d
1Be 5 μ m.
But, in active-matrix substrate 600, because reduce L
1And military order A
1Bigger, so d
2Also along with d
1Diminish, the distance between grid bus 660 and the source electrode 672 is short.For example, as mentioned above, at L
1Be 6 μ m, A
1Be 4 μ m, d
1Be under the situation of 5 μ m, d
2Be 6 μ m.Therefore, in the active-matrix substrate 600 of comparative example 2, if conductive material remains in around it when forming grid bus 660 by pattern, then by residual conductive material and gate electrode 672, produce the leakage between grid bus 660 and the source bus line 670, thereby produce line defect.
To this, from the channel region 134 of the TFT130 of active-matrix substrate 100, source electrode contact site 132c is centered close to the position far away than the center of first end 110a.Therefore, even at the d of the active-matrix substrate 100 that makes present embodiment
1Under situation that the active-matrix substrate 600 of comparative example 2 is kept lessly the samely, also can make the d of active-matrix substrate 100
2Length than the active-matrix substrate 600 of comparative example 2.Therefore, active-matrix substrate 100 can suppress the paroxysmal increase of the turn-off current among the TFT130 and prevent grid bus 160 and source bus line 170 between the generation of leakage, thereby can suppress the point defect in the display unit and the generation of line defect.
In addition, the identical manufacture method of active-matrix substrate of the execution mode 1 that illustrated according to reference Fig. 4 of the active-matrix substrate 100 of present embodiment is made.Therefore, in the manufacture method of active-matrix substrate 100, when doping gettering element, also can be as shown in Figure 9, use have peristome 310a and with the Etching mask 310 of the continuous peristome 310b of peristome 310a.But, as mentioned above, because corresponding to the peristome 310a of getter area 112 with corresponding to continuous with the peristome 310b of getter area 112 adjacent areas, then in the final active-matrix substrate of making 100, exist by source electrode 172 to produce the situation of the leakage between grid bus 160 and the source bus line 170.So, as shown in figure 10, by using the Etching mask 320 that separates with peristome 320b corresponding to the peristome 320a of getter area 112, can suppress generation by the leakage between grid bus 160 and source bus line 170 of source electrode 172 corresponding to its near zone.
In addition, in active-matrix substrate shown in Figure 7 100, grid bus 160 has main part 160a and two branching portion 160b, 160c, but the present invention is not limited to this.As shown in figure 11, grid bus 160 can also not have branching portion 160b, and is made of main part 160a and branching portion 160c.
In addition, the TFT element 120 of above-mentioned active-matrix substrate has a plurality of TFT, but the present invention is not limited to this.As shown in figure 12, the TFT element 120 in the active-matrix substrate 100 also can only be made of a TFT130.
In addition, in the above description, the display unit as using active-matrix substrate illustrates liquid crystal indicator, but the present invention is not limited to this.Using the display unit of active-matrix substrate can also be display unit arbitrarily such as CRT, plasma (PDP), organic EL, SED, liquid crystal projection apparatus.
In addition, as a reference, quoted Japanese patent application 2007-69140 number disclosure in this specification as the application's basis application.
Utilizability on the industry
Active-matrix substrate of the present invention can suitably be applied to display, television set, the projecting apparatus such as personal computer, display unit of portable phone etc.
Claims (14)
1. active-matrix substrate, it comprises:
Semiconductor layer;
Thin-film transistor element, it comprises the first film transistor, described the first film transistor has source region, channel region and the drain region that is arranged at described semiconductor layer;
Grid bus;
Source bus line; With
Pixel electrode, this active-matrix substrate is characterised in that:
The transistorized source region of described the first film comprises the source electrode contact site,
Described semiconductor layer has first getter area adjacent with the transistorized source region of described the first film,
Described semiconductor layer comprises first end, the second end and the central portion between described first end and described the second end,
Described first end has the width bigger than described central portion,
Be provided with a part and described first getter area of the transistorized source region of described the first film that comprises described source electrode contact site at described first end,
Described first getter area is positioned at the outer peripheral portion of the described first end except the path of the electric charge from described source electrode contact site to the transistorized described channel region of described the first film,
Order makes that to connect the length that the line segment of transistorized channel region of described the first film and described first getter area is projected on the straight line that is connected transistorized channel region of described the first film and described source electrode contact site with beeline be d
1, making the length from the transistorized channel region of described the first film to described source electrode contact site of described semiconductor layer is d
2, making the length from the transistorized described channel region of described the first film to described first end of described semiconductor layer is d
3, order is L along the length of the described first end of the straight line that connects transistorized channel region of described the first film and described source electrode contact site
1, order is A along the length of the described source electrode contact site of the straight line that connects transistorized channel region of described the first film and described source electrode contact site
1, then satisfy d
2＞d
1〉=d
3And d
2+ A
1/ 2＞d
3+ L
1/ 2,
At least a portion of described first end and described source bus line are overlapping.
2. active-matrix substrate as claimed in claim 1 is characterized in that:
Satisfy d
2-d
1＞L
1/ 6.
3. active-matrix substrate as claimed in claim 1 or 2 is characterized in that:
Satisfy L
1＞1.5 * A
1
4. active-matrix substrate as claimed in claim 1 or 2 is characterized in that:
d
1And d
2Satisfy
3μm≤d
1≤13μm，
8μm≤d
2≤30μm。
5. active-matrix substrate as claimed in claim 1 or 2 is characterized in that:
At least a portion of described central portion is to extend abreast with overlapping mode and the described source bus line of described source bus line.
6. active-matrix substrate as claimed in claim 1 or 2 is characterized in that:
Described active-matrix substrate also possesses auxiliary capacitance line,
The distance that makes described grid bus and described auxiliary capacitance line is B, then satisfies B 〉=2d
2+ A
1
7. active-matrix substrate as claimed in claim 1 or 2 is characterized in that:
Described thin-film transistor element also comprises second thin-film transistor, and described second thin-film transistor has source region, channel region and the drain region that is arranged at described semiconductor layer,
Described the first film transistor and the described second thin-film transistor arranged in series, described the first film transistor is positioned at an end, and described second thin-film transistor is positioned at the other end,
The drain region of described second thin-film transistor comprises the drain electrode contact site.
8. active-matrix substrate as claimed in claim 7 is characterized in that:
Described semiconductor layer has second getter area adjacent with the drain region of described second thin-film transistor.
9. active-matrix substrate as claimed in claim 8 is characterized in that:
Described the second end has the width bigger than described central portion,
Be provided with a part and described second getter area of the drain region of described second thin-film transistor that comprises described drain electrode contact site at described the second end,
Described second getter area is positioned at the outer peripheral portion of the described the second end except the path of the electric charge from the described channel region of described second thin-film transistor to described drain electrode contact site,
Length on the channel region that order is projected in the line segment that connects the channel region of described second thin-film transistor and described second getter area with beeline to be connected described second thin-film transistor and the straight line of described drain electrode contact site is d
4, making the length from the channel region of described second thin-film transistor to described drain electrode contact site of described semiconductor layer is d
5, making the length from the described channel region of described second thin-film transistor to described the second end of described semiconductor layer is d
6, order is L along the length of the described the second end of the straight line of channel region that connects described second thin-film transistor and described drain electrode contact site
2, order is A along the length of the described drain electrode contact site of the straight line of channel region that connects described second thin-film transistor and described drain electrode contact site
2, then satisfy d
5＞d
4〉=d
6And d
5+ A
2/ 2＞d
6+ L
2/ 2.
10. active-matrix substrate as claimed in claim 9 is characterized in that:
d
4And d
5Satisfy
3μm≤d
4≤13μm，
8μm≤d
5≤30μm。
11. active-matrix substrate as claimed in claim 7 is characterized in that:
Be provided with at described central portion: the channel region of the part of the drain region of the part of the transistorized source region of described the first film and drain region, described second thin-film transistor and source region and described the first film transistor and described second thin-film transistor.
12. active-matrix substrate as claimed in claim 11 is characterized in that:
Also possess the adjacent source bus adjacent with described source bus line, making grid bus corresponding with the channel region of described second thin-film transistor and the distance between the described adjacent source bus is C, then satisfies d
5＜C-A
2
13. active-matrix substrate as claimed in claim 1 or 2 is characterized in that:
Described the first film transistor drain zone comprises the drain electrode contact site,
Described semiconductor layer has and the second adjacent getter area of described the first film transistor drain zone.
14. active-matrix substrate as claimed in claim 13 is characterized in that:
Be provided with a part and described second getter area in the described the first film transistor drain zone that comprises described drain electrode contact site at described the second end,
Be provided with a part and the channel region of transistorized source region of described the first film and drain region at described central portion.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2007069140 | 2007-03-16 | ||
| JP069140/2007 | 2007-03-16 | ||
| PCT/JP2008/053689 WO2008114598A1 (en) | 2007-03-16 | 2008-02-29 | Active matrix substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101636828A CN101636828A (en) | 2010-01-27 |
| CN101636828B true CN101636828B (en) | 2011-09-21 |
Family
ID=39765708
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2008800085892A Expired - Fee Related CN101636828B (en) | 2007-03-16 | 2008-02-29 | Active matrix substrate |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US8860033B2 (en) |
| CN (1) | CN101636828B (en) |
| BR (1) | BRPI0808885A2 (en) |
| WO (1) | WO2008114598A1 (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003303831A (en) * | 2002-04-08 | 2003-10-24 | Sharp Corp | Semiconductor device and its manufacturing method |
| CN1453882A (en) * | 2002-04-24 | 2003-11-05 | 夏普公司 | Semiconductor device and producing method thereof |
| CN1506737A (en) * | 2002-12-09 | 2004-06-23 | Lg.飞利浦Lcd有限公司 | Method for producing array base plate with colour filter structure on thin film transistor for liquid crystal display device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100265179B1 (en) | 1995-03-27 | 2000-09-15 | 야마자끼 순페이 | Semiconductor device and manufacturing method thereof |
| TWI301907B (en) | 2000-04-03 | 2008-10-11 | Semiconductor Energy Lab | Semiconductor device, liquid crystal display device and manfacturing method thereof |
| JP4115283B2 (en) | 2003-01-07 | 2008-07-09 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
| JP4115441B2 (en) | 2004-10-29 | 2008-07-09 | シャープ株式会社 | Semiconductor device and manufacturing method thereof |
| JP4814371B2 (en) | 2007-03-16 | 2011-11-16 | シャープ株式会社 | Active matrix substrate |
-
2008
- 2008-02-29 CN CN2008800085892A patent/CN101636828B/en not_active Expired - Fee Related
- 2008-02-29 US US12/531,383 patent/US8860033B2/en not_active Expired - Fee Related
- 2008-02-29 BR BRPI0808885-3A patent/BRPI0808885A2/en not_active IP Right Cessation
- 2008-02-29 WO PCT/JP2008/053689 patent/WO2008114598A1/en active Application Filing
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003303831A (en) * | 2002-04-08 | 2003-10-24 | Sharp Corp | Semiconductor device and its manufacturing method |
| CN1453882A (en) * | 2002-04-24 | 2003-11-05 | 夏普公司 | Semiconductor device and producing method thereof |
| CN1506737A (en) * | 2002-12-09 | 2004-06-23 | Lg.飞利浦Lcd有限公司 | Method for producing array base plate with colour filter structure on thin film transistor for liquid crystal display device |
Also Published As
| Publication number | Publication date |
|---|---|
| US8860033B2 (en) | 2014-10-14 |
| CN101636828A (en) | 2010-01-27 |
| US20100096639A1 (en) | 2010-04-22 |
| BRPI0808885A2 (en) | 2014-08-26 |
| WO2008114598A1 (en) | 2008-09-25 |
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