CN101621248B - DC to DC converting circuit and controller thereof - Google Patents
DC to DC converting circuit and controller thereof Download PDFInfo
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- CN101621248B CN101621248B CN2008101276526A CN200810127652A CN101621248B CN 101621248 B CN101621248 B CN 101621248B CN 2008101276526 A CN2008101276526 A CN 2008101276526A CN 200810127652 A CN200810127652 A CN 200810127652A CN 101621248 B CN101621248 B CN 101621248B
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Abstract
The invention discloses a DC to DC converting circuit and a controller thereof. The invention utilizes a multi-phase oscillator or a monostable circuit to make a charge pump control circuit go into a pulse frequency modulation (PFM) mode, once the output voltage is detected to be lower than a preset value, the power can be transported to an output terminal immediately or within an acceptable time length to make the output voltage increase. In this way, the invention has the advantage that the possible time delay in the prior art can be avoided to reach the purpose of reducing the voltage pulse.
Description
Technical field
The invention relates to a kind of DC-to-DC switching circuit and controller thereof, refer to a kind of control electrical appliances for electric charge pump and controller thereof especially.
Background technology
Please refer to Fig. 1, be the existing charge pump control circuit.This control electrical appliances for electric charge pump comprises a full-bridge type commutation circuit, one first capacitor C in, one second capacitor C out, a voltage feedback circuit 30 and a control assembly 10.The full-bridge type commutation circuit has comprised four transistor switch SW1～SW4, is controlled by control signal Con_1, the Con_2 of control assembly 10.When control signal Con_1 was high level, transistor switch SW1, SW2 conducting were to form one first guiding path, and the first capacitor C in stores the electric power that an input power vd D transmits by first guiding path; And when control signal Con_2 is high level, transistor switch SW3, SW4 conducting are to form one second guiding path, the first capacitor C in transmits electric power to the second capacitor C out by second guiding path, makes the second capacitor C out can produce an output voltage V out to load (not drawing).
Then, please refer to Fig. 2, be the signal sequence schematic diagram of control electrical appliances for electric charge pump shown in Figure 1.When in time point t1, voltage feedback signal VFB is lower than reference voltage V1
-, this moment, detection signal DET changed into high level by low level.Yet, this moment, clock signal clk was a low level, just produce the time window of control signal Con_1, control signal Con_1, the low level control signal Con_2 of control assembly 10 output high level, second guiding path is an open-circuit condition, and the first capacitor C un can't transmit electric power to the second capacitor C out.This causes output voltage V out to continue to descend, till time point t2.When time point t2, clock signal clk is a high level, just produce the time window of control signal Con_2, the control signal Con_1 of control assembly 10 output low levels, the control signal Con_2 of high level, the first capacitor C in transmits electric power to the second capacitor C out by second guiding path, makes output voltage V out bottom out until arriving reference voltage V1
+Till (time point t3).Yet, time point t1 to time point t2 during this period of time in, output voltage V out down always, and with reference voltage V1
-Maximum difference reaches Δ V.Therefore, the output voltage of existing charge pump control circuit pulsation (Voltage Ripple) is uncontrollable in the scope of expection and have bigger mains ripple, this situation to also occur in simultaneously on the circuit of same operation pattern (the generation time point of control signal is determined by clock signal clk).
Summary of the invention
Problem in view of above-mentioned existing charge pump control circuit, DC-to-DC switching circuit provided by the invention and controller thereof are when detecting output voltage and be lower than a predetermined value, can be immediately or in an acceptable time length, electric power is sent to output, output voltage is gone up, therefore compared to known control electrical appliances for electric charge pump, can reduce mains ripple.
For reaching above-mentioned purpose, the invention provides a kind of DC-to-DC switching circuit, comprise an electric capacity, one and switch circuit, an output energy-storage units and a controller.This electric capacity couples an input power supply, and this commutation circuit couples this electric capacity, and this output energy-storage units couples this commutation circuit and provides electrical power to a load.This controller is according to a feedback signal of the state of representing this output energy-storage units, control this commutation circuit, make this commutation circuit form one first guiding path and one second guiding path, this input power supply transmits electric power to this electric capacity and this electric capacity by this first guiding path and exports energy-storage units by this second guiding path transmission electric power to this.This controller judges that according to this feedback signal the state of this output energy-storage units is in one first state or one second state, this output energy-storage units is in this first state when feedback signal is higher than first voltage, this output energy-storage units is in this second state when feedback signal is lower than one second voltage, when this output energy-storage units is positioned at this first state, the energy storage of keeping this electric capacity is on a predetermined energy storage, when in a single day this output energy-storage units entered this second state, this controller made this electric capacity transmit electric power immediately and exports energy-storage units to this.
The present invention also provides a kind of DC-to-DC switching circuit, comprises an input energy-storage units, and switches circuit, an output energy-storage units and a controller.This input energy-storage units couples an input power supply, and this commutation circuit couples this input energy-storage units and this output energy-storage units couples this commutation circuit and provides electrical power to a load.This controller is controlled this commutation circuit according to a feedback signal of the voltage of representing this output energy-storage units.Wherein this controller comprises a detecting unit, an oscillating unit and a control unit.This detecting unit produces a detection signal according to this feedback signal.This oscillating unit produces a plurality of clock signals, the identical and phase place difference of the frequency of each clock signal.This control unit comprises a multiplexer to receive these a plurality of clock signals and to export one of these a plurality of clock signals according to this detection signal with selection, this control unit according to the clock signal of this selection and this detection signal to produce one first control signal and one second control signal, this first control signal is controlled this commutation circuit makes this input power supply transmission electric power import energy-storage units to this, and this second control signal is controlled this commutation circuit makes this input energy-storage units transmission electric power export energy-storage units to this.
The present invention also provides a kind of DC-to-DC switching circuit a kind of charge pump controller, and in order to control the commutation circuit of a charge pump circuit, this charge pump controller comprises a detecting unit, an oscillating unit and a control unit.This detecting unit produces a detection signal according to a feedback signal of the state of representing a load.This oscillating unit produces a plurality of clock signals, the identical and phase place difference of the frequency of each clock signal.This control unit comprises one and judges the selection circuit to receive one of these a plurality of clock signals and these a plurality of clock signals of output as a reference clock signal, and this control unit is controlled the change action of this commutation circuit according to this reference clock signal and this detection signal.Wherein, when on behalf of the output of this charge pump circuit, this feedback signal be lower than a predetermined output voltage, this judge to select circuit according to this detection signal again by selecting one in these a plurality of clock signals as this reference clock signal.
Above general introduction and ensuing detailed description are all exemplary in nature, are in order to further specify claim of the present invention.And about other purpose of the present invention and advantage, will be set forth in follow-up explanation and diagram.
Description of drawings
Fig. 1 is an existing charge pump control circuit schematic diagram;
Fig. 2 is the signal sequence schematic diagram of control electrical appliances for electric charge pump shown in Figure 1;
Fig. 3 is the DC-to-DC switching circuit schematic diagram of a preferred embodiment of the present invention;
Fig. 4 is a signal timing diagram embodiment illustrated in fig. 3;
Fig. 5 is the DC-to-DC switching circuit schematic diagram of second preferred embodiment of the present invention;
Fig. 6 is a signal timing diagram embodiment illustrated in fig. 5;
Fig. 7 is the DC-to-DC switching circuit schematic diagram of the 3rd preferred embodiment of the present invention;
Fig. 8 is a signal timing diagram embodiment illustrated in fig. 7;
Fig. 9 is the DC-to-DC switching circuit schematic diagram of the 4th preferred embodiment of the present invention;
Figure 10 is a signal timing diagram embodiment illustrated in fig. 9.
[primary clustering symbol description]
Prior art:
Oscillating unit 12
Transistor switch SW1, SW2, SW3, SW4
Control signal Con_1, Con_2
Input power vd D
Output voltage V out
Voltage feedback signal VFB
Reference voltage V1, V1
-, V1
+
Detection signal DET
Clock signal clk
Time point t1, t2, t3
Level difference Δ V
The first capacitor C in
The second capacitor C out
The present invention:
Non-overlapped signal generation unit 108,118
Non-overlapped unit 108a
Signal selected cell 110
Multiplexer 112
D type keeper circuit 114
Delay circuit 116
Circuits for triggering 120
Input energy-storage units C1
Output energy-storage units C2
Input power vd D
Control signal Con_1, Con_2
Output voltage V out
Feedback signal FB
Diverter switch SW1, SW2, SW3, SW4
Reference voltage V1, V1
-, V1
+
Reference clock signal CLK
Detection signal DET
Time span Δ t
Trigger end CK
Set end D
Output Q
Time point t1, t2, t3, t4
Clock delay signal DIN
Judge signal QOUT
Time of delay delay
Embodiment
Please refer to Fig. 3, be the DC-to-DC switching circuit schematic diagram of a preferred embodiment of the present invention.DC-to-DC switching circuit comprises one and switches circuit, an input energy-storage units C1, an output energy-storage units C2, a feedback circuit 130 and a controller 100, and wherein importing energy-storage units C1 and exporting energy-storage units C2 is electric capacity.Commutation circuit is a semiconductor switch, for example: MOS, IGBT etc., couple input energy-storage units C1, output energy-storage units C2 and an input power vd D, control signal Con_1 according to controller 100 stores to importing energy-storage units C1 with the electric power that transmits input power vd D, and imports the stored energy of energy-storage units C1 to exporting energy-storage units C2 according to the control signal Con_2 of controller 100 to discharge.The electric power that output energy-storage units C2 storage input energy-storage units C1 is discharged also provides output voltage V out to a load (not drawing).Feedback circuit 130 couples output energy-storage units C2, to produce the feedback signal FB that the voltage of energy-storage units C2 is exported in representative.Controller 100 is according to the running of feedback signal FB with generation control signal Con_1, Con_2 control commutation circuit.In the present embodiment, commutation circuit is the full-bridge type commutation circuit, comprises diverter switch SW1, SW2, SW3, SW4.The control signal Con_1 control its switch SW1 of controller 100, SW2 conducting electrically connect input power vd D and input energy-storage units C1 to form one first guiding path, control signal Con_2 control its switch SW3, SW4 conducting electrically connect input energy-storage units C1 and output energy-storage units C2 to form one second guiding path.
Please refer to Fig. 4, be signal timing diagram embodiment illustrated in fig. 3.When feedback signal FB rises to reference voltage V1
+The time, detection signal DET transfers low level to, and the state of this representative output energy-storage units C2 is in one first state of releasing energy.At this moment, control signal Con_1 is a high level and control signal Con_2 is a low level, and diverter switch SW1, SW2 conducting are to form first guiding path, and input power vd D transmits electric power and stores to importing energy-storage units C1; Diverter switch SW3, SW4 end to interrupt second guiding path, and output energy-storage units C2 releases can be to load.When releasing gradually, output energy-storage units C2 can make feedback signal FB drop to reference voltage V1
-The time, detection signal DET transfers high level to, and the state of this representative output energy-storage units C2 is in one second state of energy storage, and at this moment, clock signal clk is a low level.At known circuit, when if detection signal DET transfers high level to, clock signal clk is a low level, then must wait when clock signal clk becomes high level, diverter switch SW3, SW4 just are able to conducting makes output energy-storage units C2 begin energy storage to form second guiding path, in other words, when detection signal DET is high level, and clock signal clk is a low level, because diverter switch SW1, SW2 conducting, and diverter switch SW3, SW4 end, so output voltage VO UT can continue to descend, and produce bigger ripple value.In the present invention, when feedback signal FB drops to reference voltage V1
-The time, control unit 104 produces the control signal Con_2 one time length Δ t of low level control signal Con_1 and high level immediately.Wherein, time span Δ t be a default regular time length Δ t, according to the duty ratio that the cycle determined of clock signal clk or according to the time length that phase place determined of clock signal clk.At this moment, diverter switch SW3, SW4 conducting make output energy-storage units C2 begin energy storage to rise to reference voltage V1 until feedback signal FB to form second guiding path
+Till.When feedback signal FB rises to reference voltage V1 once again
+Till, the state of output energy-storage units is got back to first state of releasing energy, so goes round and begins again, and makes feedback signal FB maintain reference voltage V1
-To reference voltage V1
+The interval.And when the state of output energy-storage units is first state, control signal Con_1 can be as the prior art, continue to switch and make input energy-storage units C1 keep energy storage on a predetermined energy storage, preferred methods is as the present embodiment, control signal Con_1 maintains high level, makes diverter switch SW1, SW2 continue conducting and reduces the switch cost of switch.
Please refer to Fig. 5, be the DC-to-DC switching circuit schematic diagram of another preferred embodiment of the present invention.In the present embodiment, oscillator 106 produces clock signal clk 1, CLK2 inverting each other, and control unit 104 has comprised signal selected cell 110 and non-overlapped signal generation unit 108, select one of clock signal clk 1, CLK2 to be output as reference clock signal CLK by signal selected cell 110 according to detection signal DET, non-overlapped signal generation unit 108 reception reference clock signal CLK and detection signal DET are to produce control signal Con_1, Con_2.Signal selected cell 110 comprises a multiplexer 112, D type keeper (Latch) circuit 114, and the trigger end CK of D type keeper circuit 114 receives detection signal DET, and sets end D receive clock signal CLK2.When detection signal DET transferred high level to, if this moment, clock signal clk 2 was a low level, then output Q output low level signal made multiplexer 112 select clock signal clk 1 output; If clock signal clk 2 is a high level, then output Q output high level signal makes multiplexer 112 select clock signal clk 2 outputs.Non-overlapped signal generation unit 108 comprises a NAND gate and a non-overlapped unit 108a, NAND gate exports non-overlapped unit 108a to after receiving reference clock signal CLK and detection signal DET union, non-overlapped unit 108a is according to the output signal of NAND gate, producing non-overlapped control signal Con_1, Con_2, damage circuit to avoid diverter switch SW1, SW2, SW3, SW4 conducting simultaneously.
Please refer to Fig. 6, be signal timing diagram embodiment illustrated in fig. 5.Before time point t1, the state of output energy-storage units C2 is in first state of releasing energy, this moment, signal selected cell 110 selection clock signal clks 1 were reference clock signal CLK output (represent selecteed signal with solid line among the figure, dotted line is represented non-selected signal).In time point t1, feedback signal FB drops to reference voltage V1
-, detection signal DET transfers high level to makes signal selected cell 110 carry out the signal selection.Clock signal clk 2 is in high level because clock signal clk 1 is in low level, and therefore, signal selected cell 110 selects clock signal clk 2 to be reference clock signal CLK output.Therefore, non-overlapped signal generation unit 108 is the control signal Con_1 of output low level and the control signal Con_2 of high level immediately, and output energy-storage units C2 enters second state of energy storage.When feedback signal FB rises to reference voltage V1 once again
+, the state of output energy-storage units C2 is got back to first state of releasing energy, and to time point t2, feedback signal FB reduces to reference voltage V1
-, the state of output energy-storage units C2 is got back to second state of energy storage, so goes round and begins again.
Please refer to Fig. 7, be the DC-to-DC switching circuit schematic diagram of the 3rd preferred embodiment of the present invention.Compared to Fig. 5, signal selected cell more than 110 has comprised a delay circuit 116, is coupled between oscillator 106 and the D type keeper circuit 114.Delay circuit 116 postpones a time of delay with clock signal clk 1 and is output into clock delay signal DIN behind the delay.D type keeper circuit 114 is exported a judgement signal QOUT according to clock delay signal DIN and detection signal DET, makes multiplexer 112 select clock signal CLK1 or CLK2 in view of the above.Increase delay circuit 116 in the present embodiment and be for fear of as Fig. 6 in time point t2, selected clock signal clk 1, control signal Con_2 but only is maintained at high level utmost point blink, transfers low level subsequently to and makes feedback signal FB down be lower than reference voltage V1 once again
-In the present embodiment, utilize the phase place of clock delay signal DIN judgement clock signal clk 1, CLK2, though to judge whether it is in high level and so is about to transfer to low level, if then avoiding selecting it is reference clock signal CLK output.Therefore, when delay can avoid exporting energy-storage units C2 and entered second state of energy storage time of delay, control signal Con_2 is owing to the problem that causes output energy-storage units C2 energy storage deficiency for the first time for the deficiency of time of high level, its setting can be set according to the difference of various application (difference of load, output energy-storage units C2 charging speed etc.), can or set the time span of a fixed duty cycle according to clock signal clk 1 for a set time length.
Please refer to Fig. 8, be signal timing diagram embodiment illustrated in fig. 7.In time point t1, detection signal DET transfers high level to.At this moment, on behalf of clock signal clk 2, clock signal clk 2 soon transfer low level to by high level for high level but clock delay signal DIN is a low level, is that reference clock signal CLK exports so still select clock signal clk 1.In time point t2, reference clock signal CLK transfers high level to, and control signal Con_2 also transfers high level to makes input energy-storage units C1 begin the energy storage to output energy-storage units C2.In time point t3, detection signal DET transfers high level once again to.At this moment, clock signal clk 1 is that high level but clock delay signal DIN also are high level, and on behalf of clock signal clk 1, this soon transfer low level to by high level, so signal selected cell 110 selection clock signal clks 2 are that reference clock signal CLK exports.In time point t4, reference clock signal CLK transfers high level to, and control signal Con_2 also transfers high level to makes input energy-storage units C1 begin the energy storage to output energy-storage units C2.So, though between time point t1-t2 and time point t3-t4, though feedback signal is lower than reference voltage V1
-Yet its time is of short duration compared to prior art, and the pulsation of lower output voltage is still arranged, and can avoid exporting energy-storage units C2 and enter second state of energy storage the time the first time energy storage time deficiency problem.
Certainly, oscillator 106 of the present invention also can produce plural clock signal, and the identical and phase place difference of the frequency of each clock signal.Multiplexer in the control unit 104 receives those clock signals, and select suitable clock signal to export as reference clock signal according to the phase place and the detection signal DET of those clock signals, when entering second state to avoid exporting energy-storage units C2, the problem of the deficiency of energy storage for the first time.At this embodiment only in order to explanation the present invention, but not in order to restriction patent right scope that the present invention advocated.
Please refer to Fig. 9, be the DC-to-DC switching circuit schematic diagram of the 4th preferred embodiment of the present invention.In the present embodiment, signal selected cell 110 has comprised a non-overlapped signal generation unit 118 and circuits for triggering 120.Circuits for triggering 120 transfer high level in detection signal DET, when representative output energy-storage units C2 enters second state, produce a pulse signal CMP immediately, make control unit 104 produce control signal Con_2 one scheduled time length or a predetermined duty cycle of a high level immediately, make output energy-storage units C2 energy storage immediately.Circuits for triggering 120 can be monostable circuit (One Shot Circuit), comprise a delay circuit 116, a reverser and one and door, the time delay of delay circuit 116 is set and be can be a preset time length, or the predetermined duty cycle of setting according to clock signal clk.Please refer to Figure 10, be signal timing diagram embodiment illustrated in fig. 9.In time point t1, feedback signal FB reduces to reference voltage V1
-, this moment, detection signal DET transferred high level to, and control unit 104 is the control signal Con_2 of export scheduled time length or predetermined duty cycle Δ t immediately, makes feedback signal FB go up to be higher than reference voltage V1
-According to generation time point and the concluding time point of clock signal clk decision control signal Con_1, Con_2, feedback signal FB is risen to reference voltage V1 subsequently
+Till.In the present embodiment, if load makes time span Δ t fail to provide enough energy storage for heavy duty, then work as feedback signal FB and reduce to reference voltage V1 once again
-The time, circuits for triggering 120 still can be triggered, and make feedback signal FB be maintained at reference voltage V1 always
-On.
Therefore, when DC-to-DC switching circuit of the present invention detects output voltage and is lower than a predetermined value, can be immediately or in an acceptable time length, electric power is sent to output, and energy storage is gone up output voltage to the output energy-storage units.Therefore compared to the existing charge pump control circuit, can reduce mains ripple.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (20)
1. a DC-to-DC switching circuit is characterized in that, comprises:
One electric capacity couples an input power supply;
One switches circuit, couples this electric capacity;
One output energy-storage units couples this commutation circuit and provides electrical power to a load; And
One controller, feedback signal according to the state of representing this output energy-storage units, control this commutation circuit, make this commutation circuit form one first guiding path and one second guiding path, this input power supply transmits electric power to this electric capacity and this electric capacity by this first guiding path and exports energy-storage units by this second guiding path transmission electric power to this;
Wherein, this controller judges that according to this feedback signal the state of this output energy-storage units is in one first state or one second state, this output energy-storage units is in this first state when this feedback signal is higher than one first voltage, this output energy-storage units is in this second state when this feedback signal is lower than one second voltage, when this output energy-storage units is positioned at this first state, the energy storage of keeping this electric capacity is on a predetermined energy storage, when in a single day this output energy-storage units entered this second state, this controller made this electric capacity transmit electric power immediately and exports energy-storage units to this.
2. DC-to-DC switching circuit as claimed in claim 1 is characterized in that, when in a single day this output energy-storage units entered this second state, this controller made this electric capacity transmit electric power to this one scheduled time of an output energy-storage units length or a predetermined duty cycle immediately.
3. DC-to-DC switching circuit as claimed in claim 2 is characterized in that, this controller comprises:
One detecting unit produces a detection signal according to this feedback signal;
One oscillating unit produces a clock signal; And
One control unit, timesharing produces one first control signal and one second control signal, this first control signal is controlled this commutation circuit makes this input power supply transmit electric power to this electric capacity, this second control signal is controlled this commutation circuit makes this electric capacity transmission electric power export energy-storage units to this, whether this first control signal produces according to this detection signal decision, and determine the generation time point and the concluding time point of this first control signal according to this clock signal, whether this second control signal produces according to this detection signal and the decision of this clock signal;
Wherein, when this output energy-storage units became this second state by this first state exchange, this control unit produces this second control signal immediately should scheduled time length or this predetermined duty cycle.
4. DC-to-DC switching circuit as claimed in claim 3, it is characterized in that, this control unit comprises a monostable circuit, when this output energy-storage units becomes this second state by this first state exchange, this monostable circuit produces a pulse signal, and making this control unit produce this second control signal should scheduled time length or predetermined duty cycle.
5. DC-to-DC switching circuit as claimed in claim 1 is characterized in that, this controller comprises:
One detecting unit produces a detection signal according to this feedback signal;
One oscillating unit produces a plurality of clock signals, the identical and phase place difference of the frequency of each this clock signal; And
One control unit, comprise a multiplexer to receive these a plurality of clock signals and to export one of these a plurality of clock signals with selection according to this detection signal, this control unit according to the clock signal of this selection and this detection signal to produce one first control signal and one second control signal, this first control signal is controlled this commutation circuit makes this input power supply transmit electric power to this electric capacity, and this second control signal is controlled this commutation circuit makes this electric capacity transmission electric power export energy-storage units to this.
6. as claim 3 or 5 described DC-to-DC switching circuits, it is characterized in that this detecting unit comprises a hysteresis comparator.
7. DC-to-DC switching circuit as claimed in claim 5 is characterized in that this oscillating unit produces two clock signals, and this two clock signal is inverting each other.
8. DC-to-DC switching circuit as claimed in claim 7, it is characterized in that, this control unit comprises a delay circuit, to produce a clock inhibit signal, this multiplexer is selected one of these a plurality of clock signals of output according to this clock delay signal and this detection signal according to one of these a plurality of clock signals.
9. a DC-to-DC switching circuit is characterized in that, comprises:
One input energy-storage units couples an input power supply;
One switches circuit, couples this input energy-storage units;
One output energy-storage units couples this commutation circuit and provides electrical power to a load; And
One controller according to a feedback signal of the voltage of representing this output energy-storage units, is controlled this commutation circuit, and this controller comprises:
One detecting unit produces a detection signal according to this feedback signal;
One oscillating unit produces a plurality of clock signals, the identical and phase place difference of the frequency of each this clock signal; And
One control unit, comprise a multiplexer to receive these a plurality of clock signals and to export one of these a plurality of clock signals with selection according to this detection signal, this control unit according to the clock signal of this selection and this detection signal to produce one first control signal and one second control signal, this first control signal is controlled this commutation circuit makes this input power supply transmission electric power import energy-storage units to this, and this second control signal is controlled this commutation circuit makes this input energy-storage units transmission electric power export energy-storage units to this.
10. DC-to-DC switching circuit as claimed in claim 9 is characterized in that, this control unit is exported one of these a plurality of clock signals according to the phase place of these a plurality of clock signals with selection.
11. DC-to-DC switching circuit as claimed in claim 10 is characterized in that, this oscillating unit produces two clock signals, and this two clock signal is inverting each other.
12. DC-to-DC switching circuit as claimed in claim 11, it is characterized in that, this control unit more comprises a keeper circuit, this keeper circuit couples this oscillating unit, this detecting unit and this multiplexer, and, select one of this two clock signal of output to control this multiplexer according to one of this detection signal and this two clock signal generation one selection signal.
13. DC-to-DC switching circuit as claimed in claim 12, it is characterized in that, this control unit more comprises a delay circuit and is coupled between this keeper circuit and this oscillating unit, one of should a plurality of clock signals postpones to handle this keeper circuit of back input.
14. DC-to-DC switching circuit as claimed in claim 10 is characterized in that, this detecting unit comprises a hysteresis comparator.
15. a charge pump controller in order to control the commutation circuit of a charge pump circuit, is characterized in that, this charge pump controller comprises:
One detecting unit produces a detection signal according to a feedback signal of the state of representing a load;
One oscillating unit produces a plurality of clock signals, the identical and phase place difference of the frequency of each this clock signal; And
One control unit comprises one and judges the selection circuit to receive one of these a plurality of clock signals and these a plurality of clock signals of output as a reference clock signal, and this control unit is controlled the change action of this commutation circuit according to this reference clock signal and this detection signal;
Wherein, when on behalf of the output of this charge pump circuit, this feedback signal be lower than a predetermined output voltage, this judge to select circuit according to this detection signal again by selecting one in these a plurality of clock signals as this reference clock signal.
16. charge pump controller as claimed in claim 15 is characterized in that, this judgement selects circuit to comprise a multiplexer to receive these a plurality of clock signals and to export one of these a plurality of clock signals according to this detection signal with selection.
17. charge pump controller as claimed in claim 16 is characterized in that, this control unit is exported one of these a plurality of clock signals according to the phase place of these a plurality of clock signals with selection.
18. charge pump controller as claimed in claim 17 is characterized in that, this oscillating unit produces two clock signals, and this two clock signal is inverting each other.
19. charge pump controller as claimed in claim 16, it is characterized in that, this control unit more comprises a keeper circuit, this keeper circuit couples this oscillating unit, this detecting unit and this multiplexer, and, select one of these a plurality of clock signals of output to control this multiplexer according to one of this detection signal and this two clock signal generation one selection signal.
20. charge pump controller as claimed in claim 19 is characterized in that, this control unit more comprises a delay circuit and is coupled between this keeper circuit and this oscillating unit, one of should a plurality of clock signals postpones to handle this keeper circuit of back input.
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|---|---|---|---|
| CN2008101276526A CN101621248B (en) | 2008-07-02 | 2008-07-02 | DC to DC converting circuit and controller thereof |
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|---|---|---|---|
| CN2008101276526A CN101621248B (en) | 2008-07-02 | 2008-07-02 | DC to DC converting circuit and controller thereof |
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| CN101621248B true CN101621248B (en) | 2011-09-28 |
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| US8922184B2 (en) * | 2012-03-22 | 2014-12-30 | Realtek Semiconductor Corp. | Integrated switch-capacitor DC-DC converter and method thereof |
| CN102938610A (en) * | 2012-11-20 | 2013-02-20 | 上海宏力半导体制造有限公司 | Charge pump circuit and storage |
| EP2884642B1 (en) * | 2013-12-11 | 2016-10-19 | Nxp B.V. | DC-DC voltage converter and conversion method |
| CN105446402B (en) * | 2014-08-04 | 2017-03-15 | 北京大学深圳研究生院 | Controllable voltage source, shift register and its unit and a kind of display |
| CN107872152B (en) * | 2016-09-28 | 2020-10-30 | 深圳市中兴微电子技术有限公司 | Power management circuit and implementation method thereof |
| CN113394968B (en) * | 2020-03-12 | 2023-09-22 | 长鑫存储技术有限公司 | Charge pump circuit |
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2008
- 2008-07-02 CN CN2008101276526A patent/CN101621248B/en not_active Expired - Fee Related
Non-Patent Citations (2)
| Title |
|---|
| JP特开2004-328843A 2004.11.18 |
| JP特开2005-192350A 2005.07.14 |
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| CN101621248A (en) | 2010-01-06 |
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