CN101610339A - A kind of image sensing synchronized method and circuit thereof - Google Patents
A kind of image sensing synchronized method and circuit thereof Download PDFInfo
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- CN101610339A CN101610339A CNA2009101089100A CN200910108910A CN101610339A CN 101610339 A CN101610339 A CN 101610339A CN A2009101089100 A CNA2009101089100 A CN A2009101089100A CN 200910108910 A CN200910108910 A CN 200910108910A CN 101610339 A CN101610339 A CN 101610339A
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Abstract
The present invention relates to a kind of image sensing synchronized method and circuit thereof, wherein method for synchronous comprises in advance the long and long calculating frequency division value in CPU utilizing camera interface DMA position according to the ADC outputs data bits, system clock is offered CPU again and needs behind the frequency division or directly offer imageing sensor and ADC by described frequency division value; Synchronous circuit comprises system clock, frequency divider and pwm signal generating unit.This image sensing synchronized method and circuit thereof, the image sensing transfer of data of guarantee dma mode, there is not the situation of losing pixel data in more existing parallel bus mode.
Description
Technical field
The present invention relates to digital synchronous circuits, be specifically related to a kind of image sensing synchronized method and circuit thereof.
Background technology
In image processing, the first step, image sensing can be contact-type image sensor (a CIS transducer); In second step, carry out mould/number (AD) conversion; The 3rd step, from A/D converter (ADC), obtain data, in the 4th step, (CPU) handles by microprocessor.At present, because ADC is a parallel bus, conventional connection is that ADC is received on the data/address bus of CPU, and for the choosing of ADC sheet distributes an address space, CPU visits this space and promptly may have access to this ADC.But because the signal of imageing sensor scanning output is continuous, signal AD conversion also is continuous, when sample rate when higher, the data rate that ADC exports continuously is also than higher, with software repeatedly the mode that reads of operator trunk be very easy to lose pixel data, the view data that causes being collected does not make image section content disappearance entirely, makes subsequent image processing and text identification (OCR) mistake occur.The present patent application people adopts the utilizing camera interface (CIM) of CPU to read the data in enormous quantities of ADC at the Chinese utility model patent " a kind of connecting circuit " of first to file, CIM receives passively from ADC by dma mode and passes the data of coming like this, there is not the situation of losing pixel data, but sort circuit also needs to carry out strict synchronism, just can not cause signal or error in data or loss.
Summary of the invention
The technical issues that need to address of the present invention are, how a kind of image sensing synchronized method and circuit thereof are provided, and can satisfy that picture signal is handled and the transmission needs, and guarantee can adopt the utilizing camera interface (CIM) of CPU to read the adc circuit form.
First technical problem of the present invention solves like this: make up a kind of image sensing synchronized method, may further comprise the steps:
1.1) the long and long calculating frequency division value in microprocessor utilizing camera interface direct memory access (DMA) (DMA) position according to the analog to digital converter outputs data bits;
1.2) system clock is offered described microprocessor and need to provide or directly offer imageing sensor and described analog to digital converter behind the frequency division by described frequency division value.
According to image sensing synchronized method provided by the invention, this method comprises that also the system clock behind more described image sensor line initial signal and the frequency division makes described imageing sensor output analog signal and the described analog to digital converter of working receive described analog signal under the control of the system clock behind the described frequency division synchronous.
According to image sensing synchronized method provided by the invention, this method also comprise described frequency divider also provide in addition one the tunnel with described frequency division after the output clock that system clock frequency is identical, phase place is opposite, make that to receive described dateout at described analog to digital converter dateout of working under described output clock control and the long restriction in described DMA position and the described microprocessor of working under the control of described system clock synchronous.
According to image sensing synchronized method provided by the invention, this method comprises that also the line synchronizing signal of more described utilizing camera interface definition and the system clock behind the frequency division make this line synchronizing signal and described analog to digital converter dateout synchronous.
According to image sensing synchronized method provided by the invention, described system clock is provided by described microprocessor master clock, described microprocessor also comprises pulse width modulation (PWM) module, and this module provides the line synchronizing signal and the frame synchronizing signal of described utilizing camera interface definition.
According to image sensing synchronized method provided by the invention, include, but are not limited to following two kinds of concrete forms:
(1) described analog to digital converter outputs data bits length is 16, and described microprocessor utilizing camera interface DMA position is long to be 8, and described frequency division value is 2, and described frequency division carries out frequency division by two-divider.
(2) described analog to digital converter outputs data bits length is 16, and described microprocessor utilizing camera interface DMA position is long to be 16, and described frequency division value is 1, and described frequency division is that described system clock directly is provided.
Another technical problem of the present invention solves like this: make up a kind of image sensing synchronous circuit, with imageing sensor, analog to digital converter is connected with the microprocessor utilizing camera interface, comprises the system clock unit that connects described microprocessor utilizing camera interface, the frequency divider that connects described imageing sensor and analog to digital converter, the image sensor line initial signal generating unit that connects described imageing sensor, connect the line synchronizing signal generating unit of described microprocessor utilizing camera interface and the frame synchronizing signal generating unit that is connected described microprocessor utilizing camera interface by signal synchronization unit; Described system clock unit connects frequency divider, and described frequency divider also connects described signal synchronization unit.
According to image sensing synchronous circuit provided by the invention, described frequency divider is a two-divider, and described signal synchronization unit is the trigger that is used for signal alignment.
According to image sensing synchronous circuit provided by the invention, described system clock unit is described microprocessor master clock module, and each described signal generating unit is built in described microprocessor pulse width modulation module.
Image sensing synchronized method provided by the invention and circuit thereof, adopting frequency division that ADC is initiatively exported with microprocessor reads synchronously, ensure the transfer of data of dma mode, ensure that like this CIM receives the data of coming from the ADC biography passively by dma mode, there is not the situation of losing pixel data in more existing parallel bus mode.
Description of drawings
Further the present invention is described in detail below in conjunction with the drawings and specific embodiments.
Fig. 1 is a specific embodiment of the invention circuit theory schematic diagram;
Fig. 2 is each clock signal sequential schematic diagram in the circuit shown in Figure 1.
Embodiment
At first, the hand-hold scanning equipment of the simple declaration specific embodiment of the invention, its operation principle:
1. pressing paper when drive is worked, touching internal switch, notice MCU starts working in scanning mode.This takes turns and also is used for fixed-direction in scanning simultaneously, teetertotters when preventing to scan.
2. internal switch triggers MCU and enters scanning work, and MCU opens the power supply of the required module of scanning, and the internal register of initialization MCU, and needed square-wave signal during the MCU output scanning is for CIS and ADC work.The external equipment of initialization simultaneously, complete machine enters scanning mode.
3. gear module, when probe moved, drive and paper compressed, and the gear module is driven by drive during scanning, and terminal gear is positioned at the fluted body optocoupler, and when each tooth stopped a light path, optocoupler sent a triggering signal to CPU.
4.MCU receive after the triggering signal delegation or the multirow data that read this position that delegation or multirow CIS collect from CIS signal processor ADC.
5.ADC the analog signal conversion of CIS output is become digital signal, and sends MCU to.
Wherein: CIS scanning, ADC mould/number conversion and MCU need synchronous working in order to avoid obliterated data during real-time working from the ADC reading of data, as shown in Figure 1, in the specific embodiment of the invention, ADC exports 16 picture point data (most-significant byte and least-significant byte), adopt the CIM of 8 DMA and microprocessor to carry out transfer of data, adopt two D flip-flop 74HC74, wherein 1 D flip-flop is as two-divider, 1 is used for signal alignment, this microprocessor also has the PWM module, is used to produce the line synchronizing signal of CIM definition, the frame synchronizing signal of CIM definition and the start of line signal of imageing sensor.
As shown in Figure 2, the concrete operation principle of this circuit is:
1, CIS is a contact-type image sensor, this transducer is linear transducer, energy will be positioned at the voltage signal that the delegation's grey scale change below the transducer is simulated by the output of induction back, the corresponding voltage of brighter place output is higher, the corresponding voltage of darker place output is lower, by serial mode, the voltage output that the gradation conversion that delegation is changed becomes to change.ADCCLK is a clock signal, and PWM2 (SI) is a start of line signal, is output as analog voltage signal.
2, CIS signal processing ADC is that analog signal conversion is become digital signal, and the SIG signal of CIS output is changed in real time, postpones (postponing three pixel clocks) output.This model ADC, the data of each pixel are 16, represent output most-significant byte during the high level of ADCCLK, output least-significant byte during low level with most-significant byte and least-significant byte.
Based on this, we read the data of ADC with the CMOS/CCD camera module interface of microprocessor, needing to read clock frequency ratio A/D change over clock doubles, so in system, will offer A/D change over clock signal and A/D sampled clock signal behind the PCLK two divided-frequency, and the A/D sampling clock is opposite with the phase place of A/D change over clock signal.Connect into the circuit of two divided-frequency with one of them d type flip flop of 74HC74 (double D trigger), for A/D sampling and conversion provide clock signal.
3, CIM transmission:
CIM is a CMOS/CCD camera module interface, this interface works in the YUV transmission mode, it during the data of ADC output place in the middle of the stable level of ADCCLK, and the input of CIM is the edge at PCLK, at this moment, one of them d type flip flop of circuit 74HC74 double D trigger carries out two divided-frequency with PCLK and gets final product, because the state variation of 74HC74 occurs in rising edge of clock signal, in the trailing edge stage of clock signal, just in time aim at during the stable level of ADCCLK.
4, row, frame synchronizing signal produce
CIM work the time needs line synchronizing signal (HSYNC) and frame synchronizing signal (VSYNC), produces with PW0 and the PWM1 of CPU, receives the CIM interface then.Here, the signal very approximate with the output of CMOS camera just possessed, and just has only the pixel of delegation in each frame signal here.Master clock signal is received PCLK by the MCLK output of microprocessor, and PCLK gives ADC and CIS respectively behind two divided-frequency.
5, the signal edge registration process of line synchronizing signal and ADCCLK
In the practical application, the pwm signal that the timer of microprocessor produces, because error relation, the alignment that its edge is not strict, after just HSYNC becomes effectively, the trailing edge of PCLK reads first data of ADC, it or not the high level of aiming at the A/D change over clock very exactly, how to solve? truth table according to d type flip flop can get, it is in rising edge of clock signal that the output level of Q end changes, and Q=D is so receive A/D change over clock signal the clock signal input terminal of d type flip flop, the signal that PWM1 produces is connected to the D end, and then the Q end signal of d type flip flop is inevitable has alignd with the rising edge of A/D change over clock.Utilize another d type flip flop of 74HC74.Connection diagram is as follows.
6, CIM reads ADC:
Microprocessor has utilizing camera interface, is applicable to the signal transmission between common camera and the CPU, and the unique usage of this machine is to read the batch data of ADC with utilizing camera interface now.Because ADC is a parallel bus, conventional connection is should receive on the data/address bus of microprocessor, and for the choosing of ADC sheet distributes an address space, this space of microprocessor access promptly may have access to this ADC.But because the signal of CIS scanning output is continuous, signal AD conversion also is continuous, with software repeatedly the mode that reads of operator trunk be very easy to lose pixel data, the view data that causes being collected does not make image section content disappearance entirely, makes subsequent image processing and text identification (OCR) mistake occur.Therefore, the data in enormous quantities that read ADC with the interface of camera module are more satisfactory, and the CIM module receives passively from ADC and pass the data of coming, and do not have the situation of losing pixel data.
The data that the CIM module reads ADC are the DMA patterns by CPU, and the data among the BUFFER of CIM are up-to-date forever.When drive turns over certain angle, after just probe had moved certain distance, the light path of optocoupler was stopped once that by a tooth of gear the square-wave signal that is produced triggers CPU and reads the buffering area among the CIM one time, so repeatedly, optocoupler produces pulsatile once and reads delegation.Just can with CIS scanned data all read out.So, the interruption of each inch generation has N, and M data are got in each interruption, also just has N * M data to offer program and carries out image splicing use.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to the covering scope of claim of the present invention.
Claims (10)
1, a kind of image sensing synchronized method is characterized in that, may further comprise the steps:
1.1) the long and long calculating frequency division value in microprocessor utilizing camera interface direct memory access (DMA) position according to the analog to digital converter outputs data bits;
1.2) system clock is offered described microprocessor and need to provide or directly offer imageing sensor and described analog to digital converter behind the frequency division by described frequency division value.
2, according to the described image sensing synchronized method of claim 1, it is characterized in that this method comprises that also the system clock behind more described image sensor line initial signal and the frequency division makes described imageing sensor output analog signal and the described analog to digital converter of working receive described analog signal under the control of the system clock behind the described frequency division synchronous.
3, according to claim 1 or 2 described image sensing synchronized methods, it is characterized in that, this method also comprise described frequency divider also provide in addition one the tunnel with described frequency division after the output clock that system clock frequency is identical, phase place is opposite, make that to receive described dateout at described analog to digital converter dateout of working under described output clock control and the long restriction in described direct memory access (DMA) position and the described microprocessor of working under the control of described system clock synchronous.
According to the described image sensing synchronized method of claim 1, it is characterized in that 4, this method comprises that also the line synchronizing signal of more described utilizing camera interface definition and the system clock behind the frequency division make this line synchronizing signal and described analog to digital converter dateout synchronous.
5, according to the described image sensing synchronized method of claim 1, it is characterized in that, described system clock is provided by described microprocessor master clock, and described microprocessor also comprises the pulse width modulation module, and this module provides the line synchronizing signal and the frame synchronizing signal of described utilizing camera interface definition.
6, according to described image sensing synchronized method of claim 1 and circuit thereof, it is characterized in that described analog to digital converter outputs data bits length is 16, described microprocessor utilizing camera interface direct memory access (DMA) position is long to be 8, described frequency division value is 2, and described frequency division carries out frequency division by two-divider.
7, according to described image sensing synchronized method of claim 1 and circuit thereof, it is characterized in that described analog to digital converter outputs data bits length is 16, described microprocessor utilizing camera interface direct memory access (DMA) position is long to be 16, described frequency division value is 1, and described frequency division is that described system clock directly is provided.
8, a kind of image sensing synchronous circuit, be connected with imageing sensor, analog to digital converter and microprocessor utilizing camera interface, it is characterized in that, comprise system clock unit, the frequency divider that connects described imageing sensor and analog to digital converter, the image sensor line initial signal generating unit that is connected described imageing sensor that connects described microprocessor utilizing camera interface, the line synchronizing signal generating unit and the frame synchronizing signal generating unit that is connected described microprocessor utilizing camera interface by signal synchronization unit that connects described microprocessor utilizing camera interface; Described system clock unit connects frequency divider, and described frequency divider also connects described signal synchronization unit.
9, according to the described image sensing synchronous circuit of claim 1, it is characterized in that described frequency divider is a two-divider, described signal synchronization unit is the trigger that is used for signal alignment.
According to described image sensing synchronized method of claim 1 and circuit thereof, it is characterized in that 10, described system clock unit is described microprocessor master clock module, each described signal generating unit is built in described microprocessor pulse width modulation module.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101924859A (en) * | 2010-08-05 | 2010-12-22 | 杭州晟元芯片技术有限公司 | Method for acquiring monochrome data of complementary metal-oxide-semiconductor (CMOS) image sensor |
| CN104113342A (en) * | 2013-11-28 | 2014-10-22 | 西安电子科技大学 | High-speed data synchronous circuit used for high-speed digital-to-analog converter |
| CN108881718A (en) * | 2018-06-22 | 2018-11-23 | 中国科学院长春光学精密机械与物理研究所 | The synchronisation control means of multiple groups TDI cmos imaging system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6046823A (en) * | 1998-03-12 | 2000-04-04 | Avision Inc. | Interface control for analog signal processing |
| CN100493136C (en) * | 2005-11-30 | 2009-05-27 | 北京思比科微电子技术有限公司 | Analog-to-digital converter and controlling method thereof |
| CN201270046Y (en) * | 2008-06-24 | 2009-07-08 | 王培勇 | Terminal timing system based on linear array CCD |
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2009
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101924859A (en) * | 2010-08-05 | 2010-12-22 | 杭州晟元芯片技术有限公司 | Method for acquiring monochrome data of complementary metal-oxide-semiconductor (CMOS) image sensor |
| CN101924859B (en) * | 2010-08-05 | 2012-07-18 | 杭州晟元芯片技术有限公司 | Method for acquiring monochrome data of complementary metal-oxide-semiconductor (CMOS) image sensor |
| CN104113342A (en) * | 2013-11-28 | 2014-10-22 | 西安电子科技大学 | High-speed data synchronous circuit used for high-speed digital-to-analog converter |
| CN104113342B (en) * | 2013-11-28 | 2017-05-24 | 西安电子科技大学 | High-speed data synchronous circuit used for high-speed digital-to-analog converter |
| CN108881718A (en) * | 2018-06-22 | 2018-11-23 | 中国科学院长春光学精密机械与物理研究所 | The synchronisation control means of multiple groups TDI cmos imaging system |
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