CN101609815B - Semiconductor element and manufacturing method thereof - Google Patents
Semiconductor element and manufacturing method thereof Download PDFInfo
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- CN101609815B CN101609815B CN2008100391067A CN200810039106A CN101609815B CN 101609815 B CN101609815 B CN 101609815B CN 2008100391067 A CN2008100391067 A CN 2008100391067A CN 200810039106 A CN200810039106 A CN 200810039106A CN 101609815 B CN101609815 B CN 101609815B
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Abstract
The invention provides a method for manufacturing a semiconductor element. The method comprises the following steps: firstly, providing a first conductive substrate with a circuit region, a capacitor region and a memory cell region; secondly, forming a channel in the substrate of the capacitor region; thirdly, forming a first dielectric layer and a first conductor layer on the substrate of the memory cell region in sequence; fourthly, forming an ONO layer on the substrate; fifthly, removing the ONO layer of the circuit region; sixthly, forming a third dielectric layer on the substrate of the circuit region; seventhly, forming a second conductor layer on the substrate; eighthly, defining a first gate structure in the memory cell region; ninthly, defining a second gate structure in the circuit region, and defining a capacitance structure in the capacitor region; and finally, forming a second conductive doped region in the substrate of two sides of the first gate structure, the second gate structure and the capacitance structure.
Description
Technical field
The invention relates to a kind of semiconductor element and preparation method thereof, and particularly relevant for having SRAM (static random access memory, SRAM) a kind of semiconductor element of the function of the function of middle capacitor and fast flash memory bank (flash memory) and preparation method thereof simultaneously.
Background technology
When semiconductor entered the processing procedure of deep-sub-micrometer (deep sub-micron), size of component was dwindled gradually, for memory cell, just represented the memory cell size more and more little.On the other hand, the data that need to handle, store along with the information electronic product increase day by day, and memory body capacity required in these information electronic products is also just more and more big.
(random access memory RAM) is a kind of memory body that is applied in the information electronic product to random access memory.The random access memory element mainly can be divided into Dynamic Random Access Memory (dynamic random access memory, DRAM) and SRAM (staticrandom access memory, SRAM).The advantage of SRAM is operation and low power consumption fast, and compared to Dynamic Random Access Memory, SRAM must not carry out the periodicity charging to be upgraded, therefore comparatively simple in design and manufacturing, thereby make SRAM be widely used in the information electronic product.
Because SRAM is a kind of volatility (volatile) memory body, it is to come storage data with the transistor conduction state in the memory cell, therefore after eliminating to the electric power of SRAM, data stored in SRAM will disappear completely.On the other hand, non-volatility memory can repeatedly carry out the actions such as depositing in, read, erase of data owing to having, and the data that deposit in can not disappear after outage yet, thus non-volatility memory also be personal computer and electronic equipment a kind of memory cell of extensively adopting.
Along with science and technology is constantly progressive, the data that the information required by electronic product will be handled, store increase day by day, and need take into account simultaneously compact, characteristic such as be convenient for carrying.Therefore, development is a kind of can have quick operation concurrently and quite be necessary with the semiconductor element that the data that deposit in also can not disappear after outage.
Summary of the invention
The object of the present invention is to provide a kind of manufacture method of semiconductor element, it can be integrated the processing procedure of the fast flash memory bank of the processing procedure of capacitor in the SRAM and memory cell region, to reduce fabrication steps.
Another object of the present invention is to be to provide a kind of semiconductor element, and it can have the function of capacitor in the SRAM and the function of fast flash memory bank simultaneously.
The present invention proposes a kind of manufacture method of semiconductor element.The method be provide earlier have circuit region, the substrate of first conductivity type of capacitive region and memory cell region.Then, in the substrate of capacitive region, form irrigation canals and ditches.Then, in the substrate of memory cell region, form first dielectric layer and first conductor layer.Then, in the substrate of circuit region, capacitive region and memory cell region, form second dielectric layer.Second dielectric layer is made up of silicon oxide layer/silicon nitride layer/silicon oxide layer.Subsequently, remove second dielectric layer of circuit region.Subsequently, in the substrate of circuit region, form the 3rd dielectric layer.Then, in the substrate of circuit region, capacitive region and memory cell region, form second conductor layer.Then, define first gate structure in memory cell region.Then, define second gate structure, and define capacitance structure in capacitive region in circuit region.Afterwards, in the substrate of first gate structure, second gate structure and capacitance structure two sides, form the doped region of second conductivity type.
According to the manufacture method of the described semiconductor element of the embodiment of the invention, the formation method of above-mentioned irrigation canals and ditches for example can be prior to forming a plurality of shallow slot isolation structures in the substrate of circuit region, capacitive region and memory cell region.Then, remove the shallow slot isolation structure of capacitive region.
According to the manufacture method of the described semiconductor element of the embodiment of the invention, the first above-mentioned dielectric layer and the formation method of first conductor layer for example are prior to forming dielectric materials layer and conductor material layer in the substrate of circuit region, capacitive region and memory cell region successively.Then, form the patterning cover curtain layer, this patterning cover curtain layer covers the material layer of segment conductor at least of memory cell region.Then, serve as the cover curtain with the patterning cover curtain layer, remove segment conductor material layer and dielectric materials layer.Afterwards, remove the patterning cover curtain layer.
Manufacture method according to the described semiconductor element of the embodiment of the invention, the above-mentioned method that defines first gate structure for example is to form the patterning cover curtain layer earlier, this patterning cover curtain layer covers second conductor layer of circuit region and capacitive region, and cover above first conductor layer of memory cell region to small part second conductor layer.Then, serve as the cover curtain with the patterning cover curtain layer, remove part second conductor layer, second dielectric layer, first conductor layer and first dielectric layer.Afterwards, remove the patterning cover curtain layer.
Manufacture method according to the described semiconductor element of the embodiment of the invention, the above-mentioned method that defines second gate structure and capacitance structure, for example be to form the patterning cover curtain layer earlier, this patterning cover curtain layer cover recall born of the same parents district, circuit region to small part second conductor layer, and cover irrigation canals and ditches top and second conductor layer on every side.Then, serve as the cover curtain with the patterning cover curtain layer, remove part second conductor layer, second dielectric layer and the 3rd dielectric layer.Afterwards, remove the patterning cover curtain layer.
The present invention proposes a kind of semiconductor element in addition.This semiconductor element comprises the doped region of substrate, conductor layer, dielectric layer and second conductivity type of first conductivity type.Have irrigation canals and ditches in the substrate.Conductor layer fills up irrigation canals and ditches, and is positioned in the outer substrate of irrigation canals and ditches.Dielectric layer is disposed between conductor layer and the substrate.Dielectric layer is made up of silicon oxide layer/silicon nitride layer/silicon oxide layer.Doped region is disposed in the substrate of conductor layer two sides.
According to the described semiconductor element of the embodiment of the invention, the material of above-mentioned conductor layer for example is a polysilicon.
The present invention integrates the processing procedure of the fast flash memory bank of the processing procedure of capacitor in the SRAM and memory cell region, therefore can reach the purpose that reduces fabrication steps.In addition, in manufacture process, the present invention utilizes silicon oxide layer/silicon nitride layer/silicon oxide layer simultaneously as the capacitance dielectric layer of the capacitor of dielectric layer and capacitive region between the lock of the fast flash memory bank of memory cell region, therefore makes capacitance dielectric layer have bigger dielectric constant and has improved the stability and the capacitance of capacitor.In addition, the present invention can also increase the capacitance of capacitor by the degree of depth of adjusting irrigation canals and ditches by nationality, so can further reach the purpose of dwindling the capacitive region area.
Importantly, in the present invention, the capacitor arrangement of SRAM also can be used as the fast flash memory bank with SONOS structure and uses.
Description of drawings
Figure 1A to Fig. 1 F is the manufacturing process profile according to the semiconductor element that the embodiment of the invention illustrated.
Among the figure: 100-substrate, 101-circuit region, 102-shallow slot isolation structure, the 103-capacitive region, 104-irrigation canals and ditches, 105-memory cell region, 106,112,116, the 126b-dielectric layer, 108,118, the 126a-conductor layer, 110,114,122,128-patterning cover curtain layer, 120,124-gate structure, 120a-control grid, dielectric layer between the 120b-lock, the 120c-gate of floating, 120d-tunneling dielectric layer, 124a-gate, the 124b-gate dielectric layer, 126-capacitance structure, 130-doped region.
Embodiment
For technological means, creation characteristic that the present invention is realized, reach purpose and effect is easy to understand, below in conjunction with concrete diagram, further set forth the present invention.
Figure 1A to Fig. 1 F is the manufacturing process profile according to the semiconductor element that the embodiment of the invention illustrated.At first, please refer to Figure 1A, substrate 100 is provided.Substrate 100 is the silicon base of first conductivity type.Substrate 100 has circuit region 101, capacitive region 103 and memory cell region 105.Then, in substrate 100, form shallow slot isolation structure 102.The degree of depth of shallow slot isolation structure 102 can be between 0.25 μ m to 0.4 μ m.Then, remove the shallow slot isolation structure 102 of capacitive region 103, in the substrate 100 of capacitive region 103, to form irrigation canals and ditches 104.
Then, please refer to Figure 1B, in the substrate 100 of memory cell region 105, form dielectric layer 106 and conductor layer 108.Dielectric layer 106 can be to form earlier dielectric materials layer (not illustrating) and conductor material layer (not illustrating) successively in substrate 100 with the formation method of conductor layer 108.Dielectric materials layer for example is a silicon oxide layer, and its formation method can be a chemical vapour deposition technique.The thickness of dielectric materials layer is for example between 50
To 200
Between.Conductor material layer can be a polysilicon layer, and its formation method can be a chemical vapour deposition technique.The thickness of conductor material layer for example is 2000
Then, in substrate 100, form patterning cover curtain layer 110.Patterning cover curtain layer 110 covers the material layer of segment conductor at least of memory cell region 105.The material example of patterning cover curtain layer 110 can be a photoresistance.Then, serve as the cover curtain with patterning cover curtain layer 110, remove segment conductor material layer and dielectric materials layer, to form conductor layer 108 and dielectric layer 106.The method that removes segment conductor material layer and dielectric materials layer can be to carry out etch process.
Then, please refer to Fig. 1 C, remove patterning cover curtain layer 110.Then, in substrate 100 conformally (conformally) form dielectric layer 112.Dielectric layer 112 is made up of silicon oxide layer/silicon nitride layer/silicon oxide layer (ONO layer), and its formation method can be to form ground floor silicon oxide layer, silicon nitride layer and second layer silicon oxide layer successively with chemical vapour deposition technique in substrate 100.The thickness of ground floor silicon oxide layer can be 100
The thickness of silicon nitride layer can be 90
The thickness of second layer silicon oxide layer can be 60
Then, in substrate 100, form patterning cover curtain layer 114.Patterning cover curtain layer 114 covers the dielectric layer 112 of capacitive region 103 and memory cell region.The material of patterning cover curtain layer 114 can be photoresistance.Then, serve as the cover curtain with patterning cover curtain layer 114, remove the dielectric layer 112 of circuit region 101.The method that removes the dielectric layer 112 of circuit region 101 can be to carry out etch process.Then, in the substrate 100 of circuit region 101, form dielectric layer 116.The material of dielectric layer 116 can be silica, and its formation method can be a thermal oxidation method.The thickness of dielectric layer 116 for example is 30
Then, please refer to Fig. 1 D, remove patterning cover curtain layer 114.Then, in substrate 100, form conductor layer 118.The material of conductor layer 118 for example is a polysilicon, and its formation method for example is a chemical vapour deposition technique.The thickness of conductor layer 118 for example is 1500
Then, define gate structure 120 in memory cell region 105.Defining the method for gate structure 120 in memory cell region 105, for example can be prior to forming patterning cover curtain layer 122 in the substrate 100.Patterning cover curtain layer 122 covers the conductor layer 118 of circuit region 101 and capacitive region 103, and the layer of segment conductor at least 118 that covers conductor layer 108 tops of memory cell region 105.The material of patterning cover curtain layer 122 for example is a photoresistance.Then, with patterning cover curtain layer 122 is the cover curtain, remove segment conductor layer 118, dielectric layer 112, conductor layer 108 and dielectric layer 106, to define dielectric layer 120b between control grid 120a, lock, to float gate 120c and tunneling dielectric layer 120d and constitute gate structure 120.The method that removes segment conductor layer 118, dielectric layer 112, conductor layer 108 and dielectric layer 106 for example is to carry out etch process.
Then, please refer to Fig. 1 E, remove patterning cover curtain layer 122.Then, define gate structure 124, and define capacitance structure 126 in capacitive region 103 in circuit region 101.Defining gate structure 124 and define the method for capacitance structure 126 in capacitive region 103 in circuit region 101, for example is prior to forming patterning cover curtain layer 128 in the substrate 100.Patterning cover curtain layer 128 covers the floor of segment conductor at least 118 of recalling born of the same parents district 105, circuit region 101, and covers irrigation canals and ditches 104 tops and conductor layer 118 on every side.The material of patterning cover curtain layer 128 for example is a photoresistance.Then, with patterning cover curtain layer 128 is the cover curtain, remove segment conductor layer 118, dielectric layer 112 and dielectric layer 116, constitute gate structure 124 to define gate 124a and gate dielectric layer 124b in circuit region 101, and define conductor layer 126a and dielectric layer 126b in capacitive region 103, wherein conductor layer 126a, dielectric layer 126b and substrate 100 constitute capacitance structures 126.
Afterwards, please refer to Fig. 1 F, remove patterning cover curtain layer 128.Then, in the substrate 100 of gate structure 120, gate structure 124 and capacitance structure 126 2 sides, form the doped region 130 of second conductivity type.Therefore, the capacitance structure 126 that is positioned at capacitive region 103 also can be used as the fast flash memory bank with SONOS structure with doped region 130.
Below will come the semiconductor element among the present invention is explained with the capacitive region among Fig. 1 F 103.
Please refer to Fig. 1 F, the semiconductor element among the present invention comprises the doped region 130 of substrate 100, conductor layer 126a, dielectric layer 126b and second conductivity type of first conductivity type.Have irrigation canals and ditches 104 in the substrate 100.Conductor layer 126a is disposed in the substrate 100, and fills up irrigation canals and ditches 104.Dielectric layer 126b is disposed between conductor layer 126a and the substrate 100.Dielectric layer 126b is made up of silicon oxide layer/silicon nitride layer/silicon oxide layer.Doped region 130 is disposed in the substrate of conductor layer 126a two sides.Conductor layer 126a, dielectric layer 126b and substrate 100 constitute capacitance structure 126.Because the dielectric layer 126b that is made up of silicon oxide layer/silicon nitride layer/silicon oxide layer has bigger dielectric constant, therefore can improve the stability and the capacitance of capacitance structure 126.In addition, but the present invention also nationality increase the area of dielectric layer 126b by the degree of depth that increases irrigation canals and ditches 104, and then improve the capacitance of capacitance structure 126, and can reach the purpose of the area that dwindles capacitive region 103.
Special one what carry is that because dielectric layer 126b is made up of silicon oxide layer/silicon nitride layer/silicon oxide layer, so capacitance structure 126 and doped region 130 also can constitute the fast flash memory bank with SONOS structure.
In sum, the present invention integrates the processing procedure of the fast flash memory bank of the processing procedure of capacitor in the SRAM and memory cell region, therefore can reach the purpose that reduces fabrication steps.
In addition, because the present invention utilizes silicon oxide layer/silicon nitride layer/silicon oxide layer to be used as the capacitance dielectric layer of the capacitor in the SRAM, so the capacitor arrangement of capacitive region also can be used as the fast flash memory bank with SONOS structure.
In addition, the present invention utilizes silicon oxide layer/silicon nitride layer/silicon oxide layer to be used as the capacitance dielectric layer of the capacitor in the SRAM, therefore makes capacitance dielectric layer have bigger dielectric constant, thereby improves the stability and the capacitance of capacitor.
Moreover, because the part of capacitor of the present invention is arranged in irrigation canals and ditches, therefore can increase capacitance, and the area that does not need additionally to increase capacitive region improves capacitance by the degree of depth of adjusting irrigation canals and ditches.
More than show and described basic principle of the present invention and principal character and advantage of the present invention.The technical staff of the industry should understand; the present invention is not restricted to the described embodiments; that describes in the foregoing description and the specification just illustrates principle of the present invention; without departing from the spirit and scope of the present invention; the present invention also has various changes and modifications, and these changes and improvements all fall in the claimed scope of the invention.The claimed scope of the present invention is defined by appending claims and equivalent thereof.
Claims (5)
1. the manufacture method of a semiconductor element is characterized in that, comprising:
The substrate of first conductivity type is provided, and described substrate has circuit region, capacitive region and memory cell region;
In the described substrate of described capacitive region, form irrigation canals and ditches;
In the described substrate of described memory cell region, form first dielectric layer and first conductor layer;
Form second dielectric layer in the described substrate of described circuit region, described capacitive region and described memory cell region, described second dielectric layer is made up of silicon oxide layer/silicon nitride layer/silicon oxide layer;
Remove described second dielectric layer of described circuit region;
In the described substrate of described circuit region, form the 3rd dielectric layer;
In the described substrate of described circuit region, described capacitive region and described memory cell region, form second conductor layer;
Define first gate structure in described memory cell region;
Define second gate structure in described circuit region, and define capacitance structure in described capacitive region; And
In the described substrate of described first gate structure, described second gate structure and described capacitance structure two sides, form the doped region of second conductivity type.
2. the manufacture method of semiconductor element according to claim 1 is characterized in that, the formation method of wherein said irrigation canals and ditches comprises:
In the described substrate of described circuit region, described capacitive region and described memory cell region, form a plurality of shallow slot isolation structures; And
Remove the described shallow slot isolation structure of described capacitive region.
3. the manufacture method of semiconductor element according to claim 1 is characterized in that, the formation method of wherein said first dielectric layer and described first conductor layer comprises:
In the described substrate of described circuit region, described capacitive region and described memory cell region, form dielectric materials layer and conductor material layer successively;
Form the patterning cover curtain layer, described patterning cover curtain layer cover described memory cell region to the described conductor material layer of small part;
With described patterning cover curtain layer is the cover curtain, removes described conductor material layer of part and described dielectric materials layer; And
Remove described patterning cover curtain layer.
4. the manufacture method of semiconductor element according to claim 1 is characterized in that, the method that wherein defines described first gate structure comprises:
Form the patterning cover curtain layer, described patterning cover curtain layer covers described second conductor layer of described circuit region and described capacitive region, and cover above described first conductor layer of described memory cell region to described second conductor layer of small part;
With described patterning cover curtain layer is the cover curtain, removes described second conductor layer of part, described second dielectric layer, described first conductor layer and described first dielectric layer; And
Remove described patterning cover curtain layer.
5. the manufacture method of semiconductor element according to claim 1 is characterized in that, the method that wherein defines described second gate structure and described capacitance structure comprises:
Form the patterning cover curtain layer, described patterning cover curtain layer cover described memory cell region, described circuit region to described second conductor layer of small part, and cover described irrigation canals and ditches top and on every side described second conductor layer;
With this patterning cover curtain layer is the cover curtain, removes described second conductor layer of part, described second dielectric layer and described the 3rd dielectric layer; And
Remove this patterning cover curtain layer.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1619794A (en) * | 2003-11-19 | 2005-05-25 | 旺宏电子股份有限公司 | Method for forming twin bit cell flash memory |
| CN1799139A (en) * | 2003-05-30 | 2006-07-05 | 印芬龙科技股份有限公司 | Nrom semiconductor memory device and fabrication method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1799139A (en) * | 2003-05-30 | 2006-07-05 | 印芬龙科技股份有限公司 | Nrom semiconductor memory device and fabrication method |
| CN1619794A (en) * | 2003-11-19 | 2005-05-25 | 旺宏电子股份有限公司 | Method for forming twin bit cell flash memory |
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Address after: No. 333, Xinghua Street, Suzhou Industrial Park, Suzhou Area, China (Jiangsu) Pilot Free Trade Zone, Suzhou, Jiangsu 215123 Patentee after: Warship chip manufacturing (Suzhou) Limited by Share Ltd. Address before: 215025 No. 333 Hua Hua Street, Suzhou Industrial Park, Jiangsu, Suzhou Patentee before: HE JIAN TECHNOLOGY (SUZHOU) Co.,Ltd. |