CN101609811B - Method for manufacturing integrated circuit - Google Patents

Abstract

The invention discloses a method for manufacturing an integrated circuit, which comprises the following steps: in the S-layer circuit layout of the integrated wiring of a plurality of hardware units, distributing the circuit wiring of the same hardware unit at the same relative position of each layer; forming an aggregation circuit at the same position of each layer, and connecting the aggregation circuits of different hardware units of the same layer at least in a C layer by communication wiring; concentrating each communication wiring at the other relatively same position of the C layer, wherein C is a positive integer less than S; the other relative same position at least comprises the width more than a cutting path, and whether the cutting path is cut or not determines the number of the produced dies and the number of the hardware units contained in each die.

Description

integrated circuit manufacturing method

technical field

The present invention relates to an Integrated Circuit Design and Layout technology, in particular to an integrated circuit manufacturing method with photomask reusability.

Background technique

In many system applications, multiple hardware units with similar functions are often used to enhance work performance. For example, the communication system improves the receiving capacity by increasing the number of receivers; the computer system uses multiple processors to speed up the calculation speed and increase the loadable calculation capacity. Among them, the number of hardware units required by each system varies with the application level and purpose.

Three methods are known to provide different numbers of hardware units:

The first method is to use a single set of photomasks to fabricate dies including hardware units, and then package multiple dies into chips including a desired number of hardware units according to actual applications. Although the photomask cost can be greatly reduced in this way, the communication between hardware units will be limited by the number of pads per die, and the transmission speed will also be affected. In addition, the packaging cost will also be relatively higher.

The second method is to manufacture a set of photomasks to produce corresponding chips for each application requiring different numbers of hardware units. Although less of a concern for communication between hardware units, it is not economical to order multiple sets of photomasks.

The third method is to produce chips containing hardware units with a set of photomasks, and then set a desired number of chips on a Printed Circuit Board (PCB) as the case may be. Although such a method can simplify the ordering of photomasks and packaging, the communication between hardware units is still limited by the pins of each chip in actual application, and the packaging cost is not low.

Contents of the invention

Therefore, the object of the present invention is to provide a method for manufacturing integrated circuits that can reduce the cost of photomasks and packaging, and can reuse photomasks to produce a variety of chips that include different numbers of hardware units without making the difference between hardware units communication is too limited.

Therefore, the integrated circuit manufacturing method of the present invention includes the following steps: in the S-layer circuit layout of integrated wiring of multiple hardware units, distributing the circuit wiring of the same hardware unit at the relatively same position of each layer; forming the relatively same position of each layer Aggregating circuits, and at least connecting different hardware units of the same layer with communication wiring on the C layer; and concentrating each communication wiring on another relatively identical position of the C layer, and C is a positive integer less than S ; Wherein, the other relatively same position includes at least a width of more than one dicing line, and whether the dicing line is cut or not will determine the number of dies produced and the number of hardware units included in each die.

Description of drawings

FIG. 1 is a schematic diagram illustrating that the circuit wiring belonging to the same hardware unit is distributed in the relatively same position of the S-layer circuit layout;

FIG. 2 is a schematic diagram illustrating that the die includes a plurality of modules, and dicing lanes of appropriate width are reserved between each module;

Figure 3 is a schematic diagram illustrating a die being cut by an additional cut;

FIG. 4 is a schematic diagram illustrating that a die is cut by two additional cuts;

5 is a schematic diagram illustrating that the die is subjected to two additional dicing to form dicing blocks each including a hardware unit; and

FIG. 6 is a schematic diagram illustrating that a die is subjected to two additional dicing operations to form dicing blocks comprising one, two, and four hardware units, respectively.

[Description of main component symbols]

1: Die

11: module

111: Input and output pads

12: Module

121: Input and output pads

13: Module

131: Input and output pads

14: module

141: Input and output pads

15: Signal connection

2: die

cut1～7: extra cutting

unit1～4: hardware unit

C _mass1～4 : Gathering circuit

P _unit1～4 : position

P _connect : position

Detailed ways

The aforementioned and other technical contents, features and effects of the present invention will be clearly presented in the following detailed description of two preferred embodiments shown with reference to the accompanying drawings.

Before the present invention is described in detail, it should be noted that in the following description, similar elements are denoted by the same reference numerals.

The preferred embodiment of the integrated circuit manufacturing method of the present invention is suitable for producing a variety of chips including different numbers of hardware units, and each hardware unit can operate independently or combined, for example: each hardware unit can be used as a receiver of a wireless communication system. The main principle is to integrate and route multiple hardware units with similar functions in the S-layer circuit layout (layout), and then after photomask fabrication and chip processing, it is cut and packaged to contain the desired number of hardware unit chip.

【The first preferred embodiment】

Please refer to Figure 1. During the circuit layout, the circuit wiring belonging to the same hardware unit unit1, unit2, unit3, and unit4 is distributed in the relatively same position P _unit1 , P _unit2 , P _unit3 , and P _unit4 of the S-layer circuit layout, and assembled Relatively same positions P _unit1-4 of each layer form aggregation circuits C _mass1 , C _mass2 , C _mass3 , C _mass4 . In the C layer, at least the aggregation circuits C _mass1~ 4 of the different hardware units unit1~4 on the same layer are connected by communication wiring, and each communication wiring is concentrated in another relatively same position P _connect of the C layer, and C is a positive integer less than S. The other relative to the same position P _connect includes at least a width of more than one dicing line, and whether the dicing line is cut or not will determine the number of dies produced and the number of hardware units included in each die.

In addition, the placement (place) intervals of these aggregation circuits C _mass1-4 must conform to the chip cutting rules, so that different aggregation circuits C _mass1-4 reserve appropriate width dicing lines to ensure that the subsequent cutting operation does not make the hardware units unit1-4 4 Potency is impaired. This approach is different from the arbitrary routing method used in general layout.

The C-layer circuit layout where the communication wiring is located can be adjusted and modified according to the expected number of hardware units of a single chip, so as to properly connect only different numbers of hardware units, so as to prepare for cutting dicing lanes in subsequent operations. At this time, the circuit layout of the other (SC) layers remains unchanged, and at most the circuit layout of the C layer needs to be adjusted. For example: if it is known that it is necessary to produce a chip comprising four hardware units (use 1, as shown in Figure 2), a chip comprising two hardware units (use 2, as shown in Figure 3) and a chip comprising one hardware unit (Purpose 3, as shown in Figure 4). When the layout of the purpose 1 chip has been completed, it is only necessary to modify at least a part of the circuit layout of the C layer (assuming that it is a C _2unit (C _2unit > 0)) layer circuit layout) to complete the layout of the purpose 2 chip; For the layout of the 2 chips, it is only necessary to modify at least part of the circuit layout of the C layer (assuming that compared with the layout of the 2 chips, the number of circuit layout layers that will be changed is C _1unit (C _1unit > 0)) ie The layout of purpose 3 chips can be completed. Please note that the layout modification may be aimed at modifying the position of P _connect (for example: removing communication wiring) or P _unit1~4 (for example: avoiding input floating) of the layer.

Next, a photomask layer is fabricated for each possible circuit layout layer, and the number of possible circuit layout layers in this example is S+C _2unit +C _1unit . Then, according to the actual application, appropriate S photomask layers are selected from these photomask layers to be processed into a desired wafer (wafer), as shown in FIGS. 2 , 3 , and 4 .

Referring to FIG. 2 , one die 1 of the chip includes a plurality of modules 11, _{12, 13, 14 respectively corresponding to these aggregation circuits C mass1-4} and a plurality of modules 11, 12, 13, 14 respectively corresponding to these communication wirings and located on the dicing lanes. The signal connections 15, and the signal connections 15 between different modules 11-14 are exposed outside the relevant modules 11-14. And each module 11 - 14 includes a plurality of input and output pads 111 , 121 , 131 , 141 (I/Opad). Wherein, there is no associated signal connection 15 in some cutting lanes in FIG. 3 and FIG. 4 because the layout has been adjusted and modified according to the situation.

Then, additional dicing is performed on the die 1 to obtain a dicing block including a desired number of hardware units, and each dicing lane can be selected to perform dicing or not. When use 1 is selected (see Figure 2), no additional dicing is required because it happens that the number of hardware units in die 1 is exactly what is needed. When selecting purpose 2 (see Fig. 3), an extra cutting cut1 is performed along the cutting road that has no relation to obtain two cutting blocks (one is made up of modules 11 and 12, and the other is made up of modules 13 and 14) ). In the same way, four cutting blocks belonging to modules 11-14 can be obtained by performing additional cutting cut2 and cut3 on the unconnected cutting lanes in FIG. 4 (application 3). Since the obtained dicing blocks can be operated independently, they can be regarded as dies, and finally the desired chips can be obtained by performing packaging operations separately.

The reason for modifying the circuit layout in this embodiment is: when the operation of the modules 11-14 cannot be independent of the signal connection 15, if the die 1 in FIG. Some related circuits do not work properly, such as input floating.

So far, it can be seen that in this embodiment, desired chips can be manufactured only through different versions of modified circuit layouts and additional dicing operations. In such a chip, the communication between the hardware units unit1-4 is directly implemented by layout and wiring, so the transmission speed is not affected, and the number of signal connections 15 can be determined according to the wiring circuit, and will not be affected by the chip as known. limited by the solder pad of the pin or die.

[Second preferred embodiment]

During the layout operation, it is not necessarily necessary to modify the C-layer circuit layout, which can be determined according to the actual circuit design. And when the circuit design makes the operation of the modules 11-14 independent of the signal connection 15, the circuit layout does not need to be changed, and the die can be directly and arbitrarily cut to obtain the desired chip. For example, the die 1 in FIG. 5 can be additionally cut through cut4 , cut5 to make a chip containing a hardware unit. The die 2 in FIG. 6 can be cut by additional cuts cut6 and cut7, and packaged into chips including one, two and four hardware units respectively.

It is worth noting that the number of modified layers usually varies with the quality of the circuit design. In the worst case, all the C-layer circuit layouts in the centralized layout must be modified, and in the best case, cutting can be performed without modification. Therefore, the prior consideration of the circuit designer will contribute to the smooth progress of the present invention. For example: Some circuit designers will set the working mode for various possible situations (that is, the number of hardware units included in each die). When a specific working mode is selected, the operation of the cutting block can be independent of the signal connection 15 , so that the number of modified circuit layout layers can be reduced, or even without any changes.

It is worth noting that the C photomask layers arranged in a centralized manner may refer to a metal (Metal) photomask layer or a connection (Via) photomask layer, and is not limited thereto. In addition, the C photomask layers may be in a continuous relationship with each other, or may be arbitrarily selected from all the S photomask layers. Of course, the circuit layouts of the modified C _unit2 and C _unit1 layers do not have to be continuous. Moreover, these signal connections 15 can be used to communicate with different modules 11-14, but can also be used as input/output pads 111-141 of related modules 11-14 for input/output purposes.

To sum up, in the integrated circuit manufacturing method of the present invention, the communication wiring between the aggregation circuits C _mass1-4 used to communicate with different hardware units unit1-4 is centralized and laid out in the C-layer circuit layout, so at most it only needs to modify _C2unit , C2unit _{1 unit} layer circuit layout, photomask and chip cutting operations can be performed to package multiple chips containing different numbers of hardware units, without hindering the communication between hardware units unit1-4, so the purpose of the present invention can indeed be achieved .

The above are only preferred embodiments of the present invention, and should not limit the scope of the present invention with this, that is, all simple equivalent changes and modifications made according to the claims of the present invention and the content of the description of the invention still belong to the present invention. within the scope of invention patents.

Claims (10)

1. A method for manufacturing an integrated circuit, comprising the following steps: In the S-layer circuit layout of integrated wiring of multiple hardware units, the circuit wiring of the same hardware unit is distributed in the relatively same position of each layer; Form an aggregation circuit at the relatively same position of each layer, and at least connect the aggregation circuits of different hardware units on the same layer with communication wiring on layer C; and Concentrate each communication wiring on another relatively same position of layer C, and C is a positive integer smaller than S; Wherein, the other relatively same position includes at least a width of more than one dicing line, and whether the dicing line is cut or not will determine the number of dies produced and the number of hardware units contained in each die, and the C-layer circuit layout It can be adjusted according to the number of hardware units to be included in the cut out die. 2. The method of manufacturing an integrated circuit according to claim 1, wherein the placement interval of each aggregation circuit conforms to the chip cutting rule, so that an appropriate width is reserved as the cutting line. 3. The manufacturing method of an integrated circuit according to claim 1, wherein each dicing line can be selected to be diced or not to be diced. 4. The method of manufacturing an integrated circuit according to claim 1, wherein if the dicing line is to be cut, at most the C-layer circuit layout needs to be adjusted. 5. The method for fabricating an integrated circuit according to claim 1, wherein the layer corresponding to the circuit layout of layer C is a metal photomask layer. 6. The method of manufacturing an integrated circuit according to claim 1, wherein the layer corresponding to the circuit layout of the layer C is connected to the photomask layer. 7. The method for fabricating an integrated circuit according to claim 1, wherein the circuit layout corresponding to the layer C comprises a metal photomask layer and a connecting photomask layer. 8. The manufacturing method of an integrated circuit according to claim 1, wherein each die comprises a plurality of signal connections respectively corresponding to the communication wirings, and a part of them can be used for input and output purposes. 9. According to the integrated circuit manufacturing method described in claim 1, further comprising the following steps: According to the number of hardware units included in each die, the working mode is set for the individual die. 10. The manufacturing method of an integrated circuit according to claim 1, wherein each hardware unit can be independently or combined as a receiver of a wireless communication system.

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