CN101609811B

CN101609811B - Method for manufacturing integrated circuit

Info

Publication number: CN101609811B
Application number: CN2008101288595A
Authority: CN
Inventors: 杨立平; 陈碧成; 康汉彰; 颜仁鸿
Original assignee: Realtek Semiconductor Corp
Current assignee: Realtek Semiconductor Corp
Priority date: 2008-06-20
Filing date: 2008-06-20
Publication date: 2012-07-18
Anticipated expiration: 2028-06-20
Also published as: CN101609811A

Abstract

The invention discloses a method for manufacturing an integrated circuit, comprising the following steps: circuit distribution wires of a same hardware unit are distributed at a relative same position of each layer in the S-layer circuit distribution of the integrated distribution wires of a plurality of hardware units; the relative same position of each layer forms an integrated circuit, and a C layer of S layers is at least connected with the integrated circuits of different hardware units of a same layer through communicating distribution wires; and the communicating distribution wires are gathered at the other relative same position of the C layer of the S layers, wherein the C is a positive integer less than the S, the other relative same position at least includes a width more than that of a cutting passage, and whether the cutting passage is cut can determine the number of generated tube cores and the number of the hardware units included by each tube core.

Description

Integrated circuit manufacture method

Technical field

The invention relates to a kind of IC design and layout (Integrated Circuit Design andLayout) technology, be meant a kind of photomask (mask) integrated circuit manufacture method of usability again that possesses especially.

Background technology

In many system applies, use a plurality of intimate hardware cells to strengthen task performance through regular meeting.For example, communication system promotes receiving ability through increasing the receiver number; Computer system is accelerated arithmetic speed and improves to carry operational capability with a plurality of processors.Wherein, the number of each required hardware cell of system with application level with purpose and different.

Known have three in order to the method that the different hardware number of unit is provided:

First method is to utilize a single set of photomask to make the tube core (die) that comprises hardware cell, according to practical application a plurality of die package (package) is become to comprise expectation hardware cell number of dies then.Though so can significantly reduce the photomask expense, but the communication between hardware cell will be subject to weld pad (pad) number of each tube core, and transfer rate is also influenced.In addition, packaging cost also will improve many relatively.

Second method is to need the purposes of different hardware number of unit to each, makes a cover photomask respectively and produces corresponding chip (chip).Though do not worry the communication between hardware cell, place an order and overlap photomasks more and be not inconsistent economic benefit.

The third method is the chip that comprises hardware cell with a cover photomask production, and the chip of desired number is set on printed circuit board (PCB) (Printed Circuit Board is called for short PCB) then according to circumstances.Though such method can be simplified placing an order of photomask and encapsulation, the communication during practical application between hardware cell still can receive the restriction of the pin (pin) of each chip, and to take packaging cost not low yet.

Summary of the invention

Therefore; The object of the invention; Promptly be to provide a kind of integrated circuit manufacture method that can reduce photomask and packaging cost, can reuse photomask and produce the multiple chip that comprises the different hardware number of unit, and do not make the communication between hardware cell receive too much restriction.

So integrated circuit manufacture method of the present invention comprises following steps: integrate in the S layer circuit layout of wiring at a plurality of hardware cells, the wiring of same hardware cell is distributed in every layer relative same position; Every layer relative same position is formed the gathering circuit, and connect gathering circuit to link up wiring at least with the different hardware unit of one deck in C layer wherein; Reach each communication wiring is concentrated on wherein another relative same position of C layer, and C is the positive integer less than S; Wherein, this another relative same position comprises the above width of a Cutting Road at least, and whether this Cutting Road cuts the hardware cell number that tube core number and each tube core that will determine to be produced are comprised.

Description of drawings

Fig. 1 is a sketch map, explains that the wiring that belongs to same hardware cell is distributed in the relative same position of S layer circuit layout;

Fig. 2 is a sketch map, explains that tube core comprises a plurality of modules, and each intermodule is reserved the Cutting Road of proper width;

Fig. 3 is a sketch map, explains that tube core is cut by extra cutting together;

Fig. 4 is a sketch map, explains that tube core is cut by the extra cutting in two roads;

Fig. 5 is a sketch map, explains that tube core receives the extra cutting in two roads and forms the cutting block that comprises a hardware cell respectively; And

Fig. 6 is a sketch map, explains that tube core receives the extra cutting in two roads and forms the cutting block that comprises one, two, four hardware cell respectively.

[main element symbol description]

1: tube core

11: module

111: the input and output weld pad

12: module

121: the input and output weld pad

13: module

131: the input and output weld pad

14: module

141: the input and output weld pad

15: signal connects

2: tube core

Cut1～7: extra cutting

Unit1～4: hardware cell

C _Mass1～4: assemble circuit

P _Unit1～4: the position

P _Connect: the position

Embodiment

About aforementioned and other technology contents, characteristics and effect of the present invention, following cooperation with reference to two DETAILED DESCRIPTION OF THE PREFERRED shown in the accompanying drawing in, can clearly appear.

Before the present invention is described in detail, be noted that in following description similar elements is to represent with identical numbering.

The preferred embodiment of integrated circuit manufacture method of the present invention is applicable to produces the multiple chip that comprises the different hardware number of unit, and each hardware cell all can independently or merge and operate, and for example: each hardware cell can be used as the receiver of wireless telecommunication system.Cardinal principle is earlier a plurality of intimate hardware cells to be integrated wiring (routing) in S layer circuit layout (layout), then after photomask making and chip manufacture, again with its cutting and be packaged into the chip of the hardware cell that comprises desired number.

[first preferred embodiment]

See also Fig. 1, when circuit layout, make the wiring that belongs to same hardware cell unit1, unit2, unit3, unit4 be distributed in the relative same position P of this S layer circuit layout _Unit1, P _Unit2, P _Unit3, P _Unit4, and gather every layer relative same position P _Unit1～4Form and assemble circuit C _Mass1, C _Mass2, C _Mass3, C _Mass4In C layer wherein, connect gathering circuit C to link up wiring at least with different hardware unit unit1～4 of one deck _Mass1～4, and each is linked up wiring concentrate on wherein another relative same position P of C layer _Connect, and C is the positive integer less than S.And this another relative same position P _ConnectAt least comprise the above width of a Cutting Road, and whether this Cutting Road cuts and will determine tube core (die) the hardware cell number that number and each tube core comprised that produced.

In addition, these assemble circuit C _Mass1～4Arrangement (place) at interval must meet the chip cutting rule so that the different circuit C that assembles _Mass1～4Between reserve the Cutting Road of proper width, the cutting operation after guaranteeing does not make hardware cell unit1～4 usefulness be damaged.Such way is different from any wire laying mode that general layout adopts.

And the C layer circuit layout of linking up the wiring place can come redjustment and modification according to the desired hardware cell number of one chip, only to get in touch the hardware cell of different numbers appositely, thinks in the subsequent job if having and will cut Cutting Road and prepare.This moment, all the other (S-C) layer circuit layouts remained unchanged, and need adjust this C layer circuit layout at the most.For instance: if known meeting need to be produced the chip (purposes 1, as shown in Figure 2) that comprises four hardware cells, comprises the chip (purposes 2, as shown in Figure 3) of two hardware cells and comprised the chip (purposes 3, as shown in Figure 4) of a hardware cell.When accomplishing the layout of purposes 1 chip, at least a portion that only needs to revise in the C layer circuit layout (supposes it is C _2unit(C _2unit＞0)) layer circuit layout) can accomplish the layout of purposes 2 chips; When accomplishing the layout of purposes 2 chips, at least a portion that only need revise again in the C layer circuit layout (supposes that compared to the layout of purposes 2 chips the circuit layout number of plies that unusual fluctuation can take place is C _1unit(C _1unit＞0)) individual) can accomplish the layout of purposes 3 chips.Note that layout modification possibly be to the P that revises layer _Connect(for example: remove and link up wiring) or P _Unit1～4(for example: avoid importing suspension joint (input floating)) position.

Then, for the possible circuit layout of each layer made a photo mask layer, and the possible circuit layout number of plies of this example is S+C _2unit+ C _1unitThen, according to practical use, from these photo mask layer, select a suitable S photo mask layer and be processed into required chip (wafer), like Fig. 2,3, shown in 4.

With Fig. 2, a wherein tube core (die) 1 of chip comprises a plurality of corresponding respectively these and assembles circuit C _Mass1～4Module 11,12,13,14 and a plurality of corresponding respectively these link up wiring and the signal that is positioned on the Cutting Road is connected 15, and the signal connection 15 of 11～14 of disparate modules is to be exposed to outside the correlation module 11～14.And each module 11～14 comprises a plurality of input and output weld pads 111,121,131,141 (I/Opad).Wherein, not exist the signal of tool contact effect to be connected 15 be because redjustment and modification according to circumstances during layout to the part Cutting Road of Fig. 3 and Fig. 4.

Then, tube core 1 is carried out extra cutting obtaining comprising the cutting block of expectation hardware cell number, and each Cutting Road can be selected all to cut or do not cut.(see figure 2) when selecting purposes 1 because by chance the hardware cell number of tube core 1 meet required, so need not carry out extra cutting.(see figure 3) when selecting purposes 2 is to carry out an extra cutting cut1 along the Cutting Road that does not have the contact relation, obtains two cutting blocks (be made up of

module

11 and 12 for, be made up of

module

13 and 14).In like manner, the Cutting Road that has not had the contact relation among Fig. 4 (purposes 3) is carried out extra cutting cut2, cut3, can obtain four cutting blocks that belong to module 11～14 respectively.Because gained cutting block all can independently operate, so all can be considered tube core, carries out the chip that packaging operation can obtain expectation at last respectively.

The reason that present embodiment is revised circuit layout is: when the running of module 11～14 can not be independent of signal and connects 15; If cut without revising direct tube core 1 to Fig. 2; May cause the part correlation circuit of each cutting in block can't normal operation, for example import suspension joint (input floating).

So far can know that present embodiment only need just can be processed the expectation chip through the modification circuit layout and the extra cutting operation of different editions.In such chip; The communication of between hardware cell unit1～4 is directly to realize with placement-and-routing; So transfer rate is unaffected, and signal connects 15 numbers and can decide according to wired circuit, not limited by the pin of chip or the weld pad of tube core.

[second preferred embodiment]

And during the layout operation, may not need to revise this C layer circuit layout, can look side circuit design and judge.And when circuit design makes the running of module 11～14 can be independent of signal to connect 15; Circuit layout does not need unusual fluctuation; Can directly cut this tube core arbitrarily and obtain the expectation chip, for example: the tube core 1 of Fig. 5 can be processed the chip that comprises a hardware cell through extra cutting cut4, cut5.And after the tube core 2 of Fig. 6 can receive extra cutting cut6, cut7 cutting, be encapsulated as the chip that comprises one, two, four hardware cell respectively.

It should be noted that the common modification number of plies can be with the circuit design quality and different, worst condition is that the C layer circuit layout of all centralized layouts all must be revised, and optimal cases is need not revise and can cut.So considering in advance of circuit designers of the present inventionly carried out helping smoothly.For example: some circuit designers can possibly situation (promptly being directed against the hardware cell number that each tube core comprised) be set mode of operation for various; When selecting specific operation mode for use; Can make the running of cutting block be independent of signal connection 15; So just, can reduce and revise the circuit layout number of plies, or even not need any change.

Even more noteworthy, the C of a centralized layout photo mask layer can be meant metal (Metal) photo mask layer or connection (Via) photo mask layer, and not as limit.And this C photo mask layer can be a serial relation each other, also can in all S photo mask layer, choose arbitrarily.Certainly, the C that is modified _Unit2, C _Unit1Layer circuit layout also needs not to be continuous.Moreover it can be to be used for getting in touch disparate modules 11～14 that these signals connect 15, but also can be used to be used as the input and output weld pad 111～141 of correlation module 11～14, thinks the input and output purposes.

In sum, integrated circuit manufacture method of the present invention will be in order to link up the gathering circuit C of different hardware unit unit1～4 _Mass1～4Between link up wiring centralized layout in C layer circuit layout, so at most only need revise wherein C _2unit, C _1unitLayer circuit layout can carry out photomask and chip cutting operation, being packaged into a plurality of chips that comprise the different hardware number of unit, and the communication that does not hinder in hardware cell unit1～4, so can reach the object of the invention really.

The above person; Be merely the preferred embodiments of the present invention; When not limiting the scope that the present invention implements with this, simple equivalent variations and the modification promptly done according to claim of the present invention and invention description generally all still belong in the scope that patent of the present invention contains.

Claims

1. integrated circuit manufacture method comprises following steps:

Integrate in the S layer circuit layout of wiring at a plurality of hardware cells, the wiring of same hardware cell is distributed in every layer relative same position;

Every layer relative same position is formed the gathering circuit, and connect gathering circuit to link up wiring at least with the different hardware unit of one deck in C layer wherein; And

Each is linked up wiring concentrate on wherein another relative same position of C layer, and C is the positive integer less than S;

Wherein, This another relative same position comprises the above width of a Cutting Road at least; And whether this Cutting Road cuts the hardware cell number that tube core number and each tube core that will determine to be produced are comprised, and wherein this C layer circuit layout can according to the tube core that cuts out the hardware cell number that will comprise adjust.

2. according to the described integrated circuit manufacture method of claim 1, wherein the arrangement of each gathering circuit all meets the chip cutting rule at interval, to reserve proper width as this Cutting Road.

3. according to the described integrated circuit manufacture method of claim 1, wherein each Cutting Road all can be selected to cut or do not cut.

4. according to the described integrated circuit manufacture method of claim 1, wherein to cut this Cutting Road, then need adjust this C layer circuit layout at the most as if having.

5. according to the described integrated circuit manufacture method of claim 1, wherein corresponding C layer circuit layout be the metal photomask layer.

6. according to the described integrated circuit manufacture method of claim 1, wherein corresponding C layer circuit layout be to connect photo mask layer.

7. according to the described integrated circuit manufacture method of claim 1, the comprising the metal photomask layer and connect photo mask layer of wherein corresponding C layer circuit layout.

8. according to the described integrated circuit manufacture method of claim 1, wherein each tube core comprises the signals connection of a plurality of corresponding respectively these communication wirings, and wherein some can be used for being used as the input and output purposes.

9. according to the described integrated circuit manufacture method of claim 1, also comprise following steps:

To the hardware cell number that each tube core comprised, individual die is set mode of operation.

10. according to the described integrated circuit manufacture method of claim 1, wherein each hardware cell all can independently or merge the receiver as wireless telecommunication system.