CN101609392A - Serial data transmits allocating method, system and controller thereof - Google Patents
Serial data transmits allocating method, system and controller thereof Download PDFInfo
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- CN101609392A CN101609392A CNA2008101259785A CN200810125978A CN101609392A CN 101609392 A CN101609392 A CN 101609392A CN A2008101259785 A CNA2008101259785 A CN A2008101259785A CN 200810125978 A CN200810125978 A CN 200810125978A CN 101609392 A CN101609392 A CN 101609392A
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Abstract
A kind of serial data transmits allocating method, system and controller thereof, its be applicable to main frame and have nonvolatile memory with the storage device of chip between the serial data transmission.Specific markers can be injected towards by main frame and be sent in the serial data of storage device, makes serial data be able to write instruction by transmission and is assigned to chip.Afterwards, by carrying out a plurality of reading command, the response message that chip produced can inerrably be received.
Description
Technical field
The invention relates to that a kind of serial data transmits allocating method, system and controller thereof, and particularly be applicable to that relevant for a kind of serial data from the main frame Data transmission to the storage device with flash memory and chip transmits allocating method, system and controller thereof.
Background technology
Digital camera, mobile phone and MP3 player are very rapid in growth over the years, make the consumer also increase rapidly the demand of Storage Media.Because flash memory (Flash Memory) has that data are non-volatile, power saving, volume are little, and there is not characteristic such as mechanical structure, so be built in the above-mentioned various portable multimedia devices of giving an example in being fit to very much.
On the other hand, along with the user accepts to use stored value card and prepayment Stored Value gradually, make that the use of smart card is universal day by day.Smart card (Smart Card) is to have for example integrated circuit (IC) chip of the assembly of microprocessor, card operation system, security module and storer (IC chip), carries out scheduled operation to allow the holder.Smart card provides calculating, encryption, two-way communication and security function, makes this card can also reach the function that its stored data are protected except the function of storage data.(SubscriberIdentification Module, SIM) card is one of them exemplary applications of smart card to use employed subscriber identification module in the machine-processed cellular telephone of global system for mobile communications (GSM).Yet itself is subject to storage volume smart card, therefore begins in recent years to combine with the storage card of mass storage, with the storage volume of amplification smart card.
In known technology, be to distinguish the data that send smart card or flash memory in conjunction with the application of flash memory and smart card by special command, the problem that this special command may cause hardware unit or driver to support.In addition, be to judge about the kenel information of transmission serial data whether this serial data is the command format of smart card in this special command of comparison in known technology.Yet, the problem that the command format that the method tends to cause the generic-document data and belong to smart card collides (be about to the erroneous judgement of generic-document data and be the serial data of smart card).
In addition, have in the application of electronic product of high-speed cache (Cache) at some, restriction because of these electronic products itself, the transmission of serial data also can't be walked around high-speed cache between smart card and the electronic product, and make response message that smart card produced and can't inerrably be back to the electronic product that is depended on, and then the restriction smart card has the application on the electronic product of high-speed cache in this class.For instance, in the mobile phone of a Java system, because of the Java system does not support must directly not carry out high-speed cache by high-speed cache such as NO Cache etc. the instruction of access, so be difficult to smart card and flash memory are applied in the mobile phone of this class Java system with the form that is integrated into storage card.Please refer to Fig. 1, Fig. 1 is the functional block diagram of the main frame 10 of known collocation storage card 12.Main frame 10 is a kind of electronic product (as: mobile phone of Java system), and has high-speed cache 14, and storage card 12 has flash memory 16 and intelligent card chip 18.High-speed cache 14 all can be passed through in data transfer path between main frame 10 and the storage card 12.Yet, because high-speed cache 14 can be kept in the cause of the data of being transmitted between nearest main frame 10 and the storage card 12, when main frame 10 desires when intelligent card chip 18 obtains data, if when having had in the high-speed cache 14 with data that reading command conforms to, then high-speed cache 14 will be sent to the data that conform to main frame 10.Yet under such framework, the response message of intelligent card chip 18 tends to be replaced by high-speed cache 14 existing data, and makes the encryption of intelligent card chip 18 and the function of secure communication be greatly affected.
Base this, the system and method that needs development one cover can inerrably transmit the response message of smart card in conjunction with the application of flash memory and smart card is arranged.
Summary of the invention
The invention provides a kind of serial data and transmit dispatching system and controller thereof, can inerrably transmit the response message of smart card.
The invention provides a kind of serial data and transmit allocating method, can inerrably transmit the response message of smart card.
Serial data provided by the present invention transmits allocating method, system and controller thereof, except can be applicable in the application in conjunction with flash memory and smart card, in also can be applicable to other chip in addition and combining of flash memory being used, inerrably transmitting the response message of chip, and said chip can be radio-frequency (RF) identification chip, wireless transmission chip (as: Bluetooth chip) or multimedia control chip (as: digital recording chip).
The present invention proposes a kind of serial data and transmits allocating method, and it is applicable to from main frame Data transmission string to the storage device with nonvolatile memory and chip.This serial data transmits allocating method and comprises: transmission writes instructs to storage device, writes to instruct to be set to write first serial data to storage device; Judge whether first serial data contains specific markers; If first serial data contains specific markers, at least a portion that then transmits this first serial data is to this chip; Transmit a plurality of reading command in order to storage device, till the main frame self-storing mechanism receives first response message, wherein first response message is that chip produces because of at least a portion that receives first serial data, and a plurality of reading command is set to the data that read in order on a plurality of logical block addresses from nonvolatile memory; And after storage device receives one of them reading command of a plurality of reading command, transmit second response message to main frame from storage device.
The present invention proposes a kind of serial data and transmits dispatching system, its be applicable to main frame and have nonvolatile memory with the storage device of chip between the serial data transmission.This serial data transmits dispatching system and comprises application program and controller.Application program is installed on the main frame and in order to the operation storage device.Controller is arranged in the storage device, and is electrically connected to nonvolatile memory and chip.Wherein application program can transmit to write and instruct to controller, writes to instruct to be set to write first serial data to storage device.Controller can judge whether first serial data contains specific markers, and if first serial data contains specific markers, then controller can transmit at least a portion of first serial data to this chip.Application program can transmit a plurality of reading command in order to storage device, till slave controller receives first response message, wherein first response message is that chip produces because of at least a portion that receives first serial data, and a plurality of reading command is set to the data that read in order on a plurality of logical block addresses from nonvolatile memory.After controller received one of them reading command of a plurality of reading command, controller can transmit second response message to application program.
The present invention proposes a kind of controller, and it is applicable to the storage device with nonvolatile memory and chip.This controller comprises microprocessing unit, memory interface and memory buffer.Above-mentioned microprocessing unit is in order to the overall operation of control controller, and above-mentioned memory interface is in order to the access nonvolatile memory, and above-mentioned memory buffer is in order to storage data temporarily.Wherein microprocessing unit can judge whether first serial data from main frame contains specific markers, and if first serial data contains specific markers, then microprocessing unit can then transmit at least a portion of first serial data to this chip.After at least a portion of first serial data is transferred into chip and before microprocessing unit receives first response message that chip produces, microprocessing unit can transmit second response message in order to main frame, with a plurality of reading command of response from main frame, wherein first response message is that chip produces because of at least a portion that receives first serial data.After microprocessing unit received first response message, microprocessing unit can be sent to main frame with first response message.
In one embodiment of this invention, the data on above-mentioned a plurality of logical block addresses belong to single specific file.
In one embodiment of this invention, above-mentioned serial data transmits allocating method and also comprises and judge whether single specific file is present in the nonvolatile memory; And if single specific file is not present in the nonvolatile memory as yet, then in nonvolatile memory, set up single specific file.
In one embodiment of this invention, the data on above-mentioned a plurality of logical block addresses belong to a plurality of specific files.
In one embodiment of this invention, above-mentioned serial data transmission allocating method also comprises: judge whether a plurality of specific files are present in the nonvolatile memory; And if any one specific file of a plurality of specific files is not present in the nonvolatile memory as yet, then in nonvolatile memory, set up also still unfounded specific file.
In one embodiment of this invention, each recorded data of above-mentioned second response message is all zero.
In one embodiment of this invention, above-mentioned serial data transmits allocating method and also comprises: if first serial data does not contain specific markers, then according to writing the address that instruction is assigned, first serial data is write to nonvolatile memory.
In one embodiment of this invention, above-mentioned serial data transmission allocating method also comprises: judge whether any is set to the data that read on a plurality of logical block addresses from the reading command that main frame is sent to storage device; And for arbitrary reading command, if reading command is not to be set to the data that read on a plurality of logical block addresses, then corresponding data are read in the address of assigning according to reading command from nonvolatile memory.
In one embodiment of this invention, above-mentioned main frame comprises high-speed cache, and all instructions all can be passed through high-speed cache with the transmission of data between main frame and the storage device.
In one embodiment of this invention, the summation of the data on above-mentioned a plurality of logical block addresses is more than or equal to the capacity of high-speed cache.
In one embodiment of this invention, above-mentioned a plurality of reading command is set to the data that read equal length in order from a plurality of logical block addresses.
In one embodiment of this invention, above-mentioned serial data transmits allocating method and also comprises: to be one be not zero serial data entirely if one of them reading command that receives above-mentioned a plurality of reading command because of response is back to the response message of this main frame, judges that then this is not that zero serial data is the first above-mentioned response message entirely.
In one embodiment of this invention, said storage unit in fact not storage data produce because of one of them reading command that response receives above-mentioned a plurality of reading command and above-mentioned second response message is a storage device in above-mentioned a plurality of logical block addresses.
In one embodiment of this invention, said chip is intelligent card chip, radio-frequency (RF) identification chip, wireless transmission chip or multimedia control chip.
In one embodiment of this invention, said storage unit is SD storage card or MMC storage card.
In one embodiment of this invention, said chip is compatible with ISO 7816 standards or ISO 14443 standards.
In one embodiment of this invention, above-mentioned nonvolatile memory is individual layer storage unit (SingleLevel Ce11, SLC) anti-(NAND) flash memory or multilayer storage unit (Multi Level Cell, MLC) anti-(NAND) flash memory that reaches of reaching.
In one embodiment of this invention, at least a portion of above-mentioned first serial data is instruction-Application Protocol Data Unit (Command-Application Protocol Data Unit, C-APDU), and first response message be response-Application Protocol Data Unit (Response-ApplicationProtocol Data Unit, R-APDU).
The present invention desires to be passed in the serial data of chip because of specific markers is added to, so can judge whether this serial data is the serial data that will be sent to chip by differentiating in the serial data whether this mark is arranged.In addition, during the response message of waiting for chip, the reading command of the data on the certain logic block address is read in execution from nonvolatile memory, and the default serial data (being all zero serial data) of passback as all, and when chip produces response message, the response message (position is not zero serial data entirely) that returns chip again and produced.Thus, can judge not only whether the serial data that is returned is the response message of this chip, and the response message that chip produced also can inerrably be received.In addition, because during the response message of waiting for chip, a plurality of reading command can be performed, from nonvolatile memory, to read the data on the different certain logic block address, so under the stored caching data of high-speed cache can be little by little by the new situation that caching data replaced, stored response data string is understood continuous updating and is possessed latest data in the high-speed cache, give application program so can avoid high-speed cache to transmit wrong response message, and make that the response message that chip produced can inerrably be returned.
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the functional block diagram of the main frame of known collocation storage card.
Fig. 2 transmits the functional block diagram of dispatching system for the serial data that illustrates according to first embodiment of the invention.
Fig. 3 is the functional block diagram of main frame among Fig. 2.
Process flow diagram when Fig. 4 operates for illustrate main frame according to first embodiment of the invention.
Process flow diagram when Fig. 5 operates for illustrate storage device according to first embodiment of the invention.
Fig. 6 is the data flow diagram of the first embodiment of the invention that illustrates according to Fig. 4 and Fig. 5.
The framework of the serial data that Fig. 7 illustrates in one embodiment of the invention to be adopted.
Process flow diagram when Fig. 8 operates for illustrate main frame according to second embodiment of the invention.
Process flow diagram when Fig. 9 operates for illustrate storage device according to second embodiment of the invention.
Figure 10 is the data flow diagram of the first embodiment of the invention that illustrates according to Fig. 8 and Fig. 9.
[main element label declaration]
10,200: main frame
12: storage card
14,212: high-speed cache
16: flash memory
18,140: intelligent card chip
100: storage device
110: controller
110a: microprocessing unit
110b: flash interface
110c: memory buffer
120: the bus connecting interface
130: nonvolatile memory
202: operating system
204: file system
206: application program
208: the standard card driver
210: card controller
S401, S403, S405, S407, S409, S411, S413, S415, S417, S501, S503, S505, S507, S509, S511, S513, S515, S517, S521, S405 ', S407 ', S413 ', S415 ', S501 ', S513 ': data transmit the step of dispatcher
700: serial data
702: specific markers
704: instruction-Application Protocol Data Unit (C-APDU)
Embodiment
The invention provides a kind of serial data and transmit allocating method, system and controller thereof, its be applicable to main frame and have nonvolatile memory with the storage device of chip between the serial data transmission.Said system comprises application program and controller, and application program and controller are to be arranged on main frame and storage device respectively.In addition, specific markers can be injected towards by main frame and be sent in the serial data of storage device, and makes that serial data is able to be assigned to chip by writing instruction.Afterwards, by carrying out a plurality of reading command, the response message that chip produced can inerrably be received.Below will and cooperate appended graphic the present invention of detailed description in detail with several exemplary embodiment.But it must be appreciated, these a little exemplary embodiment and unrestricted the present invention, for instance, serial data provided by the present invention transmits allocating method, system and controller thereof, in the application that can be applicable to combined with intelligent card and flash memory, in also can be applicable to other chip in addition and combining of flash memory being used, inerrably to transmit the response message of chip, and said chip can be radio-frequency (RF) identification (RadioFrequency Identification, RFID) chip, wireless transmission chip (as: Bluetooth chip) or a multimedia control chip (as: digital recording chip).
[first embodiment]
Please refer to Fig. 2, Fig. 2 is the summary calcspar that transmits dispatching system according to the serial data that first embodiment of the invention illustrates.Serial data transmits dispatching system and comprises application program 206 and controller 110.Application program 206 is mounted on the main frame 200, and controller 110 is arranged on the storage device 100.Usually storage device 100 can use with main frame 200, so that main frame 200 can write to data storage device 100 or reading of data from storage device 100.Particularly, storage device 100 also comprises the intelligent card chip 140 in order to functions such as nonvolatile memory 130 that stores general data and execution safety verifications, and the data that application program 206 and controller 110 can be carried out according to the embodiment of the invention transmit allocating method, to transfer a message to intelligent card chip 140 and inerrably to return the response message of intelligent card chip 140 to main frame 200.Main frame 200 comprises high-speed cache 212 in addition, in order to the temporary once used recently data of main frame 200, to promote the data processing speed of main frame 200 integral body.
The instruction that microprocessing unit 110a meeting executive utility 206 is sent, and each element in the tuning controller 100 is with the overall operation of control controller 110.
In addition, though be not illustrated in the present embodiment, controller 110 can also comprise the general common functional module of flash memory such as error correction module and power management module.
In the present embodiment, storage device 100 is secure digital (secure digital, SD) storage card.But it must be appreciated that storage device 100 can also be multimedia card (Multi Media Card, MMC) storage card or other a storage card in another embodiment of the present invention.
Application program 206 is in order to operation storage device 100, transmits allocating method with the data of finishing according to the embodiment of the invention.In addition, it must be appreciated that main frame 200 also comprises the main frame desire and is connected the required general utility functions that possess with storage device 100.For example, comprise operating system 202, file system 204, standard card driver 208 and card controller 210 (as shown in Figure 3) on the main frame 200, wherein main frame 200 can be finished with storage device 100 via standard card driver 208 and card controller 210 and be connected, and operates with 206 pairs of storage devices 100 of application program by operating system 202, file system 204.In the present embodiment, standard card driver 208 can be successively through card controller 210 and high-speed cache 212, the data and instruction is sent to storage device 100, and in another embodiment of the present invention, standard card driver 208 transmission data and instructions to the path of storage device 100 then is to pass through card controller 210 again through high-speed cache 212 earlier.In the present embodiment, all instructions all can be passed through high-speed cache 212 with the transmission of data between main frame 200 and the storage device 100.Yet, must notice that in another embodiment of the present invention, instruction can be walked around high-speed cache with the transmission of data between main frame 200 and the storage device 100, or main frame 200 itself can comprise any high-speed cache, also or main frame 200 can carry out the instruction of removing high-speed cache.In other words, serial data provided by the present invention transmit allocating method, system and controller thereof not with form, the operating mode of high-speed cache, whether exist or and other original paper between connected mode exceed.In addition, above-mentioned main frame 200 can be personal computer, mobile phone, notebook computer, PDA (Personal Digital Assistant) (PDA) .... etc.
The base this, at main frame 200 to above-mentioned when containing nonvolatile memory 130 and operating with the storage device 100 of the framework of intelligent card chip 140, operation according to the controller 110 fit applications programs 206 of the embodiment of the invention can correctly be sent to intelligent card chip 140 with data or instruction, and inerrably the response message of intelligent card chip 140 is passed to main frame 200.Below will cooperate Fig. 4 to Fig. 6 to describe the flow process of performed data transmission dispatcher between controller 110 and the main frame 200 in detail.Wherein, Fig. 4 is the process flow diagram when illustrating main frame 200 running according to first embodiment of the invention, and Fig. 5 is the process flow diagram when illustrating storage device 100 runnings according to first embodiment of the invention, and Fig. 6 is the data flow diagram that illustrates according to Fig. 4 and Fig. 5.
Please earlier with reference to Fig. 4, transmit data or instruct to the controller 110 of storage device 100 in the application program 206 of main frame 200, application program 206 can send institute's tendency to develop data or instruction and specific markers to merge, with formation serial data (step S401).As shown in Figure 7, in the present embodiment, application program 206 is sent to the data of controller 110 or instructs 704 to be instruction-Application Protocol Data Unit (Command-Application Protocol Data Unit, C-APDU), and after C-APDU 704 and specific markers 702 merging, can form serial data 700.In the present embodiment, specific markers 702 is positioned at several most significant character (MSC)s of serial data 700 (Most Significant Bit MSB) is formed on the front end of C-APDU 704.Yet, must note, the position of specific markers 702 in serial data 700 be not as limit, for example: in another embodiment of the present invention, can pass through scrambler, each position of specific markers 702 is dispersed among the serial data 700, from serial data 700, is capturing specific markers 702 by identical scrambler afterwards.
After serial data 700 formed, application program 206 can be sent to serial data 700 controller 110 (step S403) of storage device 100 by writing instruction.That is application program 206 can transmit to write and instruct to storage device 100, and this to write instruction be to be set to write serial data 700 to storage device 100.
After serial data 700 was sent to controller 110, application program 206 can transmit the controller 110 of a plurality of reading command to storage device 100 in order, till this main frame self-storing mechanism 100 receives the response message that intelligent card chip 140 produced.Wherein, above-mentioned a plurality of reading command are set to a plurality of logical block addresses (Logical Block Address, the LBA) A that reads single specific file in order from nonvolatile memory 130
1To A
NOn data.Please refer to Fig. 4, before a plurality of reading command were sent to storage device 100, application program 206 can be set at initial logical block addresses A with the present address A that reads
1(step S405).Afterwards, application program 206 can transmit reading command to storage device 100 (step S407), and this reading command is set to reads the data (i.e. the data of [A:A+511]) of logical block addresses A to (A+511) from nonvolatile memory 130.Must explanation, in the present embodiment, after controller 110 received the reading command that application program 206 exported, controller 110 can be judged earlier whether this reading command is set to and read above-mentioned a plurality of logical block addresses A
1To A
NOn data, and if this reading command be set to and read above-mentioned a plurality of logical block addresses A
1To A
NOn data, reading of data on can't be from nonvolatile memory 130 when the practical operation corresponding logical block addresses of controller 110, but by directly producing 512 byte lengths in the buffer and being that main frame 200 is given in zero data and passback entirely, to reduce because of the reading of data consumed time.In addition, in another embodiment of the present invention, above-mentioned 512 byte lengths and be that zero data microprocessing unit 110a directly reads from nonvolatile memory 130 entirely, wherein a plurality of logical block addresses A of nonvolatile memory 130
1To A
NThe stored data of last reality can be zero entirely.
Refer again to Fig. 4, when application program 206 transmits reading command to storage device 100, promptly can wait for and receive the serial data (step S409) that storage device 100 is returned, and the serial data of above-mentioned passback to be microprocessing unit 110a produce for response has received this reading command.Afterwards, application program 206 can judge whether each recorded data of passback serial data all is zero (step S411).If each recorded data of passback serial data all is zero, represent that then the microprocessing unit 110a of controller 110 does not receive the response message of intelligent card chip 140 as yet; And it is relative, if each recorded data of passback serial data is not zero entirely, represent that then the microprocessing unit 110a of controller 110 has received the response message of intelligent card chip 140, application program 206 promptly can be considered as received passback serial data the response message (step S417) of intelligent card chip 140.When each recorded data of passback serial data all was zero, application program 206 can be judged again and present read address A and whether equal last logical block addresses A
N(step S413).If the present address A that reads equals last logical block addresses A
N, represent that then application program 206 had transmitted N reading command to storage device 100, this moment, application program 206 promptly can be set at initial logical block addresses A with the present address A that reads again
1(step S405), wherein above-mentioned N reading command is to be set to a plurality of logical block addresses A that read single specific file from nonvolatile memory 130
1To A
NOn data.Yet, if present reading address A and be not equal to last logical block addresses A
N, then application program 206 can add preset data length (step S415) with the present address A that reads, and in the present embodiment, this preset data length is 512.Therefore, in the present embodiment, a plurality of reading command that application program 206 is produced are to be set in order from a plurality of logical block addresses A
1To A
NRead equal length (promptly 512 s') data.In addition, in order to simplify the operation of application program 206, in another embodiment of the present invention, application program 206 can be according to initial logical block addresses A
1And the size of above-mentioned single specific file, obtain all logical block addresses A
1To A
N, second logical block addresses A for example
2Promptly equal (A
1+ 512), last logical block addresses A
NEqual (A
1+ 512 * (N-1)), and the size of this single specific file is to equal (512 * N).
In addition, in other embodiments of the invention, also can utilize the table of comparisons to obtain all logical block addresses A
1To A
NInformation, wherein in one embodiment, the above-mentioned table of comparisons can be listed all logical block addresses that belong to this specific file; And in another embodiment, the table of comparisons is then only listed two logical block addresses of the head end and the tail end of this specific file.Wherein, because logical block addresses is a unit with section (sector) usually, and the data length of each section is 512 bytes usually, so can try to achieve all logical block addresses A by two logical block addresses of above-mentioned head end and tail end
1To A
NThus, when the logical block addresses that is write down when address that microprocessing unit 110a judges in the reading command to be assigned and this table of comparisons is coincide, if intelligent card chip 140 does not produce response message as yet, it is that zero serial data is to application program 206 entirely that microprocessing unit 110a promptly returns the position.In addition, in other embodiments of the invention, storage device 100 in fact not storage data in above-mentioned a plurality of logical block addresses A
1To A
N, that is above-mentioned specific file can be virtual, and belongs to above-mentioned a plurality of logical block addresses A when microprocessing unit 110a judges the address that reading command assigns
1To A
NThe time, microprocessing unit 110a then directly produces response message and the response message string is delivered to main frame 200, and dispenses the program of reading non-volatile storage 130.Must illustrate that in addition the preset data length among the present invention is not exceeded with 512 bytes, above-mentioned preset data length can be other numerical value, as 4K, and 8K.In addition, in the present embodiment, because of each reading command is to be set to the data that read preset data length, so this preset data length can be adjusted at different demands, for example this preset data length can be dwindled, so that the data volume of the serial data that the microprocessing unit 110a of each controller 110 returns for the response reading command can reduce, and then can shorten the time of microprocessing unit 110a response, and promote the usefulness of controller 110.
Flow process when operating with respect to the main frame 200 that Fig. 4 illustrated, the operation workflow of storage device 100 then can be with reference to figure 5.At first, when storage device 100 came into operation, the microprocessing unit 110a of controller 110 is the initial logical block addresses A of the above-mentioned single specific file of record earlier
1And size (step S501), with usefulness as the follow-up reading command that is produced than application programs 206.Yet, in another embodiment of the present invention, at record start logical block addresses A
1And before the size of single specific file, microprocessing unit 110a can judge earlier whether this single specific file is present in this nonvolatile memory, if and above-mentioned single specific file is not present in the nonvolatile memory 130 as yet, then microprocessing unit 110a can set up above-mentioned single specific file in nonvolatile memory 130.
As initial logical block addresses A
1After being recorded with the size of single specific file, controller 110 can begin to receive that application program 206 exported writes instruction (step S503), wherein this write the instruction be to be set to write first serial data to storage device 100, and this first serial data can be as shown in Figure 7 serial data 700 or other serial data.When controller 110 receive write instruction after, can judge promptly whether this first serial data contains specific markers 702 (step S505) as shown in Figure 7.If first serial data does not contain specific markers 702, then the microprocessing unit 110a of controller 110 can write to nonvolatile memory 130 (step S507) with first serial data according to writing the address that instruction is assigned; Relative, if first serial data contains specific markers 702, then the microprocessing unit 110a of controller 110 can remove specific markers 702 from first serial data, producing second serial data (C-APDU 704 as shown in Figure 7), and second serial data is sent to intelligent card chip 140 (step S509).Thus, by detecting whether contain specific markers 702 in first serial data, the microprocessing unit 110a of controller 110 can should be sent to nonvolatile memory 130 or be sent to intelligent card chip 140 by the judgment data string.Must illustrate that in addition in another embodiment of the present invention, the second above-mentioned serial data is the first above-mentioned serial data.In other words, microprocessing unit 110a can not remove specific markers 702 from first serial data, but first serial data directly is transferred to intelligent card chip 140.Afterwards, intelligent card chip 140 picks out specific markers 702 and C-APDU 704 from the first received serial data again.
After second serial data is sent to intelligent card chip 140, the microprocessing unit 110a of controller 110 promptly can wait for the reading command (step S511) that the application program 206 of reception main frame 200 is sent, and wherein above-mentioned reading command is including but not limited to the reading command that step S407 transmitted of application program 206 in Fig. 4.Afterwards, the microprocessing unit 110a of controller 110 can judge whether the address that the reading command that received is assigned belongs to above-mentioned single specific file (step S513), that is microprocessing unit 110a can judge whether the reading command that is received is set to and reads above-mentioned a plurality of logical block addresses A
1To A
NOn data.If the address that above-mentioned reading command is assigned not is to belong to this single specific file, then microprocessing unit 110a can read corresponding data (step S515) according to the address that reading command is assigned from nonvolatile memory 130, and data are sent to application program 206; Relatively, if the address that above-mentioned reading command is assigned belongs to above-mentioned single specific file, then microprocessing unit 110a can judge whether to receive the response message (step S517) of intelligent card chip 140 again, and in the present embodiment, this response message is that intelligent card chip 140 produces because of receiving the second above-mentioned serial data, and be response-Application Protocol Data Unit (Response-Application Protocol Data Unit, R-APDU), can be called as first response message.If microprocessing unit 110a does not receive the response message of intelligent card chip 140 as yet, the microprocessing unit 110a of controller 110 then can return all and be all zero serial data (being equivalent to second response message) to application program 206 (step S519), to respond received reading command, continue to wait for the next reading command of application program 206 afterwards again; Yet if microprocessing unit 110a has received the response message of intelligent card chip 140, microprocessing unit 110a can be back to application program 206 (step S521) with the response message (position is not zero serial data entirely) of intelligent card chip 140.Thus, be all zero serial data, can make application program 2 06 be judged whether the serial data that microprocessing unit 110a returned is the response message of intelligent card chip 140 by in time transmitting all.
Indulge the above, the serial data transport process between main frame 200 and the storage device 100 generally can be divided into convey program and wait-for-response messaging program, as shown in Figure 6.During carrying out convey program, main frame 200 can transmit to write earlier and instruct to controller 110 (the step S401 and the S403 that are equivalent to Fig. 4), and controller 110 can check the serial data that is received whether to contain specific markers (the step S505 that is equivalent to Fig. 5) afterwards.If the serial data that is received contains specific markers, controller 110 will be sent to the C-APDU in the serial data intelligent card chip 140 (the step S509 that is equivalent to Fig. 5).In addition, carry out above-mentioned wait-for-response messaging program during, if intelligent card chip 140 does not produce response message (for example R-APDU) as yet, main frame 200 can transmit a plurality of reading command in order to controller 110 and receive the serial data (the step S405 to S415 that is equivalent to Fig. 4) that controller 110 is returned, the address that controller 110 then can compare institute's assignment in the reading command whether with logical block addresses A
1To A
NCoincideing and returning all is that zero serial data is to main frame 200 (the step S511 to S519 that is equivalent to Fig. 5) entirely.At last, after controller 110 received the response message that intelligent card chip 140 produced, 110 of controllers can be sent to the response message that intelligent card chip 140 is produced main frame 200 (the step S521 that is equivalent to Fig. 5).
In addition, in the present embodiment, be that the storer that instruction assigns of writing with Fig. 4 step S403 writes the storer that reading command that the address is configured to be different from the step S407 of Fig. 4 assigns and reads the address.Therefore, when main frame 200 transmits reading command to controller 110, the high-speed cache 212 of Fig. 2 can't be desired to write the serial data of storage device 100 and is considered as caching data and is back to main frame 200 before writing instruction.In addition, in the present embodiment, the data volume of above-mentioned single specific file is more than or equal to the capacity of high-speed cache 212, and the reading command that is transmitted because of each main frame is the data that read on the Different Logic block address, so under the stored caching data of high-speed cache 212 can be little by little by the new situation that caching data replaced, stored response data string is understood continuous updating and is possessed latest data in the high-speed cache 212, gives application program 206 so can avoid high-speed cache 212 to transmit wrong response message.Therefore, the response message that produced of intelligent card chip 140 can inerrably be back to main frame 200.
[second embodiment]
Among above-mentioned first embodiment, a plurality of reading command that main frame 200 is sent to storage device 100 are to be set to a plurality of logical block addresses A that read single specific file
1To A
NOn data.Relatively, in the second embodiment of the present invention, a plurality of reading command that main frame 200 is sent to storage device 100 are to be set to read a plurality of specific file F
1To F
NA plurality of logical block addresses B
1To B
NOn data, wherein above-mentioned a plurality of specific file F
1To F
NBe to be stored in the nonvolatile memory 130.
Please refer to Fig. 8 to Figure 10, Fig. 8 is the process flow diagram when illustrating main frame 200 runnings according to second embodiment of the invention, Fig. 9 is the process flow diagram when illustrating storage device 100 running according to second embodiment of the invention, and Figure 10 is the data flow diagram that illustrates according to Fig. 8 and Fig. 9.
The flow process that the flow process that Fig. 8 illustrated and Fig. 4 are illustrated is very similar, difference wherein is that step S405, S407, S413 and the S415 among Fig. 4 replaced by the step S405 ' among Fig. 8, S407 ', S413 ' and S415 ' respectively, and is then identical and repeat no more as for other step S401, S403, S409, S411 and S417.In step S405 ', application program 206 can be with file destination F
tBe set to first specific file F
1Afterwards, application program 206 can transmit reading command to storage device 100 (step S407 '), and this reading command is set to reads file destination F from nonvolatile memory 130
tIn addition, in step S413 ', application program 206 can be judged present file destination F
tWhether be last specific file F
NIf present file destination F
tBe last specific file F
N, represent that then application program 206 had transmitted N reading command to storage device 100, this moment, application program 206 promptly can be again with present file destination F
tBe set at first specific file F
1(step S405 ').Yet, if present file destination F
tNot last specific file F
N, then application program 206 can be with file destination F
tBe set at a specific file (step S415 '), be about to variable t and add up one.Annotated in addition, in another embodiment of the present invention, above-mentioned a plurality of specific file F
1To F
NInitial logical block addresses can be respectively B
1To B
N(be similar to the logical block addresses A among first embodiment
1To A
N).
The flow process that is illustrated as for flow process that Fig. 9 illustrated and Fig. 5 is very similar, and difference wherein is that step S501 and the S513 among Fig. 5 replaced by step S501 ' among Fig. 8 and S513 ' respectively, and is then identical and repeat no more as for other step.In step S501 ', the microprocessing unit 110a of controller 110 is the above-mentioned a plurality of specific file F of record earlier
1To F
NLogical block addresses B
1To B
NIn step S513 ', the microprocessing unit 110a of controller 110 can judge whether the address of its appointment of reading command that is received belongs to above-mentioned a plurality of specific file F
1To F
N, that is microprocessing unit 110a can judge whether the reading command that is received is set to and reads above-mentioned a plurality of logical block addresses B
1To B
NOn data.
The flow process that is illustrated as for flow process that Figure 10 illustrated and Fig. 6 is very similar, and difference is, when carry out the wait-for-response messaging program during, the reading command that main frame 200 is sent to controller 110 is to be set to read above-mentioned a plurality of Te and Ding File F
1To F
NIn addition, before controller 110 does not receive the response message that intelligent card chip 140 produced as yet, controller 110 relatively in the reading command address of institute's assignment whether with logical block addresses B
1To B
NCoincide.
Additional disclosure in addition is in another embodiment of the present invention, at the specific file F of record
1To F
NLogical block addresses B
1To B
NBefore, microprocessing unit 110a can judge above-mentioned a plurality of specific file F earlier
1To F
NWhether be present in the nonvolatile memory 130, and if above-mentioned a plurality of specific file F
1To F
NAny one specific file be not present in as yet in the nonvolatile memory 130, then microprocessing unit 110a can set up also still unfounded specific file in nonvolatile memory 130.
In sum, the present invention desires to be passed in the serial data of chip because of main frame is added to specific markers, so controller can judge whether this serial data is the serial data that will be sent to certain certain chip by differentiating in the serial data whether this mark is arranged.In addition, during the response message of waiting for this chip, the reading command of the data on the certain logic block address is read in execution, and the default serial data (being all zero serial data) of passback as all, and when chip produces response message, the response message (position is not zero serial data entirely) that returns chip again and produced.Thus, can judge not only whether the serial data that is returned is the response message of this chip, and the response message that chip produced can be received inerrably also.In addition, because during the response message of waiting for chip, a plurality of reading command can be performed, so under the stored caching data of high-speed cache can be little by little by the new situation that caching data replaced, stored response data string is understood continuous updating and is possessed latest data in the high-speed cache, give application program so can avoid high-speed cache to transmit wrong response message, the response message that chip is produced can inerrably be returned.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (25)
1. a serial data transmits allocating method, and it is applicable to that from main frame Data transmission string to the storage device with nonvolatile memory and chip, this serial data transmission allocating method comprises:
Transmission writes instruction to this storage device, and this writes to instruct to be set to and writes first serial data to this storage device;
Judge whether this first serial data contains specific markers;
If this first serial data contains this specific markers, at least a portion that then transmits this first serial data is to this chip;
Transmit a plurality of reading command in order to this storage device, up to this main frame till this storage device receives first response message, wherein this first response message produces because of at least a portion that receives this first serial data for this chip, and these a plurality of reading command are set to the data that read on a plurality of logical block addresses; And
After this storage device receives one of them reading command of these a plurality of reading command, transmit second response message to this main frame from this storage device.
2. serial data according to claim 1 transmits allocating method, and wherein the data on these a plurality of logical block addresses belong to single specific file.
3. serial data according to claim 2 transmits allocating method, also comprises:
Judge whether this single specific file is present in this nonvolatile memory; And
If this single specific file is not present in this nonvolatile memory as yet, then in this nonvolatile memory, set up this single specific file.
4. serial data according to claim 1 transmits allocating method, and wherein the data on these a plurality of logical block addresses belong to a plurality of specific files.
5. serial data according to claim 4 transmits allocating method, also comprises:
Judge whether these a plurality of specific files are present in this nonvolatile memory; And
If the specific file of any one of these a plurality of specific files is not present in this nonvolatile memory as yet, then in this nonvolatile memory, set up also still unfounded specific file.
6. serial data according to claim 1 transmits allocating method, and wherein each recorded data of this second response message is all zero.
7. serial data according to claim 1 transmits allocating method, also comprises:
If this first serial data does not contain this specific markers, then write the address that instruction is assigned according to this, this first serial data is write to this nonvolatile memory.
8. serial data according to claim 1 transmits allocating method, also comprises:
Judge whether any is set to the data that read on these a plurality of logical block addresses from the reading command that this main frame is sent to this storage device; And
For arbitrary reading command, if this reading command is not to be set to the data that read on these a plurality of logical block addresses, then corresponding data are read in the address of assigning according to this reading command from this nonvolatile memory.
9. serial data according to claim 1 transmits allocating method, and wherein this main frame comprises high-speed cache, and all instructions all can be passed through this high-speed cache with the transmission of data between this main frame and this storage device.
10. serial data according to claim 9 transmits allocating method, and wherein the summation of the data on these a plurality of logical block addresses is more than or equal to the capacity of this high-speed cache.
11. serial data according to claim 1 transmits allocating method, wherein these a plurality of reading command are set to the data that read equal length in order from these a plurality of logical block addresses.
12. serial data according to claim 1 transmits allocating method, also comprises:
To be one be not zero serial data entirely if one of them reading command that receives these a plurality of reading command because of response is back to the response message of this main frame, judges that then this is not that zero serial data is this first response message entirely.
13. serial data according to claim 1 transmits allocating method, wherein in fact storage data is not in these a plurality of logical block addresses for this storage device, and this second response message produces because of one of them reading command that response receives these a plurality of reading command for this storage device.
14. a serial data transmits dispatching system, its be applicable to main frame and have nonvolatile memory with the storage device of chip between serial data transmit, this serial data transmission dispatching system comprises:
Application program is installed on this main frame and in order to operate this storage device; And
Controller is arranged in this storage device, and is electrically connected to this nonvolatile memory and this chip;
Wherein this application program can transmit and write instruction to this controller, and this writes to instruct to be set to and writes first serial data to this storage device;
Wherein this controller can judge whether this first serial data contains specific markers, and if this first serial data contains this specific markers, then this controller can transmit at least a portion of this first serial data to this chip;
Wherein this application program can transmit a plurality of reading command in order to this storage device, till receiving first response message from this controller, wherein this first response message produces because of at least a portion that receives this first serial data for this chip, and these a plurality of reading command are set to the data that read on a plurality of logical block addresses;
Wherein after this controller received one of them reading command of these a plurality of reading command, this controller can transmit second response message to this application program.
15. serial data according to claim 14 transmits dispatching system, wherein the data on these a plurality of logical block addresses belong to single specific file.
16. serial data according to claim 15 transmits dispatching system, wherein this controller can judge whether this single specific file is present in this nonvolatile memory, if and this single specific file is not present in this nonvolatile memory as yet, then this controller can be set up this single specific file in this nonvolatile memory.
17. a controller, it is applicable to the storage device with nonvolatile memory and chip, and this controller comprises:
Microprocessing unit is in order to control the overall operation of this controller;
Memory interface is in order to this nonvolatile memory of access; And
Memory buffer is in order to storage data temporarily;
Wherein this microprocessing unit can judge whether first serial data from main frame contains specific markers, and if this first serial data contains this specific markers, then this microprocessing unit can transmit at least a portion of this first serial data to this chip;
Wherein after at least a portion of this first serial data is transferred into this chip and before this microprocessing unit receives first response message that this chip produces, this microprocessing unit can transmit second response message in order to this main frame, with a plurality of reading command of response from this main frame, wherein this first response message produces because of at least a portion that receives this first serial data for this chip;
Wherein after this microprocessing unit received this first response message, this microprocessing unit can be sent to this main frame with this first response message.
18. controller according to claim 17, wherein these a plurality of reading command are set to the data that read on a plurality of logical block addresses, and the data on these a plurality of logical block addresses belong to single specific file.
19. controller according to claim 18, wherein this microprocessing unit can judge whether this single specific file is present in this nonvolatile memory, if and this single specific file is not present in this nonvolatile memory as yet, then this microprocessing unit can be set up this single specific file in this nonvolatile memory.
20. controller according to claim 17, wherein these a plurality of reading command are set to the data that read in order on a plurality of logical block addresses from this nonvolatile memory, and the data on these a plurality of logical block addresses belong to a plurality of specific files.
21. controller according to claim 20, wherein this microprocessing unit can judge whether these a plurality of specific files are present in this nonvolatile memory, if and any one specific file of these a plurality of specific files is not present in this nonvolatile memory as yet, then this microprocessing unit can be set up also still unfounded specific file in this nonvolatile memory.
22. controller according to claim 17, wherein each recorded data of this second response message is all zero.
23. controller according to claim 17, if wherein this first serial data does not contain this specific markers, then this microprocessing unit can write to this nonvolatile memory with this first serial data.
24. controller according to claim 17, wherein this microprocessing unit can judge that any is sent to the reading command of this storage device from this main frame, whether be set to the data that read on a plurality of logical block addresses, and for arbitrary reading command, if this reading command is not to be set to the data that read on these a plurality of logical block addresses, then this microprocessing unit can read corresponding data according to the address that this reading command is assigned from this nonvolatile memory.
25. controller according to claim 17, wherein this main frame comprises high-speed cache, and all instructions all can be passed through this high-speed cache with the transmission of data between this main frame and this storage device.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102455879A (en) * | 2010-10-21 | 2012-05-16 | 群联电子股份有限公司 | Memory storage device, memory controller and method for automatically generating filled document |
| CN103425594A (en) * | 2012-05-23 | 2013-12-04 | 群联电子股份有限公司 | Data processing method, storage controller and storage storing device |
| CN109697017A (en) * | 2017-10-20 | 2019-04-30 | 上海宝存信息科技有限公司 | Data memory device and non-volatile formula memory operating method |
| CN110750303A (en) * | 2019-09-25 | 2020-02-04 | 支付宝(杭州)信息技术有限公司 | Pipelined instruction reading method and device based on FPGA |
| CN113534695A (en) * | 2020-04-17 | 2021-10-22 | 新唐科技股份有限公司 | Tandem amplification device and tandem system comprising same |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3663043B2 (en) * | 1997-12-25 | 2005-06-22 | 三洋電機株式会社 | Method for determining the end of writing in a microcomputer |
| CN2824145Y (en) * | 2005-08-05 | 2006-10-04 | 群联电子股份有限公司 | Memory card with ID identification |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102455879A (en) * | 2010-10-21 | 2012-05-16 | 群联电子股份有限公司 | Memory storage device, memory controller and method for automatically generating filled document |
| CN102455879B (en) * | 2010-10-21 | 2014-10-15 | 群联电子股份有限公司 | Memory storage device, memory controller and method for automatically generating filled document |
| CN103425594A (en) * | 2012-05-23 | 2013-12-04 | 群联电子股份有限公司 | Data processing method, storage controller and storage storing device |
| CN103425594B (en) * | 2012-05-23 | 2016-09-14 | 群联电子股份有限公司 | Data processing method, Memory Controller and memory storage apparatus |
| CN109697017A (en) * | 2017-10-20 | 2019-04-30 | 上海宝存信息科技有限公司 | Data memory device and non-volatile formula memory operating method |
| CN109697017B (en) * | 2017-10-20 | 2022-03-15 | 上海宝存信息科技有限公司 | Data storage device and non-volatile memory operation method |
| CN110750303A (en) * | 2019-09-25 | 2020-02-04 | 支付宝(杭州)信息技术有限公司 | Pipelined instruction reading method and device based on FPGA |
| CN113534695A (en) * | 2020-04-17 | 2021-10-22 | 新唐科技股份有限公司 | Tandem amplification device and tandem system comprising same |
| CN113534695B (en) * | 2020-04-17 | 2023-09-12 | 新唐科技股份有限公司 | Tandem type amplification device and tandem type system comprising same |
Also Published As
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| CN101609392B (en) | 2012-07-04 |
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