CN101788955A - Access method of flash data, storage system and control system thereof - Google Patents

Access method of flash data, storage system and control system thereof Download PDF

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CN101788955A
CN101788955A CN200910009872A CN200910009872A CN101788955A CN 101788955 A CN101788955 A CN 101788955A CN 200910009872 A CN200910009872 A CN 200910009872A CN 200910009872 A CN200910009872 A CN 200910009872A CN 101788955 A CN101788955 A CN 101788955A
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physical page
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CN101788955B (en
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朱健华
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Phison Electronics Corp
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Phison Electronics Corp
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Abstract

The invention discloses an access method of flash data, a storage system and a control system thereof, which are used for writing data in a plurality of physical page addresses of a plurality of physical blocks of a flash memory chip. The data access method comprises the steps of providing a plurality of logical page addresses of a host system and establishing a logical page-to-physical page mapping table and a physical page-to-logical page mapping table so as to record the mapping of logical page addresses and physical page addresses. The data access method also comprises the steps of writing data in physical page addresses when the host system writes data in the logical page addresses and updating the logical page-to-physical page mapping table and the physical page-to-logical page mapping table. The data access method also comprises the step of comparing the logical page-to-physical page mapping table with the physical page-to-logical page mapping table so as to determine invalid and valid physical page addresses of the written data.

Description

The access method of flash data and stocking system thereof and control system
Technical field
The invention relates to a kind of flash memory system and flash controller that is used for the data access method of flash memory and uses the method.
Background technology
Digital camera, mobile phone camera and MP3 are very rapid in growth over the years, make the consumer also increase rapidly the demand of Storage Media.Because flash memory (Flash Memory) has that data are non-volatile, power saving, volume is little and the characteristic of no mechanical structure etc., suitable portable applications, the most suitable being used on the battery-powered product of this class Portable.Solid state hard disc is exactly a kind of with the storage device of nand flash memory as Storage Media.
In general, the flash chip of flash memory system (chip) can be divided into a plurality of physical blocks, and wherein physical blocks more is divided into a plurality of page or leaf, and physical blocks be the unit of erasing and the page or leaf of flash memory is the unit of writing of flash memory.Because when the mnemon of sequencing flash memory, only can the fill order to sequencing (that is, only the value of mnemon can be turned to 0 by 1 program), therefore can't be (promptly to the page or leaf of sequencing, the page or leaf that has legacy data) directly write, but sequencing again after must earlier this page or leaf being erased.Particularly, because erasing of flash memory be to be unit with the physical blocks, therefore the page or leaf that will have a legacy data when desire is carried out and is erased when operating, and must erase to the whole physical blocks under this page.Therefore, the writing mechanism of flash memory can be that carry out on the basis with the physical blocks traditionally.For example, in traditional wiring method, these a little physical blocks can be able to be defined as data field (data area) and spare area (spare area), wherein classify as and to store in the physical blocks of data field by writing the valid data that instruction writes, and the physical blocks in the spare area is the physical blocks in the replacement data district when writing instruction in execution.Specifically, when flash memory system receive host computer system writing the instruction and desire is write fashionable to the physical blocks of data field, flash memory system can from the spare area, extract physical blocks and will be in the data field effective legacy data in the physical blocks upgraded of desire write to the physical blocks of from the spare area, extracting with the new data of desiring to write and the physical blocks that will write new data is associated as the data field, and the physical blocks of data field is erased and is associated as the spare area originally.In order to allow the physical blocks of host computer system access successfully with the mode storage data of rotating, flash memory system can carry out access for host computer system by the configuration logic block, and wherein logical blocks is to dispose according to the size of physical blocks with one or more physical blocks.That is to say, flash memory system can be set up logical blocks-physical blocks mapping table (logical block-physical block mapping table), and the enantiomorphic relationship in this table between the physical blocks of record and renewal logical blocks and data field reflects rotating of physical blocks, so host computer system only need be carried out access and flash memory system can come the physical blocks of institute's mapping is read or write data practically according to logical blocks-physical blocks mapping table at providing logical blocks.
Therefore when host computer system was only upgraded a part of data in the logical blocks, above-mentioned data access method also must comprise the action of moving the effective legacy data in the physical blocks except the action that writes new data.Particularly, when the data updated amount is more little, cause required effective legacy data amount of moving more for a long time, the required time of finishing above-mentioned write activity can significantly increase.Particularly, the trend of computing machine development at present gradually with flash memory (promptly, solid state hard disc) as the Primary Hard Drive of computer system, simultaneous computer operating system has the characteristic of upgrading low volume data continually, so the writing speed of flash chip will have a strong impact on the operational paradigm of overall calculation machine system.Therefore, the data access method that needs development one cover can reduce data-moving is arranged, write the speed of data to flash memory with lifting.
Summary of the invention
The invention provides a kind of data access method, it can reduce the data-moving action when writing data to flash chip, and then promotes the writing speed of flash memory.
The invention provides a kind of controller system, it can reduce the data-moving action when writing data to flash chip, and then promotes the writing speed of flash memory.
The invention provides a kind of flash memory system, it can reduce the data-moving action when writing data, and then promotes the writing speed of flash memory.
The present invention proposes a kind of data access method, and it is to be carried out to write data in a plurality of physical page address (physical page address) of a plurality of physical blocks of at least one flash chip by a flash controller.This data access method comprises provides a plurality of logical page addresses of host computer system (logical page address), setting up logical page (LPAGE) changes physical page mapping table (logical page to physical page mapping table) writing down the physical page address of logical page address institute mapping respectively, and sets up physical page and change logical page (LPAGE) mapping table (physicalpage to logical page mapping table) to write down the logical page address of physical page address institute mapping respectively.This data access method also comprises: host computer system reception is from then on desired to write data and and is desired to write logical page address; Write this and desire to write data in a physical page address; Change at above-mentioned logical page (LPAGE) and to upgrade this in the physical page mapping table to desire to write logical page address be the physical page address that mapping writes these data; And above-mentioned physical page change upgrade in the logical page (LPAGE) mapping table write this physical page address of desiring to write data be mapping this desire to write logical page address.This data access method also comprises that the comparison logical page (LPAGE) changes physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table is judged invalid physical page address and effective physical page address among the physical page address of written data.
In one embodiment of this invention, above-mentioned data access method more comprises sets up the invalid page address count table of physical blocks writing down the number of physical page address invalid in each physical blocks, and is updated in the above-mentioned number of desiring to write physical page address invalid in the physical page address of the original mapping of logical page address in the invalid page address count table of this physical blocks.
In one embodiment of this invention, above-mentioned data access method more comprises sets up physical blocks active page address count table writing down in each physical blocks the effectively number of physical page address, and is updated in the above-mentioned physical page address of desiring to write the original mapping of logical page address the effectively number of physical page address in this physical blocks active page address count table.
In one embodiment of this invention, above-mentioned data access method comprises more whether number that judgement does not write those physical blocks of data is less than a no datat physical blocks and counts threshold value, wherein when the number of the physical blocks that does not write data is less than this no datat physical blocks and counts threshold value, then carry out the invalid data program of erasing, wherein this invalid data program of erasing comprises: select at least one first physical blocks according to the invalid page address count table of above-mentioned physical blocks among the physical blocks of written data; Never select at least one second physical blocks among writing the physical blocks of data; Data in the effective physical page address in this first physical blocks are copied in the physical page address that belongs to second physical blocks; Upgrade above-mentioned logical page (LPAGE) and change physical page mapping table, physical page commentaries on classics logical page (LPAGE) mapping table and the invalid page address count table of physical blocks; And this first physical blocks of erasing.
In one embodiment of this invention, wherein among the physical blocks of written data above-mentioned first physical blocks have the effective physical page of minimized number address.
In one embodiment of this invention, above-mentioned data access method more comprises sets up a no datat physical blocks admin table, does not write the physical blocks of data with record.
In one embodiment of this invention, this logical page (LPAGE) of above-mentioned comparison changes physical page mapping table and this physical page changes logical page (LPAGE) mapping table and judge that those invalid among those physical page addresses of written data physical page addresses and the effective step of those physical page addresses comprise: selection one waits to judge the physical page address among the physical page address; Change the logical page address that the inquiry of logical page (LPAGE) mapping table waits to judge the mapping of physical page address according to physical page; Change the physical page address of the logical page address mapping of physical page mapping table inquiry institute mapping according to logical page (LPAGE); Judge whether the physical page address of being inquired about is same as physical page to be measured address.If the physical page address of being inquired about in this judges is same as physical page to be measured address, then wait to judge the physical page address for effectively, and if the physical page address of being inquired about be different from physical page to be measured address, wait then to judge that the physical page address is invalid.
In one embodiment of this invention, above-mentioned data access method more comprises according to the invalid page address count table of above-mentioned physical blocks judges among the physical blocks of written data whether the ratio that invalid physical page address at least one first physical blocks accounts for its all physical page addresses surpasses an invalid physical page address threshold value, when wherein the ratio that accounts for its all physical page addresses when physical page address invalid in this first physical blocks surpasses this invalid physical page address threshold value, then carry out the invalid data program of erasing, wherein this invalid data program of erasing comprises: select at least one second physical blocks among never writing the physical blocks of data; Data in effective those physical page addresses in this first physical blocks are copied in the physical page address that belongs to this second physical blocks; Upgrade above-mentioned logical page (LPAGE) and change physical page mapping table, physical page commentaries on classics logical page (LPAGE) mapping table and the invalid page address count table of physical blocks; And this first physical blocks of erasing.
In one embodiment of this invention, above-mentioned data access method more comprises according to the invalid page address count table of above-mentioned physical blocks judging whether do not have any effectively those physical page addresses at least one first physical blocks among the physical blocks of written data, wherein when in this first physical blocks during no effective physical page address, first physical blocks of then erasing and upgrade the invalid page address count table of above-mentioned physical blocks.
In one embodiment of this invention, above-mentioned data access method comprises that more setting up one can write the physical page pointer, with the next writeable physical page of mark address.
The present invention proposes a kind of controller system, be useful in a plurality of physical page address of a plurality of physical blocks of at least one flash chip and write data, this controller system comprises microprocessor unit, in order to the host interface unit that connects host computer system, in order to connecting the flash interface unit of flash chip, in order to memory buffer, the logical page (LPAGE) of temporal data change physical page mapping table, physical page is changeed logical page (LPAGE) mapping table and page management module.Microprocessor unit desires to write logical page address in order to desire to write data and from host computer system reception one, logical page (LPAGE) commentaries on classics physical page mapping table is the physical page address in order to the mapping of record logical page address institute, and physical page commentaries on classics logical page (LPAGE) mapping table is the logical page address in order to the mapping of record physical page address institute.The page management module desires to write data in a physical page address in order to write this, change at above-mentioned logical page (LPAGE) and to upgrade this in the physical page mapping table to desire to write logical page address be the physical page address that mapping writes these data, and above-mentioned physical page change upgrade in the logical page (LPAGE) mapping table write this physical page address of desiring to write data be mapping this desire to write logical page address.In addition, page management module can compare logical page (LPAGE) commentaries on classics physical page mapping table and physical page is changeed invalid physical page address and effective physical page address among the physical page address of logical page (LPAGE) mapping table judgement written data.
In one embodiment of this invention, above-mentioned controller system more comprises the invalid page address count table of a physical blocks, in order to write down the number of physical page address invalid in each physical blocks, wherein page management module is more in order to be updated in the above-mentioned number of desiring to write physical page address invalid in the physical page address of the original mapping of logical page address in the invalid page address count table of this physical blocks.
In one embodiment of this invention, above-mentioned controller system more comprises a physical blocks active page address count table, in order to writing down in each physical blocks the effectively number of physical page address, wherein page management module is more in order to be updated in the above-mentioned physical page address of desiring to write the original mapping of logical page address the effectively number of physical page address in this physical blocks active page address count table.
In one embodiment of this invention, whether above-mentioned page management module more is less than a no datat physical blocks in order to the number of judging the physical blocks that does not write data is counted threshold value, wherein when the number of those physical blocks that do not write data is less than this no datat physical blocks and counts threshold value, this page management module is more in order to select at least one first physical blocks according to the invalid page address count table of above-mentioned physical blocks among the physical blocks of written data, never select at least one second physical blocks among writing the physical blocks of data, data in the effective physical page address in this first physical blocks are copied in the physical page address that belongs to this second physical blocks, upgrade above-mentioned logical page (LPAGE) and change physical page mapping table, physical page is changeed logical page (LPAGE) mapping table and the invalid page address count table of physical blocks, and this first physical blocks of erasing.
In one embodiment of this invention, above-mentioned first physical blocks and second physical blocks has the effective physical page of minimized number address among those physical blocks of written data.
In one embodiment of this invention, above-mentioned controller system more comprises a no datat physical blocks admin table, does not write the physical blocks of data in order to record.
In one embodiment of this invention, above-mentioned page management module is to wait to judge the physical page address by selection one from the physical page address, change logical page (LPAGE) mapping table according to above-mentioned physical page and inquire about the logical page address that this waits to judge the mapping of physical page address, change the physical page address of the logical page address mapping of physical page mapping table inquiry institute mapping according to this logical page (LPAGE), and judge whether the physical page address of being inquired about is same as this physical page to be measured address and judges invalid physical page address and effective physical page address, if the physical page address of wherein being inquired about is same as this physical page to be measured address, then this waits to judge that the physical page address is for effective, if and the physical page address of being inquired about is different from this physical page to be measured address, then this waits to judge that the physical page address is invalid.
In one embodiment of this invention, above-mentioned page management module is more in order to judge according to above-mentioned physical blocks invalid page address count table among the physical blocks of written data whether the ratio that invalid physical page address at least one first physical blocks accounts for its all physical page addresses surpasses an invalid physical page address threshold value, above-mentioned page management module was selected at least one second physical blocks among more in order to the physical blocks that never writes data when wherein the ratio that accounts for its all those physical page addresses when those invalid in this first physical blocks physical page addresses surpassed this invalid physical page address threshold value, data in the effective physical page address in this first physical blocks are copied in the physical page address that belongs to this second physical blocks, upgrade above-mentioned logical page (LPAGE) and change physical page mapping table, physical page is changeed logical page (LPAGE) mapping table and the invalid page address count table of physical blocks, and this first physical blocks of erasing.
In one embodiment of this invention, above-mentioned page management module is more in order to judge whether do not have any effectively those physical page addresses at least one first physical blocks among those physical blocks of written data according to above-mentioned physical blocks invalid page address count table, wherein when effective those physical page addresses of nothing this first physical blocks in above-mentioned page management module more in order to erase this first physical blocks and upgrade the invalid page address count table of above-mentioned physical blocks.
In one embodiment of this invention, above-mentioned controller system comprises that more one can write the physical page pointer, in order to the next writeable physical page of mark address.
The present invention proposes a kind of flash memory system, it comprises a plurality of physical page address of belonging to a plurality of physical blocks, in order to the connector that connects host computer system, flash controller, the logical page (LPAGE) of connector change physical page mapping table and physical page is changeed logical page (LPAGE) mapping table therewith to be electrically connected to the physical page address.Logical page (LPAGE) commentaries on classics physical page mapping table is the physical page address in order to the mapping of record logical page address institute, and physical page commentaries on classics logical page (LPAGE) mapping table is the logical page address in order to the mapping of record physical page address institute.Flash controller is desired to write data and in order to host computer system reception from then on and is desired to write logical page address.In addition, flash memory desires to write data in a physical page address in order to write this, change at above-mentioned logical page (LPAGE) and to upgrade this in the physical page mapping table to desire to write logical page address be the physical page address that mapping writes these data, and above-mentioned physical page change upgrade in the logical page (LPAGE) mapping table write this physical page address of desiring to write data be mapping this desire to write logical page address.In addition, flash controller is in order to invalid physical page address and effective physical page address among the physical page address of comparing logical page (LPAGE) commentaries on classics physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table judgement written data.
In one embodiment of this invention, above-mentioned flash memory system more comprises the invalid page address count table of a physical blocks, in order to write down the number of physical page address invalid in each physical blocks, wherein work as above-mentioned flash controller more in order in the invalid page address count table of this physical blocks, to be updated in the number of desiring to write physical page address invalid in the physical page address of the original mapping of logical page address.
In one embodiment of this invention, above-mentioned flash memory system, more comprise a physical blocks active page address count table, in order to write down in each physical blocks the effectively number of those physical page addresses, wherein flash controller is more in order to be updated in the physical page address of desiring to write the original mapping of logical page address the effectively number of physical page address in this physical blocks active page address count table.
In one embodiment of this invention, whether above-mentioned flash controller more is less than a no datat physical blocks with the number of judging the physical blocks that does not write data is counted threshold value, wherein when the number of those physical blocks that do not write data is less than this no datat physical blocks and counts threshold value, flash controller is more in order to select at least one first physical blocks according to the invalid page address count table of above-mentioned physical blocks among the physical blocks of written data, never select at least one second physical blocks among writing the physical blocks of data, data in the effective physical page address in this first physical blocks are copied in the physical page address that belongs to this second physical blocks, upgrade above-mentioned logical page (LPAGE) and change physical page mapping table, physical page is changeed logical page (LPAGE) mapping table and the invalid page address count table of physical blocks, and this first physical blocks of erasing.
In one embodiment of this invention, above-mentioned flash controller is by selecting one to wait to judge the physical page address among the physical page address, change logical page (LPAGE) mapping table according to above-mentioned physical page and inquire about the logical page address that this waits to judge the mapping of physical page address, change the physical page address of the logical page address mapping of physical page mapping table inquiry institute mapping according to this logical page (LPAGE), and judge whether the physical page address of being inquired about is same as this physical page to be measured address and judges invalid physical page address and effective physical page address, if the physical page address of wherein being inquired about is same as this physical page to be measured address, then this waits to judge that the physical page address is for effective, if and the physical page address of being inquired about is different from this physical page to be measured address, then this waits to judge that the physical page address is invalid.
Based on above-mentioned, the present invention uses logical page (LPAGE) to change physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table writes down the enantiomorphic relationship of logical page address and physical page address, can for basic flash chip be write by page or leaf thus, can promote the usefulness of flash memory system effectively.
For above-mentioned feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 is the summary calcspar that illustrates flash memory system according to one embodiment of the invention.
Fig. 2 is the summary calcspar that one exemplary embodiment illustrates flash chip according to the present invention.
Fig. 3 is the schematic diagram that exemplary embodiment illustrates storage area in the flash chip according to the present invention.
Fig. 4 A～Fig. 4 C is that one exemplary embodiment illustrates the example that logical page (LPAGE) changes physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table according to the present invention.
Fig. 5 is the process flow diagram of the access running of one flash memory system that exemplary embodiment illustrates according to the present invention.
Fig. 6 is the summary calcspar that illustrates flash memory system according to another embodiment of the present invention.
Fig. 7 is the example that one exemplary embodiment illustrates the invalid page address count table of physical blocks according to the present invention.
Fig. 8 is the process flow diagram of the access running of the flash memory system that another exemplary embodiment illustrates according to the present invention.
Fig. 9 is the process flow diagram of the access running of the flash memory system that another exemplary embodiment illustrates according to the present invention.
Figure 10 is the process flow diagram of the access running of flash memory that another exemplary embodiment the illustrates system according to the present invention.
Embodiment
Fig. 1 is the summary calcspar that illustrates flash memory system according to one embodiment of the invention.Please refer to Fig. 1, flash memory system 100 has connector 110, flash chip 120 and comprises that flash controller 130, logical page (LPAGE) change the controller system of physical page mapping table 140 and physical page commentaries on classics logical page (LPAGE) mapping table 150.
Usually flash memory system 100 can use with host computer system 200, so that host computer system 200 can write to data flash memory system 100 or reading of data from flash memory system 100.In this exemplary embodiment, flash memory system 100 be solid state hard disc (Solid State Drive, SSD).But it must be appreciated that flash memory system 100 can also be storage card or carry-on dish in another embodiment of the present invention.
Connector 110 is to be electrically connected to flash controller 130, and connects host computer system 200 in order to see through bus 300.In this exemplary embodiment, connector 110 is the SATA connector.Yet, it must be appreciated to the invention is not restricted to this that connector 110 can also be USB connector, IEEE 1394 connectors, PCI Express connector, MS connector, MMC connector, SD connector, CF connector, IDE connector or other connector that is fit to.
Flash chip 120 is to be electrically connected to flash controller 130 and in order to storage data.Flash chip 120 is multilayer mnemon (Multi Level Cell, a MLC) nand flash memory in this example is implemented.Yet, it must be appreciated that the invention is not restricted to this, in another embodiment of the present invention, (Single LevelCell, SLC) nand flash memory also can be applicable to the present invention to individual layer mnemon.
Fig. 2 is the summary calcspar that one exemplary embodiment illustrates flash chip according to the present invention.It must be appreciated that the physical blocks of operating flash chip 120 with speech such as " selection ", " moving ", " division ", " replacement ", " rotating ", " groupings " when this describes the running of flash chip is notions in logic.That is to say that the physical location of the physical blocks of flash memory is not changed, but in logic the physical blocks of flash memory is operated.What deserves to be mentioned is that the running of flash chip 120 (running such as for example, write, read, erase) is to be controlled by flash controller 130.
Please refer to Fig. 2, flash chip 120 has a plurality of physical blocks (physical block) 120-0～120-N.Generally speaking, in flash memory, physical blocks is the least unit of erasing.That is each physical blocks contains the mnemon of being erased in the lump of minimal amount.Physical blocks 120-0～120-N has 128 pages or leaves (page) respectively in this exemplary embodiment, and wherein page or leaf is the minimum unit of sequencing (program).Change speech, page or leaf is for writing the minimum unit of data or reading of data.Each page or leaf comprises user data field D and redundant area R.User data field D is in order to storing user's data, and redundant area R is in order to the data of stocking system (for example, the logical page address of ECC sign indicating number, the mapping of physical page address institute etc.).In this exemplary embodiment, user data field D is 512 bytes, and redundant area R is 16 bytes.
Physical blocks 120-0～120-N can logically be grouped into system region 210, storage area 220 and alternate area 230.
Physical blocks 120-0～physical blocks the 120-S that is grouped into system region 210 is in order to the stocking system data, and this system data comprises that logical page (LPAGE) changes the page address number of the physical blocks number of physical page mapping table 140, physical page commentaries on classics logical page (LPAGE) mapping table 150, flash chip 120, each physical blocks, writes down the relation of logical page address and physical page address etc.
Physical blocks 120-(the S+1)～physical blocks 120-(S+D) that is grouped into storage area 220 is in order to store the data that host computer system 200 is write.That is to say that flash memory system 100 can use physical blocks 120-(the S+1)～physical blocks 120-(S+D) that is grouped into storage area 220 to store the data that host computer system 200 is write practically.
Physical blocks 120-(the S+D)～physical blocks 120-N that is grouped in the alternate area 230 substitutes physical blocks.Specifically, flash chip 120 can be reserved 4% physical blocks as changing use when dispatching from the factory, that is to say that when the physical blocks in the storage area 220 was damaged, the physical blocks of reserving in alternate area 230 can be in order to replacing damaged physical blocks.Therefore, if when the physical blocks in the storage area 220 takes place still to have available physical blocks in damage and the alternate area 230, flash controller 130 can extract available physical blocks and change the physical blocks of damage from alternate area 230.If when no available physical blocks took place in damage and the alternate area 230 physical blocks in the storage area 220, flash memory system 100 will be declared to re-use.
Fig. 3 is the schematic diagram that exemplary embodiment illustrates storage area in the flash chip according to the present invention.
Please refer to Fig. 3, each physical blocks of storage area 220 comprises 127 physical page addresses, therefore physical blocks 120-(the S+1)～physical blocks 120-(S+D) of storage area 220 comprises (127 * D) individual physical page addresses altogether, wherein physical page address 0～physical page address 127 belongs to physical blocks 120-(S+1), 128～physical page address, physical page address 254 belongs to physical blocks 120-(S+2), 255～physical page address, physical page address 381 belongs to physical blocks 120-(S+3), ..., physical page address (127 (D-1)+1)～physical page address 127D belongs to physical blocks 120-(S+D).In addition, in exemplary embodiment of the present invention, logical page address 0～logical page address L of physical page address that flash memory system 100100 can provide mapping storage area 220 to host computer system 200 to carry out access.In exemplary embodiment of the present invention, S, D and L are integer, and it is to be set by the deviser according to the capacity of flash chip 120, and in general, the number of physical page address is the number greater than logical page address.
Referring again to Fig. 1, flash controller 130 can be carried out with the real a plurality of instructions done of hardware pattern, software pattern or firmware pattern to finish the storage of data, the running of reading and erase etc. with connector 110 and flash chip 120.Flash controller 130 comprises microprocessor unit 130a, memory buffer 130b, host interface unit 130c and flash block 130130d.
Microprocessor unit 130a is in order to the running of control flash controller 130, for example with cooperative cooperatings such as memory buffer 130b, host interface unit 130c, flash interface module 130d and page management module 130e with to instructions such as flash memory system 100 write, reads, erases.
Memory buffer 130b is coupled to microprocessor unit 130a and in order to stocking system data temporarily or data that host computer system 200 read or write.In this exemplary embodiment, memory buffer 130b be static random access memory (static random access memory, SRAM).Yet, it must be appreciated, the invention is not restricted to this, DRAM (Dynamic Random Access Memory) (Dynamic Random Access memory, DRAM), reluctance type internal memory (Magnetoresistive Random Access Memory, MRAM), phase-change memory element (PhaseChange Random Access Memory, PRAM) or other internal memory that is fit to also can be applicable to the present invention.
Host interface unit 130c is the instruction that is coupled to microprocessor unit 130a and is transmitted in order to reception and identification host computer system 200.Just, the instruction that transmitted of host computer system 200 and data can see through host interface unit 130c and be sent to microprocessor unit 130a.In this exemplary embodiment, host interface unit 130c is the SATA interface.Yet, it must be appreciated to the invention is not restricted to this that host interface unit 130c can also be USB interface, IEEE 1394 interfaces, PCI Express interface, MS interface, MMC interface, SD interface, CF interface, ide interface or other data transmission interface that is fit to.Particularly, host interface unit 130c can be corresponding with connector 110.Just, host interface unit 130c must arrange in pairs or groups mutually with connector 110.
Flash interface module 130d is coupled to microprocessor unit 130a and in order to access flash chip 120.Just, the data of desiring to write to flash chip 120 can be converted to 120 receptible forms of flash chip via flash interface module 130d.Specifically; flash interface module 130d can support the flash interface signal; for example; the flash interface signal comprises chip enable signal/CE, order latch-up signal/CLE, address latch signal/ALE; data read control signal/RE; data write control signal/WE, write protect signal/WP, chip status signal R/B and a plurality of data are exported into signal/IO etc.
Page management module 130e is in order to management flash chip 120 under the control of microprocessing unit 130a unit.
In exemplary embodiment of the present invention, page management module 130e is embodied in the flash controller 130 with a firmware pattern.For example, the page management module 130e that will comprise a plurality of programmed instruction (for example is burned onto a program internal memory, ROM (read-only memory) (Read Only Memory, ROM)) be embedded in the flash controller 130 in and with this program internal memory, wherein when flash memory system 100 running, microprocessor unit 130a from then in the program internal memory loaded page administration module 130e come flash chip 120 is carried out runnings such as erasing, read, write.
In addition, in another exemplary embodiment of the present invention, page management module 130e can also be stored in flash chip 120 with the software pattern the specific region (for example, system region 210 in flash chip 120) in, wherein when flash memory system 100 runnings, page management module 130e can be loaded among the memory buffer 130b and by microprocessor unit 130a and carry out with runnings such as erasing, read, write.
Moreover, in another embodiment of the present invention, page management module 130e can also a hardware pattern (for example, logic lock) directly layout (lay out) in flash controller 130.
In addition, though be not illustrated in this exemplary embodiment, flash controller 130 also can comprise more that error correction module and power management module etc. are used to control the general utility functions module of flash memory.
It is to operate physical page address with the mapping of record logical page address 0～logical page address L institute by microprocessor unit 130a via carrying out page management module 130e that logical page (LPAGE) changes physical page mapping table 140, and physical page to change logical page (LPAGE) mapping table 150 be to operate logical page address with the mapping of record 0～physical page address, physical page address 127D institute by microprocessor unit 130a via carrying out page management module 130e.For example, it is to be stored in the system region 210 of flash chip 120 with physical page commentaries on classics logical page (LPAGE) mapping table 150 that logical page (LPAGE) changes physical page mapping table 140, and when flash memory system 100 runnings, logical page (LPAGE) commentaries on classics physical page mapping table 140 can be loaded among the memory buffer 130b and by page management module 130e with physical page commentaries on classics logical page (LPAGE) mapping table 150 and operate, and can be returned the system region of depositing to flash chip 120 210 in not timing ground, avoiding flash memory system 100 to cut off the power supply undesiredly, and lose the content of wherein having upgraded.
Specifically, in exemplary embodiment of the present invention, when host computer system 200 write data in any logical page address 0～logical page address L, the programmed instruction of the programmed instruction of the page management module 130e that microprocessor unit 130a institute flash controller 130 is performed can write to data in the physical page address in physical blocks 120-(S+1)～physical blocks 120-(S+D) in order.Specifically, when the programmed instruction of the programmed instruction of page management module 130e brings into use physical blocks 120-(S+1) to store the data that host computer system 200 desires to write, no matter host computer system 200 is to write that logical page address, the programmed instruction of the programmed instruction of page management module 130e all can write to data 0～physical page address, physical page address 127 in order; And when the programmed instruction of the programmed instruction of page management module 130e brings into use physical blocks 120-(S+2) to store the data that host computer system 200 desires to write, no matter host computer system 200 is to write that logical page address, the programmed instruction of the programmed instruction of page management module 130e all can write to data 128～physical page address, physical page address 254 in order.That is to say, when writing the data that host computer system 200 desires to write, the coded program instruction of page management module 130e uses the physical page address in the physical blocks to write data in order, and after the physical page address in this physical blocks is used up, just can select the physical blocks of another no datat again, and in the physical page address of the new physical blocks of selecting, continue to write in order data.
Particularly, after the programmed instruction of page management module 130e write to the physical page address with data, the programmed instruction of page management module 130e can upgrade logical page (LPAGE) commentaries on classics physical page mapping table 140 changeed logical page (LPAGE) mapping table 150 correctly to write down the enantiomorphic relationship of logical page address and physical page address with physical page.
What deserves to be mentioned is, in the present invention's one exemplary embodiment, comprise more that in page management module 130e one can write physical page pointer (Available Physical Page Pointer), in order to indicate next writeable physical page address, the base this, when the programmed instruction of carrying out page management module 130e when flash controller 130 writes the data that host computer system 200 desires to write, can in order data be write in the physical page address of flash chip 120 according to the mark that can write the physical page pointer.
In addition, what deserves to be explained is, in another embodiment, when flash chip 120 is multilayer mnemon (MultiLevel Cell, MLC) nand flash memory chip, and when writing mode is the nextpage (lower page) that upward page (upper page) is fast of specifying in the more same physical blocks of writing speed that writes in the physical blocks, because the physical page address of these nextpages is also discontinuous, so the programmed instruction of page management module 130e can be according to the physical page address of the nextpage in this physical blocks, by little to writing data greatly, and this can write the physical page pointer also can be according to the physical page address of nextpage by little to the next writeable physical page of big indication address.
In addition, when this physical page pointer desire changes when pointing to another physical blocks from a physical blocks, the order that can be among the physical blocks of no datat state be erased according to these physical blocks selects the minimum material page address of the physical blocks of being erased the earliest to desire to write the physical page address of data for next, and wherein these physical blocks order of being erased can be write down (not illustrating) and learnt by the block order of erasing.
Fig. 4 A～Fig. 4 C is that one exemplary embodiment illustrates the example that logical page (LPAGE) changes physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table according to the present invention.
Please refer to Fig. 4 A, logic of propositions page address 0～logical page address L is the address of mapping physical page respectively 0～physical page address L, just, 0～physical page address L in physical page address stores the data that host computer system 200 writes respectively in logical page address 0～logical page address L.Therefore, logical page (LPAGE) change physical page mapping table 140 and physical page change logical page (LPAGE) mapping table 150 can these a little enantiomorphic relationship of record, and can write the physical page pointer this moment and can point to physical page address (L+1).
When if host computer system 200 is desired to write data to logical page address 1, the programmed instruction of page management module 130e can write in the physical page address (L+1) according to writing the data that the physical page pointer desires host computer system 200 to write, and can write the physical page pointer and change into and point to physical page address (L+2).At this moment, the programmed instruction of page management module 130e can be updated to physical page address (L+1) in the mapping that logical page (LPAGE) changes in the physical page mapping table 140 logical page address 1, and the mapping of changeing in the logical page (LPAGE) mapping table 150 physical page address (L+1) in physical page is updated to logical page address 1 (shown in Fig. 4 B).
Then, when if host computer system 200 is desired to write data to logical page address 129, the programmed instruction of page management module 130e can write in the physical page address (L+2) according to writing the data that the physical page pointer desires host computer system 200 to write, and can write the physical page pointer and change into and point to physical page address (L+3).At this moment, the programmed instruction of page management module 130e can be updated to physical page address (L+2) in the mapping that logical page (LPAGE) changes in the physical page mapping table 140 logical page address 129, and the mapping of changeing in the logical page (LPAGE) mapping table 150 physical page address (L+2) in physical page is updated to logical page address 129 (shown in Fig. 4 C).
Fig. 5 is the process flow diagram of the access running of one flash memory system that exemplary embodiment illustrates 100 according to the present invention.
Please refer to Fig. 5, when flash memory system 100 is connected with host computer system 200 and activates, in step S501, can provide a plurality of logical page addresses for host computer system 200 accesses.Then, in step S503, can set up logical page (LPAGE) and change physical page mapping table 140 and physical page commentaries on classics logical page (LPAGE) mapping table 150.Afterwards, in step S505, can await orders and judge the instruction that is received.
If when in step S505, receiving reading command, then in step S507, can change the physical page mapping table 140 from logical page (LPAGE) and read the physical page address of mapping, and in step S509, send host computer system to from the physical page address reading data of mapping and with these data according to the logical page address of desiring to read.Afterwards, returning step S505 awaits orders.For example, when the storage area 220 at flash chip 140 is when being in the state of (b) of Fig. 4 and host computer system 200 and desiring to read the data of logical page address 1, it is physical page address (L+1) that the programmed instruction of page management module 130e can change the physical page address of reading mapping logical page address 1 the physical page mapping table 140 from logical page (LPAGE), and from physical page address (L+1) reading of data and send data to host computer system 200.
If in step S505, receive when writing instruction, then in step S511, data can be write to and to write physical page pointer physical page address pointed.Then, can change in the physical page mapping table 140 the physical page address of will desire to write the logical page address institute mapping of data at logical page (LPAGE) in step S513 is updated to and can writes physical page pointer physical page address pointed.Then, in step S515, in physical page commentaries on classics logical page (LPAGE) mapping table 150, upgrade the logical page address of the physical page address institute mapping that writes these data, and in step S517, can write the next writeable physical page of physical page pointed address.At last, in step S519, judge and record effective physical page address and invalid physical page address, return step S505 afterwards.For example, when the storage area 220 at flash chip 140 is when being in the state of Fig. 4 B and host computer system 200 and desiring to write data to logical page address 129, the programmed instruction of page management module 130e can write to data in the physical page address (L+2) and upgrade logical page (LPAGE) and change physical page mapping table 140 and change logical page (LPAGE) mapping table 150 with physical page shown in Fig. 4 C.
What deserves to be mentioned is, in exemplary embodiment of the present invention, the programmed instruction of page management module 130e can judge which physical page address is invalid physical page address and effective physical page address by the record that the comparison logical page (LPAGE) changes in physical page mapping table 140 and the physical page commentaries on classics logical page (LPAGE) mapping table 150, wherein so-called invalid physical page address is meant that wherein stored data are invalid legacy data, and effectively the physical page address is meant that wherein stored data are valid data of mapping current logic page address.
For example, with Fig. 4 C is example, when desire judges whether physical page address 0 is effective physical page address, the programmed instruction of page management module 130e can change that to read physical page address 0 the logical page (LPAGE) mapping table 150 be mapping logical page address 0 from physical page, and reading logical page address 0 according to logical page address 0 from logical page (LPAGE) commentaries on classics physical page mapping table 140 is mapping physical page address 0, so physical page address 0 is effective physical page address.In addition, when desire judges whether physical page address 1 is effective physical page address, the programmed instruction of page management module 130e can change that to read physical page address 1 the logical page (LPAGE) mapping table 150 be mapping logical page address 1 from physical page, and reading logical page address 1 according to logical page address 1 from logical page (LPAGE) commentaries on classics physical page mapping table 140 is mapping physical page address (L+1), so physical page address 1 is invalid physical page address.Similarly, when desire judges whether physical page address 129 is effective physical page address, the programmed instruction of page management module 130e can change that to read physical page address 129 the logical page (LPAGE) mapping table 150 are mapping logical page addresses 129 from physical page, and reading logical page address 129 according to logical page address 129 from logical page (LPAGE) commentaries on classics physical page mapping table 140 is mapping physical page addresses (L+2), so physical page address 129 is invalid physical page address.That is to say, the programmed instruction of page management module 130e can change the physical page address of the logical page address institute mapping of physical page mapping table 140 inquiry physical page address mapping to be judged according to physical page address to be judged through physical page commentaries on classics logical page (LPAGE) mapping table 150 and logical page (LPAGE), if when physical page address to be judged conforms to the physical page address of being inquired about, then this physical page address to be judged is effective physical page address, and anti-then is invalid physical page address.
What deserves to be mentioned is, since flash chip 120 be with physical blocks as the least unit of erasing, so the programmed instruction of page management module 130e can merge the data in the effective physical page address to discharge invalid physical page address and writes new data through above-mentioned comparison.For example, the programmed instruction of page management module 130e can copy to the data in effective physical page address at least one physical blocks in the physical page address of the physical blocks that does not write any data, and, the valid data that disperse can be merged and invalid physical page address are discharged (hereinafter referred to as the invalid data program of erasing) thus with the running of erasing of this physical blocks.What deserves to be mentioned is, merge with after discharging invalid physical page address carrying out valid data, the programmed instruction of page management module 130e can upgrade physical page changes the enantiomorphic relationship that logical page (LPAGE) mapping table 150 and logical page (LPAGE) change logical page address and physical page address in the physical page mapping table 140.
In the present invention's one exemplary embodiment, controller system more comprises the invalid page address count table 170 of physical blocks (shown in the flash memory system 100 ' of Fig. 6) writing down the number of physical page address invalid among each physical blocks 120-0～140-(S+D), with as the data in the effective physical page address are merged to discharge the foundation of invalid physical page address.Similarly, be to be stored in the system region 210 of flash chip 120, and when flash memory system 100 runnings, the invalid page address count table 170 of physical blocks can be loaded among the memory buffer 130b and by the programmed instruction of flash controller 130 execution page management module 130e and operate, and can be returned the system region of depositing to flash chip 120 210 in not timing ground, avoiding flash memory system 100 to cut off the power supply undesiredly, and lose the content of wherein having upgraded.
Fig. 7 is the example that one exemplary embodiment illustrates the invalid page address count table of physical blocks according to the present invention, wherein the invalid page address count table 170 of the physical blocks example that is corresponding diagram 4.
Please refer to (a) and Fig. 4 A of Fig. 7, under the state shown in the corresponding diagram 4A, the count value that the invalid page address count table 170 of physical blocks can write down the invalid physical page address of each physical blocks 120-0～120-(S+D) is 0.
Please refer to (b) and Fig. 4 B of Fig. 7, under the state shown in the corresponding diagram 4B, because the data of host computer system 200 logical page address 1 desiring to write are written into physical page address (L+1), so mapping and physical page that the programmed instruction of page management module 130e can upgrade logical page (LPAGE) and change logical page address 1 in the physical page mapping table 140 are changeed the mapping of physical page address (L+1) in the logical page (LPAGE) mapping table 150.Particularly, can to read the physical page address of logical page address 1 former mapping before changeing physical page mapping table 140 be physical page address 1 and will add 1 about the count value of the invalid physical page address of the physical blocks 120-(S+1) under the physical page address 1 in the invalid page address count table 170 of physical blocks to upgrade logical page (LPAGE) at the programmed instruction of page management module 130e.
Similarly, please refer to (c) and Fig. 4 C of Fig. 7, under the state shown in the corresponding diagram 4C, because the data of host computer system 200 logical page address 129 desiring to write are written into physical page address (L+2), so mapping and physical page that the programmed instruction of page management module 130e can upgrade logical page (LPAGE) and change logical page address 129 in the physical page mapping table 140 are changeed the mapping of physical page address (L+2) in the logical page (LPAGE) mapping table 150.Particularly, can to read the physical page address of logical page address 129 former mappings before changeing physical page mapping table 140 be physical page address 129 and will add 1 about the count value of the invalid physical page address of the physical blocks 120-(S+1) under the physical page address 129 in the invalid page address count table 170 of physical blocks to upgrade logical page (LPAGE) at the programmed instruction of page management module 130e.
For example, in the present invention's one exemplary embodiment, when carrying out to carry out the data consolidation procedure according at least one physical blocks that the invalid page address count table 170 of physical blocks is selected to have the effective physical page of minimized number address when invalid data is erased program.
What deserves to be mentioned is that above-mentioned exemplary embodiment is to count the number of physical page address invalid in the physical blocks to set up the invalid page address count table 170 of physical blocks.Yet, in another embodiment of the present invention, can also set up physical blocks active page address count table and count in the physical blocks the effectively number of physical page address, to select the physical blocks of valid data minimum data to come data to merge thus carrying out the invalid data program of erasing.
In addition, in the present invention's one exemplary embodiment, controller system upgrades and comprises that no datat physical blocks admin table (not illustrating) does not write the physical blocks of any data with record.That is to say that the physical blocks that is recorded in the no datat physical blocks admin table has been erased to supply to write the physical blocks of data.Particularly, the programmed instruction of page management module 130e can upgrade according to the information in the no datat physical blocks admin table can write the physical page pointer.For example, pointed to physical page address 127D and carry out when writing instruction can writing the physical page pointer, the programmed instruction of page management module 130e can one of them write first physical page address of the physical blocks of any data according to writing the physical page pointed in the no datat physical blocks admin table.
Particularly, ought carry out invalid data as mentioned above erases and needs not write the physical blocks of any data in the program and write data in effective physical page address, therefore in the present invention's one exemplary embodiment, the programmed instruction of page management module 130e can then can carry out invalid data and erase program to discharge invalid physical page address when judge only surplus 1 physical blocks that does not write any data in the no datat physical blocks admin table.What deserves to be mentioned is, the invention is not restricted to when not writing the physical blocks of any data for surplus 1, to carry out invalid data and erase.
In addition, in another exemplary embodiment of the present invention, when the programmed instruction of page management module 130e also can judge that the ratio of invalid physical page address at least one physical blocks surpasses an invalid physical page address threshold value according to the count value in the invalid page address count table 170 of physical blocks, then carry out data and merge to discharge the program of invalid physical page address.At this, this invalid physical page address threshold value is to be set up on their own by the user, and wherein when this invalid physical page address threshold value was low more, the frequency of then carrying out the data consolidation procedure was high more, otherwise, then low more.In the present invention's one exemplary embodiment, this invalid physical page address threshold value is to be set at 80%.
In addition, in another exemplary embodiment of the present invention, when the programmed instruction of page management module 130e also can be judged in arbitrary physical blocks no any effective physical page address according to the count value in the invalid page address count table 170 of physical blocks, the physical blocks of then this not being had any effective physical page address is carried out the running of erasing discharging invalid physical page address, and this physical blocks is recorded in the no datat physical blocks admin table.
Fig. 8 is the process flow diagram of the access running of one flash memory system 100 ' that exemplary embodiment illustrates according to the present invention.
Please refer to Fig. 8, when flash memory system 100 is connected with host computer system 200 and activates, in step S801, can provide a plurality of logical page addresses for host computer system 200 accesses.Then, in step S803, can set up logical page (LPAGE) and change physical page mapping table 140, physical page commentaries on classics logical page (LPAGE) mapping table 150 and the invalid page address count table 170 of physical blocks.Afterwards, in step S805, can await orders and judge the instruction that is received.
If when in step S805, receiving reading command, then in step S807, can change physical page mapping table 140 from logical page (LPAGE) and read the physical page address of mapping, and in step S809, send host computer system to from the physical page address reading data of mapping and with these data according to the logical page address of desiring to read.Afterwards, returning step S805 awaits orders.
If in step S805, receive when writing instruction, then in step S811, data can be write to and to write physical page pointer physical page address pointed.Then, can be in the invalid page address count table 170 of physical blocks in step S813 the count value of invalid physical page address of physical blocks of desiring to write the present institute of the logical page address mapping of data be added 1.Afterwards, can change in the physical page mapping table 140 the physical page address of will desire to write the logical page address institute mapping of data at logical page (LPAGE) in step S815 is updated to and can writes physical page pointer physical page address pointed.Then, in step S817, in physical page commentaries on classics logical page (LPAGE) mapping table 150, upgrade the logical page address of the physical page address institute mapping that writes these data, and in step S819, can write the next writeable physical page of physical page pointed address.
Particularly after finishing write activity, meeting judges whether the number of the physical blocks that does not write data is less than the no datat physical blocks and counts threshold value (for example, as mentioned above, this exemplary embodiment is to be set at 1) in step S821.If in step S821, judge when the physical blocks do not write data is less than the no datat physical blocks and counts threshold value, then can carry out the invalid data program of erasing.For example, in step S823, can from the physical blocks of written data, select 2 physical blocks according to the invalid page address count table 170 of physical blocks.For example, 2 physical blocks that have the effective physical page of minimized number address among the physical blocks that selected 2 physical blocks are written data, and comparison logical page (LPAGE) commentaries on classics physical page mapping table 140 changes logical page (LPAGE) mapping table 150 to judge the effective physical page address in selected 2 physical blocks with physical page in step S825.
Then, in step S827, can from flash chip 120, select 1 physical blocks that does not write data, and the data in the effective physical page address that will be judged copy in the physical page address of selected physical blocks in step S827 in step S825 in step S829.Then, in step S831, selected 2 physical blocks among the step S823 are erased running to discharge available storage area.At last, upgrade in step S833 that logical page (LPAGE) changes physical page mapping table 140, physical page is changeed logical page (LPAGE) mapping table 150 and the invalid page address count table 170 of physical blocks, and finish erase program and return step S805 and await orders of invalid data.
It must be appreciated, though being 2 physical blocks selecting written data, Fig. 8 carries out the invalid data program of erasing with 1 physical blocks that does not write data, yet the invention is not restricted to this, carry out invalid data when the physical blocks of carrying out to select when invalid data is erased program one or more written data and erase, and can select one or more physical blocks that do not write data to store the valid data that merged.
Fig. 9 is the process flow diagram of the access running of the flash memory system 100 ' that another exemplary embodiment illustrates according to the present invention.
Please refer to Fig. 9, step S901, S903, S905, S907, S909, S911, S913, S915, S917 and S919 are same as step S801, S803, S805, S807, S809, S811, S813, S815, S817 and S819, do not repeat them here.
In step S921, can judge whether that the ratio of invalid physical page address in the physical blocks surpasses invalid physical page address threshold value (for example, this exemplary embodiment is to set 80%) according to the invalid page address count table 170 of physical blocks.If in step S921, judge when the ratio that invalid physical page address at least 1 physical blocks is arranged surpasses invalid physical page address threshold value, then can carry out invalid data program (for example, the step S923～S929) that erases.
Meeting comparison logical page (LPAGE) commentaries on classics physical page mapping table 140 and physical page commentaries on classics logical page (LPAGE) mapping table 150 are judged the effective physical page address in this physical blocks in step S923.
Then, the physical blocks number that can surpass invalid physical page address threshold value according to the ratio of judge invalid physical page address in step S925 is selected at least 1 physical blocks that does not write data from flash chip 120, and the data in the effective physical page address that will be judged in step S923 in step S927 copy in the physical page address of selected physical blocks in step S925.Then, in step S927, the physical blocks of being judged among the step S921 is erased running to discharge available storage area.At last, upgrade in step S929 that logical page (LPAGE) changes physical page mapping table 140, physical page is changeed logical page (LPAGE) mapping table 150 and the invalid page address count table 170 of physical blocks, and finish erase program and return step S905 and await orders of invalid data.
Figure 10 is the process flow diagram of the access running of the flash memory system 100 ' that another exemplary embodiment illustrates according to the present invention.
Please refer to Figure 10, step S1001, S1003, S1005, S1007, S1009, S1011, S1013, S1015, S1017 and S1019 are same as step S801, S803, S805, S807, S809, S811, S813, S815, S817 and S819, do not repeat them here.
In step S1021, can judge whether to have any its physical page address according to the invalid page address count table 170 of physical blocks and be all invalid physical blocks.If when judging that in step S1021 having the physical page address is all invalid physical blocks, then in step S1023, the physical page address can be all invalid physical blocks and carry out the running of erasing to discharge available storage area.At last, in step S1025, upgrade the invalid page address count table of physical blocks, and finish the data consolidation procedure and return step S1005 and await orders.
It must be appreciated, though in above-mentioned Fig. 5, Fig. 8, Fig. 9 and Figure 10, do not illustrate the step that finishes running, these those skilled in the art can understand easily in flash memory system this a little flow processs that decommission and can stop.In addition, the order of this exemplary embodiment Fig. 5, Fig. 8, Fig. 9 and the described step of Figure 10 and non-limiting the present invention, skill person is known in this field can come the real the present invention that does with non-the described order of exemplary embodiment easily according to spirit of the present invention.
In sum, the present invention uses logical page (LPAGE) to change physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table writes down the enantiomorphic relationship of logical page address and physical page address, can for basic flash chip be write by page or leaf thus, can promote the usefulness of flash memory system effectively.In addition, tranmittance is that the data merging is carried out to discharge invalid physical page address with effective physical page address in the invalid physical page address of decidable to logical page (LPAGE) commentaries on classics physical page mapping table and physical page commentaries on classics logical page (LPAGE) mapping table.Moreover the present invention uses the invalid page address count table of physical blocks to write down the number of invalid physical page address in each physical blocks, can judge the physical blocks that can discharge more space in the back of erasing thus apace, to promote the usefulness of flash memory system.
Though the present invention discloses as above with embodiment; right its is not in order to limit the present invention; have in the technical field under any and know the knowledgeable usually; without departing from the spirit and scope of the present invention; when doing a little change and retouching, so protection scope of the present invention is worked as with being as the criterion that claim was defined.

Claims (25)

1. data access method, it is carried out with access data in a plurality of physical page address of a plurality of physical blocks of at least one flash chip by a flash controller, and this data access method comprises:
Provide a plurality of logical page addresses, for a host computer system access;
Set up a logical page (LPAGE) and change physical page mapping table to write down those physical page addresses of those logical page address institute mappings respectively;
Set up a physical page and change logical page (LPAGE) mapping table to write down those logical page addresses of those physical page address institute mappings respectively;
Desire to write data and from this host computer system reception one and desire to write logical page address, write this and desire to write data in a physical page address, and change at this logical page (LPAGE) and to upgrade this in physical page mapping table to desire to write logical page address be the physical page address that mapping writes these data, and this physical page change upgrade in logical page (LPAGE) mapping table write this physical page address of desiring to write data be mapping this desire to write logical page address; And
Compare this logical page (LPAGE) commentaries on classics physical page mapping table and this physical page and change invalid those physical page addresses and effective those physical page addresses among those physical page addresses of logical page (LPAGE) mapping table judgement written data.
2. data access method as claimed in claim 1 is characterized in that, more comprises:
Set up the invalid page address count table of a physical blocks to write down the number of those invalid in each those physical blocks physical page addresses; And
In the invalid page address count table of this physical blocks, be updated in the number that this desires to write those invalid in the physical page address of the original mapping of logical page address physical page addresses.
3. data access method as claimed in claim 1 is characterized in that, more comprises:
Set up a physical blocks active page address count table to write down the number of effective those physical page addresses in each those physical blocks; And
In this physical blocks active page address count table, be updated in this physical page address of desiring to write the original mapping of logical page address the effectively number of those physical page addresses.
4. data access method as claimed in claim 2 is characterized in that, more comprises:
Whether the number of judging those physical blocks do not write data is less than a no datat physical blocks is counted threshold value,
Wherein when the number of those physical blocks that do not write data is less than this no datat physical blocks and counts threshold value, then carry out the invalid data program of erasing, this invalid data program of erasing comprises:
Among those physical blocks of written data, select at least one first physical blocks according to the invalid page address count table of this physical blocks;
Never select at least one second physical blocks among writing those physical blocks of data;
Data in effective those physical page addresses in this at least one first physical blocks are copied in those physical page addresses that belong to this at least one second physical blocks;
Upgrade this logical page (LPAGE) and change physical page mapping table, this physical page commentaries on classics logical page (LPAGE) mapping table and the invalid page address count table of this physical blocks; And
This at least one first physical blocks of erasing.
5. data access method as claimed in claim 4 is characterized in that, this at least one first physical blocks has effectively those physical page addresses of minimized number among those physical blocks of written data.
6. data access method as claimed in claim 4 is characterized in that, more comprises setting up a no datat physical blocks admin table, does not write those physical blocks of data with record.
7. data access method as claimed in claim 1, it is characterized in that, compare this logical page (LPAGE) and change physical page mapping table and this physical page and change logical page (LPAGE) mapping table and judge that those invalid among those physical page addresses of written data physical page addresses and the step of effective those physical page addresses comprise:
Among those physical page addresses, select one to wait to judge the physical page address;
Change logical page (LPAGE) mapping table according to this physical page and inquire about the logical page address that this waits to judge the mapping of physical page address;
Change the physical page address of the logical page address mapping of physical page mapping table inquiry institute mapping according to this logical page (LPAGE);
Judge whether the physical page address of being inquired about is same as this physical page to be measured address, if the physical page address of wherein being inquired about is same as this physical page to be measured address, then this waits to judge that the physical page address is for effective, if and the physical page address of being inquired about is different from this physical page to be measured address, then this waits to judge that the physical page address is invalid.
8. data access method as claimed in claim 2 is characterized in that, more comprises:
Judge according to the invalid page address count table of this physical blocks whether the ratio that those invalid physical page addresses at least one first physical blocks account for its all those physical page addresses surpasses an invalid physical page address threshold value in those physical blocks of written data
When wherein the ratio that accounts for its all those physical page addresses when those invalid in this at least one first physical blocks physical page addresses surpasses this invalid physical page address threshold value, then carry out the invalid data program of erasing, this invalid data program of erasing comprises:
Never select at least one second physical blocks among writing those physical blocks of data;
Data in effective those physical page addresses in this at least one first physical blocks are copied in those physical page addresses that belong to this at least one second physical blocks;
Upgrade this logical page (LPAGE) and change physical page mapping table, this physical page commentaries on classics logical page (LPAGE) mapping table and the invalid page address count table of this physical blocks; And
This at least one first physical blocks of erasing.
9. data access method as claimed in claim 2 is characterized in that, more comprises:
Judge among those physical blocks of written data, whether not have any effectively those physical page addresses at least one first physical blocks according to the invalid page address count table of this physical blocks,
Wherein when not having effectively those physical page addresses in this at least one first physical blocks, this at least one first physical blocks of then erasing and upgrade the invalid page address count table of this physical blocks.
10. data access method as claimed in claim 1 is characterized in that, comprises that more setting up one can write the physical page pointer, with next writeable those physical page addresses of mark.
11. a controller system is useful in a plurality of physical page address of a plurality of physical blocks of at least one flash chip and writes data, this controller system comprises:
One host interface unit is in order to connect a host computer system;
One microprocessor unit desires to write logical page address in order to desire to write data and from this host computer system reception one;
One flash interface unit is in order to connect this at least one flash chip;
One memory buffer is in order to temporal data;
One logical page (LPAGE) changes physical page mapping table, in order to write down those physical page addresses of those logical page address institute mappings;
One physical page is changeed logical page (LPAGE) mapping table, in order to write down those logical page addresses of those physical page address institute mappings; And
One page administration module, desire to write data in a physical page address in order to write this, and change at this logical page (LPAGE) and to upgrade this in physical page mapping table to desire to write logical page address be the physical page address that mapping writes these data, and this physical page change upgrade in logical page (LPAGE) mapping table write this physical page address of desiring to write data be mapping this desire to write logical page address
Wherein this page management module is compared this logical page (LPAGE) changes physical page mapping table and this physical page and changes logical page (LPAGE) mapping table and judge invalid those physical page addresses and effective those physical page addresses among those physical page addresses of written data.
12. controller system as claimed in claim 11 is characterized in that, more comprises the invalid page address count table of a physical blocks, in order to writing down the number of those invalid in each those physical blocks physical page addresses,
Wherein this page management module is more in order to be updated in the number that this desires to write those invalid in the physical page address of the original mapping of logical page address physical page addresses in the invalid page address count table of this physical blocks.
13. controller system as claimed in claim 11 is characterized in that, more comprises a physical blocks active page address count table, in order to writing down in each those physical blocks the effectively number of those physical page addresses,
Wherein this page management module is more in order to be updated in this physical page address of desiring to write the original mapping of logical page address the effectively number of those physical page addresses in this physical blocks active page address count table.
14. controller system as claimed in claim 12 is characterized in that, whether this page management module more is less than a no datat physical blocks in order to the number of judging those physical blocks that do not write data is counted threshold value,
Wherein when the number of those physical blocks that do not write data is less than this no datat physical blocks and counts threshold value, this page management module is more in order to select at least one first physical blocks according to the invalid page address count table of this physical blocks among those physical blocks of written data, never select at least one second physical blocks among writing those physical blocks of data, data in effective those physical page addresses in this at least one first physical blocks are copied in those physical page addresses that belong to this at least one second physical blocks, upgrade this logical page (LPAGE) and change physical page mapping table, this physical page is changeed logical page (LPAGE) mapping table and the invalid page address count table of this physical blocks, and this at least one first physical blocks of erasing.
15. flash controller as claimed in claim 14 is characterized in that, this at least one first physical blocks has effectively those physical page addresses of minimized number among those physical blocks of written data.
16. controller system as claimed in claim 14 is characterized in that, more comprises a no datat physical blocks admin table, does not write those physical blocks of data in order to record.
17. flash controller as claimed in claim 11; It is characterized in that; This page management module is by select physical page a to be judged address among those physical page addresses; Turn to the logical page address that logical page (LPAGE) mapping table is inquired about this physical page to be judged address mapping according to this physical page; Turn to the physical page address of the logical page address mapping of physical page mapping table inquiry institute mapping according to this logical page (LPAGE); And judge whether the physical page address of inquiring about is same as this physical page to be measured address and judges those invalid physical page addresses and effective those physical page addresses
If the physical page address of wherein being inquired about is same as this physical page to be measured address, then this waits to judge the physical page address for effectively, and if the physical page address of being inquired about be different from this physical page to be measured address, then this waits to judge that the physical page address is invalid.
18. controller system as claimed in claim 12, it is characterized in that, this page management module is more in order to judge according to the invalid page address count table of this physical blocks among those physical blocks of written data whether the ratio that those invalid physical page addresses at least one first physical blocks account for its all those physical page addresses surpasses an invalid physical page address threshold value
When wherein the ratio that accounts for its all those physical page addresses when those invalid in this at least one first physical blocks physical page addresses surpasses this invalid physical page address threshold value, this page management module is more in order to select at least one second physical blocks among those physical blocks that never write data, data in effective those physical page addresses in this at least one first physical blocks are copied in those physical page addresses that belong to this at least one second physical blocks, upgrade this logical page (LPAGE) and change physical page mapping table, this physical page is changeed logical page (LPAGE) mapping table and the invalid page address count table of this physical blocks, and this at least one first physical blocks of erasing.
19. controller system as claimed in claim 12, it is characterized in that, this page management module is more in order to judge whether do not have any effectively those physical page addresses at least one first physical blocks among those physical blocks of written data according to the invalid page address count table of this physical blocks
Wherein when not having effectively those physical page addresses in this at least one first physical blocks, this page management module is more in order to erase this at least one first physical blocks and upgrade the invalid page address count table of this physical blocks.
20. controller system as claimed in claim 11 is characterized in that, comprises that more one can write the physical page pointer, in order to next writeable those physical page addresses of mark.
21. a flash memory system comprises:
A plurality of physical page address, wherein those physical page addresses belong to a plurality of physical blocks;
A connector is in order to connect a host computer system;
One logical page (LPAGE) changes physical page mapping table, in order to write down those physical page addresses of those logical page address institute mappings;
One physical page is changeed logical page (LPAGE) mapping table, in order to write down those logical page addresses of those physical page address institute mappings; And
One flash controller is electrically connected to those physical page addresses and this connector, and desires to write logical page address in order to desire to write data and from this host computer system reception one,
Wherein this flash controller more desires to write data in a physical page address in order to write this, and change at this logical page (LPAGE) and to upgrade this in physical page mapping table to desire to write logical page address be the physical page address that mapping writes these data, and this physical page change upgrade in logical page (LPAGE) mapping table write this physical page address of desiring to write data be mapping this desire to write logical page address
Wherein this flash controller is compared this logical page (LPAGE) changes physical page mapping table and this physical page and changes logical page (LPAGE) mapping table and judge invalid those physical page addresses and effective those physical page addresses among those physical page addresses of written data.
22. flash memory system as claimed in claim 21 is characterized in that, more comprises the invalid page address count table of a physical blocks, in order to writing down the number of those invalid in each those physical blocks physical page addresses,
Wherein this flash controller is more in order to be updated in the number that this desires to write those invalid in the physical page address of the original mapping of logical page address physical page addresses in the invalid page address count table of this physical blocks.
23. flash memory system as claimed in claim 21 is characterized in that, more comprises a physical blocks active page address count table, in order to writing down in each those physical blocks the effectively number of those physical page addresses,
Wherein this flash controller is more in order to be updated in this physical page address of desiring to write the original mapping of logical page address the effectively number of those physical page addresses in this physical blocks active page address count table.
24. flash memory system as claimed in claim 22 is characterized in that, whether this flash controller more is less than a no datat physical blocks in order to the number of judging those physical blocks that do not write data is counted threshold value,
Wherein when the number of those physical blocks that do not write data is less than this no datat physical blocks and counts threshold value, this flash controller is more in order to select at least one first physical blocks according to the invalid page address count table of this physical blocks among those physical blocks of written data, never select at least one second physical blocks among writing those physical blocks of data, data in effective those physical page addresses in this at least one first physical blocks are copied in those physical page addresses that belong to this at least one second physical blocks, upgrade this logical page (LPAGE) and change physical page mapping table, this physical page is changeed logical page (LPAGE) mapping table and the invalid page address count table of this physical blocks, and this at least one first physical blocks of erasing.
25. flash memory system as claimed in claim 21; It is characterized in that; This flash controller is by select physical page a to be judged address among those physical page addresses; Turn to the logical page address that logical page (LPAGE) mapping table is inquired about this physical page to be judged address mapping according to this physical page; Turn to the physical page address of the logical page address mapping of physical page mapping table inquiry institute mapping according to this logical page (LPAGE); And judge whether the physical page address of inquiring about is same as this physical page to be measured address and judges those invalid physical page addresses and effective those physical page addresses
If the physical page address of wherein being inquired about is same as this physical page to be measured address, then this waits to judge the physical page address for effectively, and if the physical page address of being inquired about be different from this physical page to be measured address, then this waits to judge that the physical page address is invalid.
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