CN110633224A - Logic-to-entity table updating method and storage controller - Google Patents
Logic-to-entity table updating method and storage controller Download PDFInfo
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- CN110633224A CN110633224A CN201810558362.0A CN201810558362A CN110633224A CN 110633224 A CN110633224 A CN 110633224A CN 201810558362 A CN201810558362 A CN 201810558362A CN 110633224 A CN110633224 A CN 110633224A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/10—Address translation
- G06F12/1009—Address translation using page tables, e.g. page table structures
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Abstract
The invention provides a logic conversion entity table updating method and a storage controller. The memory controller includes a processor and a flash memory access circuit. The flash memory access circuit is coupled to the flash memory. The logic conversion entity table updating method comprises the following steps: transferring, by the processor, a write command to the flash memory access circuit; accessing the flash memory by the flash memory access circuit executing the write command; and updating the logic transition entity table in the random access memory through the flash memory access circuit after the flash memory access circuit executes the write command.
Description
Technical Field
The present invention relates to a method for updating a logic to entity table and a memory controller, and more particularly, to a method for updating a logic to entity table and a memory controller capable of increasing instruction execution speed.
Background
Solid State Drive (SSD) is a storage device that is quite popular today. Generally, the solid state disk receives a command from a host system through a memory controller and accesses a flash memory (i.e., a rewritable nonvolatile memory module) according to the received command.
In the example of FIG. 1, the memory device 10 may include a memory controller 100, a flash memory 170, and a DRAM 180. The storage device 10 is, for example, a solid state disk. The memory controller 100 may include a processor 110, flash memory access circuitry 120, dynamic random access memory access circuitry 130, static random access memory 140, and interrupt control circuitry 150. The interrupt control circuit 150 can transmit or receive an interrupt signal through the signal line 101, the signal line 102, and the signal line 103.
The processor 110 may issue a write command (i.e., a page program command or a page program request) to the flash memory access circuit 120 via the bus 160. The flash memory access circuit 120 accesses the flash memory 170 according to the write command. At this time, the processor 110 waits for the write instruction to finish executing. After the write command is executed, the flash memory access circuit 120 transmits an interrupt signal to the interrupt control circuit 150 through the signal line 101, and the interrupt control circuit 150 transmits the interrupt signal to the processor 110. After the processor 110 receives the interrupt signal and confirms that the write command is executed, the processor 110 updates a logical-to-physical table (L2P table) temporarily stored in the sram 140 or the dram 180 according to the physical write address of the write command. The logical-to-physical address mapping table is also called logical-to-physical address mapping table. However, the process of sending the interrupt signal and the processor 110 executing the firmware to update the logic transition entity table takes too much time to reduce the Input/Output Operations Per Second (IOPS) of the system. Therefore, how to increase the input/output operations per second of the system is an objective that should be addressed by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides a method for updating a logical-to-entity table and a storage controller, which efficiently updates the logical-to-entity table to increase the input/output operations per second of a system.
The invention provides a logic-to-entity table updating method which is suitable for a storage controller and a flash memory (flash). The memory controller includes a processor and a flash memory access circuit. The flash memory access circuit is coupled to the flash memory. The logic conversion entity table updating method comprises the following steps: transferring, by the processor, a write command to the flash memory access circuit; accessing the flash memory by the flash memory access circuit executing the write command; and updating the logic transition entity table in the random access memory through the flash memory access circuit after the flash memory access circuit executes the write command.
In an embodiment of the invention, the processor searches the entity unit mapped by the logic unit through the logic transition entity table.
In an embodiment of the invention, the write command includes a physical address, a data source, and an update address of the random access memory.
In an embodiment of the invention, the step of executing the write command by the flash memory access circuit includes: data corresponding to the data source is written to a physical address of the flash memory by the flash memory access circuit.
In an embodiment of the invention, the step of updating the logic transition table in the random access memory by the flash memory access circuit includes: the physical address is written to the update address of the random access memory by the flash memory access circuit.
In an embodiment of the invention, the Random Access Memory is a Static Random Access Memory (SRAM) in the Memory controller or a dynamic Random Access Memory coupled to the Memory controller.
The invention provides a memory controller, which comprises a processor and a flash memory access circuit. The flash memory access circuit is coupled to the processor by a bus. The flash memory access circuit is coupled to the flash memory. The processor transfers the write command to the flash memory access circuit. The flash memory access circuit executes a write command to access the flash memory. After the flash memory access circuit executes the write command, the flash memory access circuit updates the logical transition table in the random access memory.
In an embodiment of the invention, the processor searches the entity unit mapped by the logic unit through the logic transition entity table.
In an embodiment of the invention, the write command includes a physical address, a data source, and an update address of the random access memory.
In an embodiment of the invention, the flash memory access circuit writes data corresponding to the data source to a physical address of the flash memory.
In one embodiment of the present invention, after the flash memory access circuit executes the write command, the flash memory access circuit writes the physical address to the update address of the random access memory.
In an embodiment of the invention, the random access memory is a static random access memory in the memory controller or a dynamic random access memory coupled to the memory controller.
Based on the above, the method for updating a logic transition entity table and the memory controller according to the present invention update the logic transition entity table in the random access memory through the flash memory access circuit after the flash memory access circuit executes the write command. Therefore, the flash memory access circuit does not need to transmit an interrupt signal to the processor after the write instruction is executed, and then the processor executes the firmware to update the logic transition table in the random access memory. The instruction execution speed can thus be increased, thereby improving the input-output operations per second of the system.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 is a block diagram of a conventional memory device.
FIG. 2 is a block diagram of a memory device according to an embodiment of the invention.
FIG. 3 is a flowchart of a logic transition entity table updating method according to an embodiment of the present invention.
Fig. 4A and 4B are schematic diagrams of updating a logical transition entity table according to an embodiment of the invention.
Description of reference numerals:
10. 20: storage device
100. 200: storage controller
101. 102, 103, 201, 202, 203: signal line
110. 210: processor with a memory having a plurality of memory cells
120. 220, and (2) a step of: flash memory access circuit
130. 230: dynamic random access memory access circuit
140. 240: static random access memory
150. 250: interrupt control circuit
160. 260: bus line
170. 270: flash memory
180. 280: dynamic random access memory
221: logic to entity table updating circuit
S301, S303, S305: step of logic conversion entity table updating method
400: logic to entity table
Detailed Description
FIG. 2 is a block diagram of a memory device according to an embodiment of the invention.
Referring to fig. 2, the memory device 20 may include a memory controller 200, a flash memory 270, and a dynamic random access memory 280. The Dynamic Random Access Memory 280 may be, for example, a Synchronous Dynamic Random Access Memory (SDRAM), a Double Data rate SDRAM (DDR SDRAM), a mobile DDR (MDDR SDRAM), a low power DDR (LPDDRSDRAM), or the like. The memory controller 200 may include a processor 210, flash memory access circuitry 220, dynamic random access memory access circuitry 230, static random access memory 240, and interrupt control circuitry 250. The interrupt control circuit 250 can transmit or receive an interrupt signal through the signal line 201, the signal line 202, and the signal line 203. The various components in the memory controller 200 may communicate over a bus 260.
The storage device 20 is, for example, a usb disk, a memory card, a Solid State Drive (SSD), or other similar devices. The Processor 210 is, for example, a Central Processing Unit (CPU), a Microprocessor (micro-Processor), or other Programmable Processing Unit (Microprocessor), a Digital Signal Processor (DSP), a Programmable controller, an Application Specific Integrated Circuit (ASIC), a Programmable Logic Device (PLD), or other similar circuit elements, but the invention is not limited thereto. The flash memory 270 may include a rewritable non-volatile memory module.
The flash memory access circuit 220 is used for receiving an instruction from the processor 210 to perform a data writing (also referred to as Programming) operation and a data reading operation on the rewritable nonvolatile memory module. The flash memory access circuit 220 can also perform an erase operation on the rewritable nonvolatile memory module.
For example, the processor 210 can execute a write instruction sequence to instruct the flash memory access circuit 220 to write data into the rewritable nonvolatile memory module. The processor 210 can execute a read instruction sequence to instruct the flash memory access circuit 220 to read data from the rewritable non-volatile memory module. The processor 210 can execute an erase command sequence to instruct the flash memory access circuit 220 to perform an erase operation on the rewritable nonvolatile memory module. The write command sequence, the read command sequence, and the erase command sequence may include one or more program codes or command codes respectively and are used to instruct the rewritable nonvolatile memory module of the flash memory 270 to perform corresponding write, read, and erase operations. In one embodiment, the processor 210 may issue other types of command sequences to the flash memory access circuit 220 to perform corresponding operations on the rewritable nonvolatile memory module.
In addition, the data to be written into the rewritable nonvolatile memory module is converted into a format acceptable to the rewritable nonvolatile memory module by the flash memory access circuit 220. Specifically, if the processor 210 wants to access the rewritable nonvolatile memory module, the processor 210 sends a corresponding instruction sequence to the flash memory access circuit 220 to instruct the flash memory access circuit 220 to perform a corresponding operation. For example, the instruction sequences may include a write instruction sequence for indicating write data, a read instruction sequence for indicating read data, an erase instruction sequence for indicating erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection procedures, etc.). The sequences of instructions may include one or more signals or data on bus 260. These signals or data may include instruction code or program code. For example, the read command sequence includes the read identification code, the memory address, and other information.
In the embodiment, the flash memory access circuit 220 also identifies the status of the logic blocks allocated to the rewritable nonvolatile memory module. The flash memory access circuit 220 can also recognize the status of the physical block of the rewritable nonvolatile memory module. More specifically, after the flash memory access circuit 220 issues a read/write request to the rewritable nonvolatile memory module according to the read/write command, the flash memory access circuit 220 identifies whether the state of the memory unit (e.g., the physical block, the physical page, or the corresponding logical block or the logical page) of the corresponding rewritable nonvolatile memory module is a ready state (ready). For example, when the flash access circuit 220 identifies a physical block corresponding to a read/write command to be ready for data transfer, the flash access circuit 220 reports the logical block mapped to the physical block as a ready status. In other words, the flash memory access circuit 220 determines whether the status of the logical block is ready according to whether the physical block mapped by the logical block is ready for data transmission. The flash memory access circuit 220 can actively determine whether the status of the corresponding physical block is ready for data transmission, and can also passively receive the status report of the corresponding physical block from the rewritable nonvolatile memory module.
The rewritable nonvolatile memory module of the flash memory 270 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory Cell), a Multi-Level Cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics. The memory cells in the rewritable nonvolatile memory module are arranged in an array.
In the present embodiment, the memory cells of the rewritable nonvolatile memory module form a plurality of physical programming units, and the physical programming units form a plurality of physical blocks (also called as physical erasing units). Specifically, memory cells on the same word line (or same word line layer) constitute one or more physical program cells. If each memory cell is used to store more than 2 bits, the physical program cells on the same word line (or the same word line layer) can be classified into at least a lower physical program cell and an upper physical program cell.
In one embodiment, if each memory cell is used to store 2 bits, the physical program cells on the same word line (or the same word line layer) can be classified into a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a cell belongs to the lower physical program unit, and the Most Significant Bit (MSB) of a cell belongs to the upper physical program unit. Generally, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell. In another embodiment, if each memory cell is used to store 3 bits, the physical program cells on the same word line (or the same word line layer) can be classified into a lower physical program cell, an upper physical program cell, and an additional (extra) physical program cell. For example, the least Significant Bit of a cell belongs to the lower physical program cell, the middle Significant Bit (CSB) of a cell belongs to the upper physical program cell, and the most Significant Bit of a cell belongs to the additional physical program cell.
In the present embodiment, data is used as a memory cell for writing data (program programming) in units of physical blocks. The physical blocks may also be referred to as physical erase cells or physical cells. The physical erase cell is the minimum unit of erase. That is, each physically erased cell contains one of the minimum number of memory cells that are erased. Each physical block has a plurality of physical programming units. The physical programming unit is a physical page (page) or a physical fan (sector). If the physical program cells are physical pages, the physical program cells usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., error correction codes).
However, the present invention is not limited thereto. For example, in another embodiment, the data transmission method described in this embodiment can also be applied to a rewritable nonvolatile memory module in which the physical programming unit is used as a unit for writing data.
The memory controller 200 is configured with a plurality of logical units for mapping a plurality of physical units of the rewritable nonvolatile memory module for storing user data, and a host system (not shown) accesses the user data in the plurality of physical units for storing user data through the logical units. Here, each logical unit may be composed of one or more logical addresses. For example, a logical unit may be a logical block, a logical page, or a logical sector. A logical unit may be mapped to one or more physical units, where a physical unit may be one or more physical addresses, one or more physical sectors, one or more physical programming units, or one or more physical erasing units.
In addition, the memory controller 200 establishes a logical to physical table (L2P table) and a physical to logical table (P2L table) to record a mapping relationship between logical units (e.g., logical blocks, logical pages, or logical sectors) and physical units (e.g., physical erase units, physical program units, physical sectors) allocated to the rewritable nonvolatile memory module. The logical-to-physical table is also called a logical-to-physical address mapping table. In other words, the memory controller 200 may search for the physical unit mapped by a logical unit through the logical-to-physical table, and the memory controller may search for the logical unit mapped by a physical unit through the physical-to-logical address mapping table. The logical-to-physical or physical-to-logical address mapping table may be temporarily stored in the SRAM 240 or the DRAM 280. However, the technical concepts related to the mapping of the logical units and the physical units are conventional in the art and will not be described herein.
In this embodiment, the flash memory access circuit 220 may further include a logic transition table update circuit 221 for automatically updating the logic transition table in the sram 240 or the dram 280 after the write command is executed.
FIG. 3 is a flowchart of a logic transition entity table updating method according to an embodiment of the present invention.
Referring to fig. 3, in step S301, a write command is transmitted to the flash memory access circuit 220 through the processor 210.
Specifically, the write instruction may include an operation code (op code), a physical address, a data source, and an update address of the random access memory. The random access memory may be static random access memory 240 or dynamic random access memory 280. The operation code represents the kind of operation to be performed. The physical address is the physical address at which the write command writes data to the flash memory 270. The data source records the logical unit where the write data corresponding to the write command is located. The update address of the random access memory records the address of the logical forwarding entity table in the random access memory to be updated.
In step S303, the flash memory 270 is accessed by the flash memory access circuit 220 executing a write command. Specifically, the flash memory access circuit 220 writes the write data corresponding to the data source to the physical address of the flash memory 270.
In step S305, after the flash memory access circuit 220 executes the write command, the logic transition table in the random access memory is updated by the flash memory access circuit 220. Specifically, after the flash memory access circuit 220 successfully writes the write data into the physical address of the flash memory 270, the logical-to-entity table update circuit 221 writes the physical address into the update address of the random access memory to complete the update operation of the logical-to-entity table.
Fig. 4A and 4B are schematic diagrams of updating a logical transition entity table according to an embodiment of the invention.
In FIG. 4A, the logical transition entity table 400 is recorded in an address field of the RAM, for example, an address field starting from 0x 4000. Each field of the logical-to-entity table 400 may be four bytes (bytes) to record the physical address corresponding to the logical unit. In the present embodiment, the logical units of the storage apparatus 20 are represented by Logical Block Addresses (LBAs), for example, the storage apparatus 20 includes logical units LBA (0), LBA (1), …, and LBA (n). Thus, address 0x4000 may correspond to LBA (0) and address 0x4000 records the physical address to which LBA (0) maps, address 0x4004 may correspond to LBA (1) and address 0x4004 records the physical address to which LBA (1) maps, and so on.
In FIG. 4B, assuming that the write command indicates that the data from LBA (7) is written to physical address A of the flash memory 270, the write command also includes the updated address of the logical-to-physical table in RAM, i.e., 0x 401C. After the flash memory access circuit 220 successfully writes the LBA (7) data to the physical address a of the flash memory 270, the logical-to-entity table update circuit 221 writes the physical address a to the address 0x401C in the random access memory to complete the update operation of the logical-to-entity table.
In summary, the logic-to-entity table updating method and the memory controller according to the present invention update the logic-to-entity table in the random access memory through the logic-to-entity table updating circuit in the flash memory access circuit after the flash memory access circuit executes the write command. Therefore, the flash memory access circuit does not need to transmit an interrupt signal to the processor after the write instruction is executed, and then the processor executes the firmware to update the logic transition table in the random access memory. The instruction execution speed can thus be increased, thereby improving the input-output operations per second of the system.
Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, and various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.
Claims (12)
1. A logic-to-entity table update method, adapted for a memory controller and a flash memory, the memory controller including a processor and a flash memory access circuit, the flash memory access circuit coupled to the flash memory, the logic-to-entity table update method comprising:
transferring, by the processor, a write instruction to the flash memory access circuit;
accessing the flash memory by the flash memory access circuitry executing the write instruction; and
after the flash memory access circuitry executes the write instruction, a table of logical transitionary entities in random access memory is updated by the flash memory access circuitry.
2. The logical transition entity table updating method of claim 1, wherein the processor finds the entity unit mapped by the logical unit through the logical transition entity table.
3. The logic transition entity table update method of claim 1, wherein the write command comprises a physical address, a data source, and an update address of the random access memory.
4. The logic transition entity table update method of claim 3, wherein the step of executing the write instruction by the flash memory access circuit comprises: writing data corresponding to the data source to the physical address of the flash memory by the flash memory access circuitry.
5. The logic transition table updating method according to claim 3, wherein the step of updating the logic transition table in the random access memory by the flash memory access circuit comprises: writing, by the flash memory access circuitry, the physical address to the update address of the random access memory.
6. The logic transition entity table update method of claim 1, wherein the random access memory is a Static Random Access Memory (SRAM) in the memory controller or a dynamic Random Access Memory (RAM) coupled to the memory controller.
7. A storage controller, comprising:
a processor; and
a flash memory access circuit coupled to the processor through a bus, wherein the flash memory access circuit is coupled to a flash memory, wherein
The processor transferring a write instruction to the flash memory access circuit;
the flash memory access circuit executes the write instruction to access the flash memory; and
after the flash memory access circuitry executes the write instruction, the flash memory access circuitry updates a table of logical transitionary entities in random access memory.
8. The storage controller of claim 7, wherein the processor looks up the entity unit mapped by the logical unit through the logical transition entity table.
9. The memory controller of claim 7, wherein the write command comprises a physical address, a data source, and an update address of the random access memory.
10. The memory controller of claim 9, wherein the flash memory access circuit writes data corresponding to the data source to the physical address of the flash memory.
11. The memory controller of claim 9, wherein the flash memory access circuit writes the physical address to the update address of the random access memory after the flash memory access circuit executes the write instruction.
12. The memory controller of claim 7, wherein the random access memory is a static random access memory in the memory controller or a dynamic random access memory coupled to the memory controller.
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