CN101604867A - The changing method of a kind of main power source and back-up source and commutation circuit - Google Patents
The changing method of a kind of main power source and back-up source and commutation circuit Download PDFInfo
- Publication number
- CN101604867A CN101604867A CNA2009100573286A CN200910057328A CN101604867A CN 101604867 A CN101604867 A CN 101604867A CN A2009100573286 A CNA2009100573286 A CN A2009100573286A CN 200910057328 A CN200910057328 A CN 200910057328A CN 101604867 A CN101604867 A CN 101604867A
- Authority
- CN
- China
- Prior art keywords
- pmos pipe
- main power
- source
- power source
- switch
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
- Tests Of Electronic Circuits (AREA)
Abstract
The present invention discloses the changing method and the commutation circuit of a kind of main power source and back-up source, comprises that main power switch, back-up source switch, first to fourth switch control logic, main power source testing circuit and switch controlling signal produce circuit.Main power switch comprises PMOS pipe and the 2nd PMOS pipe, and PMOS pipe and the 2nd PMOS pipe are series between main power source and the output node.The back-up source switch comprises the 3rd PMOS pipe and the 4th PMOS pipe, and the 3rd PMOS pipe and the 4th PMOS pipe are series between output node and the back-up source.Switch controlling signal produces circuit determines first to fourth PMOS pipe according to the input of main power source testing circuit conducting and ends.Produce the individual substrate of PMOS pipe by cross-linked mode, can avoid substrate leakage, can satisfy the needs that two series connection PMOS manage conducting respectively and end again.
Description
Technical field
The present invention relates to a kind of double power-supply system that has back-up source, particularly a kind of when main power source drops or recover, can finish the double power-supply system of seamless switching between main power source and the back-up source by control MOS switch.
Background technology
Along with development of science and technology, more and more equipments and precision instrument such as communication terminal device, bank computer system, surgical apparatus and the operate as normal of much measuring the highly sophisticated device of usefulness, all need continual stable working power, based on such requirement, these equipment and instrument often have two or more power supplys to be its power supply, one of them is a main power source, and all the other are auxiliary power.When system's operate as normal, provide internal system voltage by main power source usually, and auxiliary power and system disconnect; When power down appears in main power source, require to switch to auxiliary power, provide internal system voltage by auxiliary power, and main power source and system disconnect; When main power source recovers, switch back main power source by auxiliary power again, internal system voltage is provided, realize the uninterrupted power supply of system by this way.
Realize that the mode that duplicate supply switches is a lot, the most traditional mode is at major and minor power supply place, all adopts diode to power, but because this mode efficient is too low, uses limitedly, and the power supply switching mode that is had biswitch gradually replaces.It is little to adopt the MOS switch to have a conduction loss, is convenient to be integrated into the advantage in the sheet.MOS (metal-oxide semiconductor (MOS)) switch that is used for the power supply switching is generally the PMOS switch, also has minority to adopt nmos switch; The PMOS switch has the single switch of employing to realize, also has the series connection of employing biswitch to realize, enumerates real example concrete analysis below.
Chinese patent application 200420082475.1 provides a kind of dual power supply switching circuit of the PMOS of employing series connection biswitch, Fig. 1 illustrates the major part of its switch switching circuit, the substrate diode of PMOS series connection biswitch is connected into form back-to-back, the Switch Control logic is by two inverter M205, M207 and M206, M208, forms with door IC201B, IC201C and sample detecting IC circuit 202 and part discrete component for two.Directly inverter M205, the M207 of control switch and M206, M208 power supply are from the voltage of tandem tap common point.This type of attachment is when VSYS or VBAT end making alive, because the existence of the substrate parasitic diode of switch M201 and M204, external voltage can be transferred to the tandem tap common point, and that real controlled is switch M202 and M203.This patent also is to determine that by the state of judging main power source builtin voltage VDD is connected with VSYS or is connected with VBAT, under the normal mode, and VDD=VSYS; When the VSYS power down but VBAT just often, VDD=VBAT; When VSYS and the equal power down of VBAT, M201～M204 all ends, VDD=0.
The advantage one of above-mentioned patent is to have guaranteed that the output HIGH voltage of switch control logic gets the higher value of tandem tap two polygonal voltages all the time, can not have the threshold value leakage problem of the single switch of PMOS when turn-offing because of VSG＞Vth; The 2nd, because the substrate diode of PMOS series connection biswitch is connected into form back-to-back, there is not the substrate leakage problem.Yet the shortcoming one of this patent is M201 and M202, M203 and M204 tandem tap must be with opening with closing, otherwise the electric leakage by PMOS substrate parasitic diode may take place, for example during VDD=VBAT, if switch M202 closes, but switch M201 leaves, then when VDD＞VSYS, VDD can leak electricity to VSYS by the substrate diode of switch M202, and under some application-specific, may need non-like this with opening with the control logic of closing; The 2nd, when VDD was too low, the output of Switch Control circuit may not be correct, that is to say, even this moment, VSYS recovered, control circuit also may not provide correct information, switch is switched to VSYS power.
Summary of the invention
The present invention is directed to the shortcoming of existing switch switching mode, the method and the commutation circuit that provide a kind of twin-power switch to switch can realize switch control logic more flexibly.
The present invention solves the problems of the technologies described above the changing method that the technical scheme that adopts provides a kind of main power source and back-up source, detect the state of a main power source, one of them provides an output voltage to an output node to select this main power source and this back-up source according to this, and this commutation circuit comprises that main power switch, back-up source switch, first to fourth switch control logic, main power source testing circuit and switch controlling signal produce circuit.Main power switch comprises PMOS pipe and the 2nd PMOS pipe, and PMOS pipe and the 2nd PMOS pipe are series between this main power source and this output node.The back-up source switch comprises the 3rd PMOS pipe and the 4th PMOS pipe, and the 3rd PMOS pipe and the 4th PMOS pipe are series between this output node and this back-up source.First to fourth switch control logic is connected to the control end of described first to fourth PMOS pipe correspondingly, with the conducting of controlling first to fourth PMOS pipe with end.The main power source testing circuit relatively the sampled value of this main power voltage and a reference voltage to obtain a detection signal, when the sampled value of this main power source electricity during more than or equal to this reference voltage, this detection signal is first logic level, when the sampled value of this main power voltage during less than this reference voltage, this detection signal is second logic level.Switch controlling signal produces circuit and is connected between this main power source testing circuit and described first to fourth switch control logic, wherein this switch controlling signal generation circuit responds this first logic level and controls PMOS pipe and the conducting of the 2nd PMOS pipe, controlling the 3rd PMOS pipe ends with the 4th PMOS pipe, and switch controlling signal generation circuit responds this second logic level and controls PMOS pipe and end with the 2nd PMOS pipe, controls the 3rd PMOS pipe and manages conducting with the 4th PMOS.
On the other hand, the present invention proposes the changing method of a kind of main power source and back-up source, detect the state of a main power source, one of them provides an output voltage to an output node to select this main power source and this back-up source according to this, wherein a main power switch is connected between this main power source and this output node so that conductive path to be provided, one back-up source switch is connected between this back-up source and this output node so that conductive path to be provided, this main power switch comprises PMOS pipe and the 2nd PMOS pipe, and PMOS pipe and the 2nd PMOS pipe are series between this main power source and this output voltage; This back-up source switch comprises the 3rd PMOS pipe and the 4th PMOS pipe, and the 3rd PMOS pipe and the 4th PMOS pipe are series between this output node and this back-up source; This changing method comprises: relatively the voltage sample value of this main power source and a reference voltage are to produce a detection signal; When the voltage sample value of this main power source during more than or equal to this reference voltage, this detection signal is that first logic level is controlled PMOS pipe and the conducting of the 2nd PMOS pipe, controls the 3rd PMOS pipe and ends with the 4th PMOS pipe, makes this main power source that this output voltage is provided; When the sampled value of this main power voltage during less than this reference voltage, this detection signal is that second logic level is controlled PMOS pipe and ended with the 2nd PMOS pipe, controls the 3rd PMOS pipe and the conducting of the 4th PMOS pipe, makes this back-up source that this output voltage is provided.
In an embodiment of the present invention, at least one of above-mentioned first to fourth PMOS pipe has independently substrate.
In an embodiment of the present invention, above-mentioned independently substrate is by source terminal and the drain electrode end of two transistors cross couple to corresponding PMOS pipe.
In an embodiment of the present invention, power to this first switch control logic by this main power source; Power to second switch control logic and the 3rd switch control logic by this output voltage; Power to the 4th switch control logic by this back-up source.
In an embodiment of the present invention, the output voltage observation circuit is this output voltage and a predetermined voltage threshold relatively, when this output voltage during less than this predetermined voltage threshold, control PMOS pipe, the 3rd PMOS pipe and be independent of the logic level of this detection signal with the 4th PMOS pipe conducting, and keep the 2nd PMOS pipe to be controlled by this detection signal; When this output voltage during, make first to fourth PMOS pipe all be controlled by this detection signal more than or equal to this predetermined voltage threshold.
The present invention makes it compared with prior art owing to adopt above technical scheme, has following remarkable advantage:
1) each switch is controlled with independent switch control logic, can realize more flexibly, and is for example non-with opening with the control logic of closing;
2) reduced requirement, improved system reliability main power source VSYS and back-up source VBAT.VSYS at allowed band 0～3.3V with interior (employing be the CMOS technology of 3.3V), VBAT in allowed band 0～3.6V the time, normally power-on and power-off of switch switching circuit, and under the lower situation of VDD, owing to there be resetting of output voltage observation circuit, so, after powering on once more, system also is unlikely to run disorderly;
3) adopt cross-linked mode to produce the underlayer voltage of PMOS pipe, both avoided substrate leakage, solved again in the biswitch control, two tandem taps can not be when needed the conducting and the problem of ending respectively;
4) by the power supply of the corresponding control logic of each PMOS pipe of choose reasonable, guaranteed that when needs are closed, there is the threshold value leakage problem in tandem tap scarcely;
5) added electrify restoration circuit, the system that guaranteed is in first time power up, and switch switching circuit can reliably working.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Fig. 1 illustrates a kind of Switch Control circuit theory diagrams of prior art.
Fig. 2 illustrates switch switching circuit schematic diagram according to an embodiment of the invention.
Fig. 3 illustrates switch changing method flow chart according to an embodiment of the invention.
Fig. 4 illustrates the working waveform figure of switch switching circuit according to an embodiment of the invention.
Embodiment
Fig. 2 illustrates switch switching circuit schematic diagram according to an embodiment of the invention.With reference to shown in Figure 2, this commutation circuit comprises power supply biswitch, test section and Switch Control part.Specifically, the power supply biswitch comprises main power switch 10 and back-up source switch 11, and main power switch 10 is composed in series by PMOS pipe S0 and the 2nd PMOS pipe S1, so that the conductive path between main power source VSYS and the output node O to be provided; Back-up source switch 11 is composed in series by the 3rd PMOS pipe S2 and the 4th PMOS pipe S3, so that the conductive path between back-up source (as battery) VBAT and the output node O to be provided.Output node O is in order to output voltage V DD, and this output voltage can be used as the continual internal power source voltage of various power circuits.
In one embodiment, the substrate sub0 of PMOS pipe S0 produces by the cross-couplings form that transistor Q0 and transistor Q1 are connected into as shown in Figure 2.Similarly, PMOS manages S1, and the substrate of S2 and S3 is also produced by transistor Q2～Q7 by identical mode.
The test section comprises electrify restoration circuit (POR_VSYS) 19, comparison circuit 12, output voltage observation circuit (LBOR) 18 and reference circuit (LVREF) 20.Comparison circuit 12 and reference circuit 20 are formed the main power source testing circuit, comparison circuit 12 comprises hysteresis comparator (hysteresis comparator) and low pass filter (LPF), be a comparator circuit that has sluggish filter function, to increase the reliability of main power source testing circuit.Reference circuit 20 is low-power consumption reference circuits, is used to comparison circuit 12 that reference voltage and bias current are provided.The main power source testing circuit is sampled value and the reference voltage V REF of main power source VSYS relatively, produces and output detection signal vsysout, to determine first to fourth PMOS to manage the conducting of S0-S3 and to end.For example, when the sampled value of main power voltage VSYS during more than or equal to reference voltage V REF, detection signal vsysout is first logic level (as a low level), S0, S1 conducting and S2, S3 end, and system is powered by main power source VSYS; As the sampled value VSYS of main power voltage during less than reference voltage V REF, detection signal vsysout is second logic level (as a high level), S0, S1 by and S2, S3 conducting, system is powered by back-up source VBAT.
Output voltage observation circuit 18 is equivalent to a not single threshold testing circuit of tape base standard, has certain filter function, be used for when the output voltage V DD of system is lower than the minimum predetermined voltage threshold VL of circuit reliably working, send signal LBOR_rst, make PMOS pipe S0, S2 and S3 conducting, and be independent of the output valve vsysout of comparison circuit 12, and send systematic reset signal and give the CPU that is powered, when VDD is greater than or equal to VL, make switch S 0, S2 and S3 are subjected to the control of comparison circuit 12 again, and with the release that resets of above-mentioned CPU.
In addition, in one embodiment, electrify restoration circuit 19 be used for main power source VSYS power on for the first time finish before, and the VSYS power down is to threshold voltage (as 0.3V) when following, produce the reset signal of PMOS pipe S0, make the S0 conducting, and be independent of the output valve vsysout of comparison circuit 12.
Switch Control comprises that partly (S0_ctrl～S3_ctrl) and switch controlling signal produce circuit (sw_ctrl_generater) 17 to first to fourth switch control logic 13～16.What switch controlling signal produced circuit 17 is input as comparison circuit 12, the output signal of output voltage observation circuit 18 and electrify restoration circuit 19, and the output signal that switch controlling signal produces circuit 17 is sent to first to fourth switch control logic 13～16.First to fourth switch control logic 13～16 is used for directly controlling the conducting of first to fourth PMOS pipe S0～S3 and ending, its output is respectively a0～a3, be sent to the grid control end of first to fourth PMOS pipe S0～S3, when a0～a3 is low level, the conducting of corresponding PMOS pipe, when a0～a3 was high level, corresponding PMOS pipe ended.This each PMOS pipe is allowed to control more flexibly by the mode of independent switch control logic control.
It should be noted that, first to fourth PMOS pipe S0～S3 all produces independently substrate with the cross-couplings mode, this mode can guarantee that underlayer voltage is in the high value in each switch ends voltage at any time all the time, avoided substrate leakage, this also helps to prevent to connect the non-same electric leakage that may exist when closing together of opening of biswitch (as S0, S1).In addition, in one embodiment, the power supply of first switch control logic 13 links to each other with main power source VSYS, and the power supply of the 4th switch control logic 16 links to each other with back-up source VBAT, and the power supply of the second and the 3rd switch control logic 14,15 is all from output voltage V DD.Choose power supply in this manner, can guarantee to connect biswitch when needs turn-off, exist threshold value to reveal scarcely.
The principle of switch switching circuit shown in Figure 2 can contrast the switch changing method flow chart of Fig. 3 and describe:
Under the normal mode of operation, the output of electrify restoration circuit (POR_VSYS) 19 and output voltage observation circuit (LBOR) 18 is high level, switch control logic 13～16 there is not influence, and comparison circuit 12 compares (step S10) by sampled value and benchmark VREF with main power source VSYS, output low level, and this output produced circuit 17 through switch controlling signal and switch control logic 13～16 makes first and second PMOS pipe S0 and S1 conducting simultaneously, third and fourth PMOS pipe S2 and S3 are by (step S12), and the output voltage V DD of system is provided by main power source VSYS.
When main power source VSYS power down is arrived certain below the preset threshold VH (as 2.8V), the output of comparison circuit 12 is uprised by low, make third and fourth PMOS pipe S2 and S3 conducting simultaneously, first and second PMOS pipe S0 and S1 are by (step S16), the output voltage V DD of system is provided by battery supply VBAT (supposing that battery supply VBAT is normal at this moment), and system is in low-power consumption mode.Under battery powered mode, return to certain more than the preset threshold VH (as 2.8V) when detecting main power source VSYS, the output of comparison circuit 12 is by high step-down, make first and second PMOS pipe S0 and S1 conducting simultaneously, third and fourth PMOS pipe S2 and S3 end, and the output voltage V DD of system is switched back by main power source VSYS by battery supply VBAT to be provided; Under battery powered mode, do not recover when detecting main power source VSYS, and detecting VBAT in step S14 drops to and makes VDD be lower than VL, triggered output voltage observation circuit 18, make its output by high step-down, then system resets, simultaneously, output voltage observation circuit 18 makes PMOS pipe S0, S2 and S3 conducting and no matter why the output of comparison circuit 12 is worth (promptly being independent of the output of comparison circuit 12) (step S18), at this moment, the output of comparison circuit 12 can only be used to control the 2nd PMOS pipe S1, makes S1 still be in cut-off state; System is in reset mode following time, if main power source VSYS recovers, because S1 closes but the S0 conducting, makes the V of S1
SG＞V
THSo S1 exists threshold value to reveal, but the threshold value of this moment is revealed and is wished, it can cause the rising of output voltage V DD, 18 outputs of output voltage observation circuit are uprised by low, all PMOS pipes begin to be subjected to comparison circuit 12 again and directly control, when main power source VSYS rises to certain more than the preset threshold VH (as 2.8V), and output voltage V DD rise to comparison circuit 12 and reference circuit 20 all can operate as normal after, its output makes first and second PMOS pipe S0 and S1 conducting simultaneously, third and fourth PMOS pipe S2 and S3 are by (step S12), and system gets back to normal mode of operation again, and the output voltage V DD of system is provided by main power source VSYS; System is in reset mode following time, main power source VSYS does not recover, but battery supply VBAT returns to VL when above, 18 outputs of output voltage observation circuit are uprised by low, first to fourth PMOS pipe S0-S4 begins to be subjected to comparison circuit 12 again and directly controls, its output makes third and fourth PMOS pipe S2 and S3 conducting simultaneously, and first and second PMOS pipe S0 and S1 end, and the output voltage V DD of system is provided by battery supply VBAT; System is in reset mode following time, if main power source VSYS does not recover, and battery supply VBAT do not return to more than the VL yet, and system will be in reset mode always.
Fig. 4 is the working waveform figure of corresponding diagram 2 switching systems, wherein, VSYS is a main power source, VBAT is a back-up source, VDD is the continual output voltage of system, LBOR_rst is the output of output voltage observation circuit 18 among Fig. 3, VL is the detection threshold of output voltage observation circuit, vsysout is the output of main power source testing circuit (further being comparison circuit 12), VH is the detection threshold of comparison circuit 12, a0～a3 is respectively the direct control signal of first to fourth PMOS pipe S0～S3, when a0～a3 is low level, and corresponding switch conduction.Because electrify restoration circuit (POR_VSYS) 19 is mainly used in the reliability that guarantees that switch switching circuit powers on for the first time, if existing supposition main power source VSYS is after powering on, be higher than 0.3V always, then the output of electrify restoration circuit 19 is high always, and switch switching circuit is not had influence (do not give and drawing) herein.
In the above embodiment of the present invention, comparison circuit 12, output voltage observation circuit 18 and electrify restoration circuit 19 are to realize by the internal logic of switch controlling signal generation circuit 17 to the control of each PMOS pipe.Switch controlling signal produces circuit 17 and comprises some combinational logics and level shift circuit, according to the control requirement of comparison circuit in the foregoing description 12, output voltage observation circuit 18 and electrify restoration circuit 19, the combining form of these combinational logics and level shift circuit can have multiple design.These modes all are well known to those skilled in the art, and therefore no longer launch narration at this.The design that switch controlling signal produces circuit 17 should guarantee to satisfy the correctness of switching circuit switching and the quiescent dissipation of system.
In sum, innovative point of the present invention is mainly reflected in following four aspects:
1) reduced requirement, improved system reliability main power source VSYS and back-up source VBAT.VSYS at allowed band 0～3.3V with interior (employing be the CMOS technology of 3.3V), VBAT in allowed band 0～3.6V the time, normally power-on and power-off of switch switching circuit, and under the lower situation of VDD, owing to there be resetting of output voltage observation circuit, so, after powering on once more, system also is unlikely to run disorderly;
2) adopt cross-linked mode to produce the underlayer voltage of PMOS pipe, both avoided substrate leakage, solved again in the biswitch control, two tandem taps can not be when needed the conducting and the problem of ending respectively;
3) by the power supply of the corresponding control logic of each PMOS pipe of choose reasonable, guaranteed that when needs are closed, there is the threshold value leakage problem in tandem tap scarcely;
4) added electrify restoration circuit, the system that guaranteed is in first time power up, and switch switching circuit can reliably working.
Described as above-mentioned embodiment, be the cardinal principle framework and the system works principle of switch switching circuit of the present invention and method, and the physical circuit of each module does not provide, because as long as come design circuit based on above-mentioned thought, the form of each module can be various, is as the criterion can reach application requirements.In addition, though the present invention do not describe in detail relevant since the power supply of the present invention and chip switches, so those skilled in the art should understand the design that can dissolve in ESD (Electro-Static discharge, static release) in design.
Claims (12)
1. the commutation circuit of main power source and back-up source detects the state of a main power source, and one of them provides an output voltage to an output node to select this main power source and this back-up source according to this, and this commutation circuit comprises:
Main power switch comprises PMOS pipe and the 2nd PMOS pipe, and PMOS pipe and the 2nd PMOS pipe are series between this main power source and this output node;
The back-up source switch comprises the 3rd PMOS pipe and the 4th PMOS pipe, and the 3rd PMOS pipe and the 4th PMOS pipe are series between this output node and this back-up source;
First to fourth switch control logic is connected to the control end of described first to fourth PMOS pipe correspondingly, with the conducting of controlling first to fourth PMOS pipe with end;
The main power source testing circuit, be used for the sampled value of this main power voltage is compared with a reference voltage to obtain a detection signal, when the sampled value of this main power voltage during more than or equal to this reference voltage, this detection signal is first logic level, when the sampled value of this main power voltage during less than this reference voltage, this detection signal is second logic level; And
Switch controlling signal produces circuit, be connected between this main power source testing circuit and described first to fourth switch control logic, wherein this switch controlling signal generation circuit responds this first logic level and controls PMOS pipe and the conducting of the 2nd PMOS pipe, controlling the 3rd PMOS pipe ends with the 4th PMOS pipe, and switch controlling signal generation circuit responds this second logic level and controls PMOS pipe and end with the 2nd PMOS pipe, controls the 3rd PMOS pipe and manages conducting with the 4th PMOS.
2. the commutation circuit of main power source as claimed in claim 1 and back-up source is characterized in that,
At least one of described first to fourth PMOS pipe has independently substrate.
3. the commutation circuit of main power source as claimed in claim 2 and back-up source is characterized in that,
Described independently substrate is by source terminal and the drain electrode end of two transistors cross couple to corresponding PMOS pipe.
4. the commutation circuit of main power source as claimed in claim 1 and back-up source is characterized in that, this first switch control logic is by this main power source power supply; This second switch control logic and the 3rd switch control logic are by this output voltage power supply; The 4th switch control logic is by this back-up source power supply.
5. the commutation circuit of main power source as claimed in claim 1 and back-up source, it is characterized in that, described commutation circuit also comprises an output voltage observation circuit, be used for this output voltage is compared with a predetermined voltage threshold, when this output voltage during, export a reset signal less than this predetermined voltage threshold;
This switch controlling signal produces circuit and connects this output voltage observation circuit, and respond this reset signal, control PMOS pipe, the 3rd PMOS pipe and be independent of the logic level of this detection signal with the 4th PMOS pipe conducting, and keep the 2nd PMOS pipe to be controlled by this detection signal.
6. the commutation circuit of main power source as claimed in claim 1 and back-up source, it is characterized in that, described commutation circuit also comprises an electrify restoration circuit, be used for powering on for the first time and finish preceding or be lower than a threshold voltage when following at main power voltage at main power source, produce PMOS pipe reset signal, wherein switch controlling signal produces circuit and responds PMOS pipe reset signal, controls PMOS pipe conducting and is independent of the logic level of this detection signal.
7. the commutation circuit of main power source as claimed in claim 1 and back-up source is characterized in that, this main power source testing circuit comprises the comparator with sluggish filter function.
8. the changing method of main power source and back-up source, detect the state of a main power source, one of them provides an output voltage to an output node to select this main power source and this back-up source according to this, wherein a main power switch is connected between this main power source and this output node so that conductive path to be provided, one back-up source switch is connected between this back-up source and this output node so that conductive path to be provided, this main power switch comprises PMOS pipe and the 2nd PMOS pipe, and PMOS pipe and the 2nd PMOS pipe are series between this main power source and this output node; This back-up source switch comprises the 3rd PMOS pipe and the 4th PMOS pipe, and the 3rd PMOS pipe and the 4th PMOS pipe are series between this output node and this back-up source; This changing method comprises:
Relatively the voltage sample value of this main power source and a reference voltage are to produce a detection signal;
When the voltage sample value of this main power source during more than or equal to this reference voltage, this detection signal is that first logic level is controlled PMOS pipe and the conducting of the 2nd PMOS pipe, controls the 3rd PMOS pipe and ends with the 4th PMOS pipe, makes this main power source that this output voltage is provided;
When the sampled value of this main power voltage during less than this reference voltage, this detection signal is that second logic level is controlled PMOS pipe and ended with the 2nd PMOS pipe, controls the 3rd PMOS pipe and the conducting of the 4th PMOS pipe, makes this back-up source that this output voltage is provided.
9. the changing method of main power source as claimed in claim 8 and back-up source is characterized in that, also comprises:
Relatively this output voltage and a predetermined voltage threshold, when this output voltage during less than this predetermined voltage threshold, control PMOS pipe, the 3rd PMOS pipe and be independent of the logic level of this detection signal with the 4th PMOS pipe conducting, and keep the 2nd PMOS pipe to be controlled by this detection signal; When this output voltage during, make first to fourth PMOS pipe all be controlled by this detection signal more than or equal to this predetermined voltage threshold.
10. the changing method of main power source as claimed in claim 8 and back-up source is characterized in that,
At least one of described first to fourth PMOS pipe has independently substrate.
11. the changing method of main power source as claimed in claim 10 and back-up source is characterized in that,
Described independently substrate is by source terminal and the drain electrode end of two transistors cross couple to corresponding PMOS pipe.
12. the changing method of main power source as claimed in claim 11 and back-up source is characterized in that, powers to this first switch control logic by this main power source; Power to second switch control logic and the 3rd switch control logic by this output voltage; Power to the 4th switch control logic by this back-up source.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100573286A CN101604867B (en) | 2009-05-27 | 2009-05-27 | Method for switching main power supply and backup power supply and switching circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100573286A CN101604867B (en) | 2009-05-27 | 2009-05-27 | Method for switching main power supply and backup power supply and switching circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101604867A true CN101604867A (en) | 2009-12-16 |
| CN101604867B CN101604867B (en) | 2011-05-11 |
Family
ID=41470464
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009100573286A Expired - Fee Related CN101604867B (en) | 2009-05-27 | 2009-05-27 | Method for switching main power supply and backup power supply and switching circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101604867B (en) |
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130492A (en) * | 2010-07-31 | 2011-07-20 | 华为技术有限公司 | Device and method for selecting power supply |
| WO2013127335A1 (en) * | 2012-02-28 | 2013-09-06 | International Business Machines Corporation | Low-voltage differential signal receiver |
| CN104882956A (en) * | 2014-02-28 | 2015-09-02 | 北京谊安医疗系统股份有限公司 | Multi-power switching circuit and anaesthesia machine with multi-power switching circuit |
| CN104949775A (en) * | 2015-06-30 | 2015-09-30 | 成都众山科技有限公司 | Wireless pressure transmitter based on Internet of Things |
| CN105449831A (en) * | 2014-06-13 | 2016-03-30 | 钜泉光电科技(上海)股份有限公司 | Main-auxiliary power supply automatic switching system and method |
| WO2016090761A1 (en) * | 2014-12-09 | 2016-06-16 | Gd Midea Heating & Ventilating Equipment Co., Ltd. | Back-up power source apparatus in indoor unit, controlling method thereof and multi-split air conditioning system |
| CN106134081A (en) * | 2014-04-18 | 2016-11-16 | 矢崎总业株式会社 | Load driving circuits |
| CN106230099A (en) * | 2015-06-02 | 2016-12-14 | Ls产电株式会社 | Power-supply device |
| CN106406179A (en) * | 2016-10-31 | 2017-02-15 | 山东康威通信技术股份有限公司 | Modularly-designed multi-interface host, control system comprising same, and control method |
| CN106997097A (en) * | 2016-01-22 | 2017-08-01 | 三星电子株式会社 | Electronic equipment and for the method for the electric power for controlling the electronic equipment |
| CN107204774A (en) * | 2017-05-11 | 2017-09-26 | 成都华微电子科技有限公司 | Support the cold standby system high-impedance state High Linear sampling hold circuit of multichannel input |
| CN108899991A (en) * | 2018-07-20 | 2018-11-27 | 上海东软载波微电子有限公司 | Power supply automatic switchover circuit |
| CN109474060A (en) * | 2018-12-19 | 2019-03-15 | 电子科技大学中山学院 | Dual-power switching system and switching method |
| CN110518687A (en) * | 2019-08-06 | 2019-11-29 | 成都锐成芯微科技股份有限公司 | A kind of power supply automatic switchover circuit |
| CN111443644A (en) * | 2020-04-29 | 2020-07-24 | 深圳市道通科技股份有限公司 | OBD power control management system and OBD monitor terminal |
| CN114397957A (en) * | 2022-01-15 | 2022-04-26 | 上海列拓科技有限公司 | Low-power-consumption power management circuit for MCU chip, and MCU chip |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI813070B (en) * | 2021-11-16 | 2023-08-21 | 瑞昱半導體股份有限公司 | Power supplying circuit and power supplying method |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH10271710A (en) * | 1997-03-28 | 1998-10-09 | Mitsubishi Electric Corp | Power source transfer circuit |
| JP4302070B2 (en) * | 2005-02-25 | 2009-07-22 | Ｏｋｉセミコンダクタ株式会社 | Power supply switching circuit, microcomputer, portable terminal device, and power supply switching control method |
-
2009
- 2009-05-27 CN CN2009100573286A patent/CN101604867B/en not_active Expired - Fee Related
Cited By (27)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102130492A (en) * | 2010-07-31 | 2011-07-20 | 华为技术有限公司 | Device and method for selecting power supply |
| US8751846B2 (en) | 2010-07-31 | 2014-06-10 | Huawei Technologies Co., Ltd. | Power supply selector and power supply selection method |
| CN102130492B (en) * | 2010-07-31 | 2015-05-27 | 华为技术有限公司 | Device and method for selecting power supply |
| WO2013127335A1 (en) * | 2012-02-28 | 2013-09-06 | International Business Machines Corporation | Low-voltage differential signal receiver |
| CN103296984A (en) * | 2012-02-28 | 2013-09-11 | 国际商业机器公司 | LVDS (low-voltage differential signaling) receiver |
| CN104882956B (en) * | 2014-02-28 | 2018-11-13 | 北京谊安医疗系统股份有限公司 | More power supply switch circuits and Anesthesia machine with it |
| CN104882956A (en) * | 2014-02-28 | 2015-09-02 | 北京谊安医疗系统股份有限公司 | Multi-power switching circuit and anaesthesia machine with multi-power switching circuit |
| CN106134081A (en) * | 2014-04-18 | 2016-11-16 | 矢崎总业株式会社 | Load driving circuits |
| CN106134081B (en) * | 2014-04-18 | 2019-01-15 | 矢崎总业株式会社 | Load driving circuits |
| CN105449831A (en) * | 2014-06-13 | 2016-03-30 | 钜泉光电科技(上海)股份有限公司 | Main-auxiliary power supply automatic switching system and method |
| CN105449831B (en) * | 2014-06-13 | 2019-03-01 | 钜泉光电科技(上海)股份有限公司 | A kind of major-minor power source automatic switching system and method |
| WO2016090761A1 (en) * | 2014-12-09 | 2016-06-16 | Gd Midea Heating & Ventilating Equipment Co., Ltd. | Back-up power source apparatus in indoor unit, controlling method thereof and multi-split air conditioning system |
| CN106230099A (en) * | 2015-06-02 | 2016-12-14 | Ls产电株式会社 | Power-supply device |
| CN106230099B (en) * | 2015-06-02 | 2019-07-19 | Ls 产电株式会社 | Power-supply device |
| CN104949775A (en) * | 2015-06-30 | 2015-09-30 | 成都众山科技有限公司 | Wireless pressure transmitter based on Internet of Things |
| CN106997097A (en) * | 2016-01-22 | 2017-08-01 | 三星电子株式会社 | Electronic equipment and for the method for the electric power for controlling the electronic equipment |
| CN106406179B (en) * | 2016-10-31 | 2019-02-15 | 山东康威通信技术股份有限公司 | The multiplex roles host of modularized design, control system and method including the host |
| CN106406179A (en) * | 2016-10-31 | 2017-02-15 | 山东康威通信技术股份有限公司 | Modularly-designed multi-interface host, control system comprising same, and control method |
| CN107204774A (en) * | 2017-05-11 | 2017-09-26 | 成都华微电子科技有限公司 | Support the cold standby system high-impedance state High Linear sampling hold circuit of multichannel input |
| CN107204774B (en) * | 2017-05-11 | 2020-11-06 | 成都华微电子科技有限公司 | High-resistance high-linearity sampling and holding circuit of cold backup system supporting multi-channel input |
| CN108899991A (en) * | 2018-07-20 | 2018-11-27 | 上海东软载波微电子有限公司 | Power supply automatic switchover circuit |
| CN109474060A (en) * | 2018-12-19 | 2019-03-15 | 电子科技大学中山学院 | Dual-power switching system and switching method |
| CN109474060B (en) * | 2018-12-19 | 2021-06-29 | 电子科技大学中山学院 | Dual power supply switching system and switching method |
| CN110518687A (en) * | 2019-08-06 | 2019-11-29 | 成都锐成芯微科技股份有限公司 | A kind of power supply automatic switchover circuit |
| CN110518687B (en) * | 2019-08-06 | 2023-05-30 | 成都锐成芯微科技股份有限公司 | Automatic switching circuit of power supply |
| CN111443644A (en) * | 2020-04-29 | 2020-07-24 | 深圳市道通科技股份有限公司 | OBD power control management system and OBD monitor terminal |
| CN114397957A (en) * | 2022-01-15 | 2022-04-26 | 上海列拓科技有限公司 | Low-power-consumption power management circuit for MCU chip, and MCU chip |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101604867B (en) | 2011-05-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101604867B (en) | Method for switching main power supply and backup power supply and switching circuit | |
| CN211086970U (en) | Multi-power-supply up-down control circuit | |
| EP2680104B1 (en) | A CMOS power backup switching circuit and method for operating a CMOS power backup switching circuit | |
| US9966793B2 (en) | Supply-switching system | |
| EP3550723B1 (en) | Pad tracking circuit for high-voltage input-tolerant output buffer | |
| EP1882306B1 (en) | Integrated circuit, electronic device and integrated circuit control method | |
| US7902914B2 (en) | Semiconductor integrated circuit | |
| TW515137B (en) | CMOS low leakage operation of real-time clock | |
| US20070035183A1 (en) | Power supply circuit | |
| JP6288822B2 (en) | System and method for controlling power in a semiconductor circuit | |
| CN109194126B (en) | Power supply switching circuit | |
| JP6297758B1 (en) | Self-detection type reverse current protection switch | |
| US9287875B2 (en) | Load switch for controlling electrical coupling between power supply and load | |
| US8742829B2 (en) | Low leakage digital buffer using bootstrap inter-stage | |
| US10620676B1 (en) | Wake-up control circuit for power-gated integrated circuits | |
| US20100244911A1 (en) | Supply circuitry for sleep mode | |
| CN109818411B (en) | Power switch circuit, chip and power supply system suitable for power supply sudden change | |
| US20090167359A1 (en) | Current mode logic circuit and control apparatus therefor | |
| US8230251B2 (en) | Time sequence control circuit | |
| US7688121B2 (en) | Power supply voltage detection circuit | |
| US8653882B2 (en) | Controlling over voltage on a charge pump power supply node | |
| CN219436662U (en) | Power supply monitoring circuit, power supply management system and storage main control chip | |
| CN104137416B (en) | Voltage detecting circuit and electronic circuit | |
| KR100715601B1 (en) | Power-on reset circuit | |
| TW202327210A (en) | Glitch free brown out detector |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20110511 Termination date: 20180527 |