CN101604656A

CN101604656A - A kind of PN junction partition method that is suitable for power supply polarity reversal

Info

Publication number: CN101604656A
Application number: CNA2009103048158A
Authority: CN
Inventors: 陈奕星
Original assignee: HUNAN LIHU MICRO-ELECTRONICS Co Ltd
Current assignee: HUNAN LIHU MICRO-ELECTRONICS Co Ltd
Priority date: 2009-07-24
Filing date: 2009-07-24
Publication date: 2009-12-16

Abstract

The invention discloses a kind of PN junction partition method that is suitable for power supply polarity reversal.It may further comprise the steps: in P type substrate bipolar process, open two N-epitaxial loayer windows between the P+ buried layer, inject N+ on the N-epitaxial loayer, inject N+ from two and draw two metal end.The mode that the present invention adopts the diode switching electric potential has solved the isolation technology problem of the semiconductor element of power supply polarity reversal for the semiconductor element of power supply polarity reversal provides a kind of partition method cheaply.

Description

A kind of PN junction partition method that is suitable for power supply polarity reversal

Technical field

The present invention relates to a kind of method of isolation of semiconductor element, particularly a kind of PN junction partition method that is suitable for power supply polarity reversal.

Background technology

In the integrated circuit structure, isolate in order to realize the electricity between the element, generally adopt the PN junction isolation technology, P type substrate connects electronegative potential, and N type substrate connects maximum potential.Utilize the electricity between two solid existing elements of anti-pn partially that exist between isolated island or the trap to isolate.The isolation of bipolar process as shown in Figure 1.Among the figure, VDD and VSS represent maximum potential and potential minimum respectively, PSUB is a P type substrate, P+ is a P type buried layer, and N-is an epitaxial loayer, and N+ is the N+ implanted layer, help external pin better to contact with N-, the X1 representative is with all kinds of devices of epitaxial loayer as a device part, and X2 represents resistance, and the residing N-epitaxial loayer of X2 has promptly formed the resistance trap.The isolation of CMOS or BICMOS technology as shown in Figure 2.Among the figure, VDD and VSS represent maximum potential and potential minimum respectively, and PSUB is a P type substrate, and NWELL is the N trap that N-forms, and N+ and P+ are respectively that N+ injects and the P+ injection, and NMOSs and PMOSs then represent N type device on the P substrate and the P type device in the N trap respectively.The isolation of twin well processs such as BCD as shown in Figure 3.Among the figure, VDD and VSS represent maximum potential and potential minimum respectively, and PSUB is the P substrate, and PWELL and NWELL are respectively the P trap and the N trap of P-and N-formation, N+ and P+ are respectively that N+ injects and the P+ injection, and X1 and X2 then represent N type device in the P trap and the P type device in the N trap respectively.

Yet in some specific application scenario, circuit does not exist fixing power supply and ground, and perhaps in use, the situation of polarity inversion will appear in power supply and earth potential.At this moment, owing to can't provide fixing current potential to substrate and isolated island or trap, can not guarantee that two PN junctions between isolated island or the trap are anti-inclined to one side, cause isolated failure, circuit can't be integrated.

Summary of the invention

Isolate the above-mentioned technical problem that semiconductor element exists in the time of can't determining in order to solve power supply, the invention provides a kind of PN junction partition method that is suitable for power supply polarity reversal.When adopting the present invention that operating voltage polarity is changed, still can guarantee the PN junction isolation effectively.

The technical scheme that the present invention solves the problems of the technologies described above may further comprise the steps: in P type substrate bipolar process, open two N-epitaxial loayer windows between the P+ buried layer, inject N+ on the N-epitaxial loayer, inject N+ from two and draw two metal end.

A kind of PN junction partition method that is suitable for power supply polarity reversal, may further comprise the steps: in P type substrate and CMOS or BICMOS technology, on the P substrate, do two N traps, in the N trap, inject N+, all inject around two N traps and do isolation, inject N+ from two and draw two metal end with P+.

A kind of PN junction partition method that is suitable for power supply polarity reversal, may further comprise the steps: in P type substrate BJT resistance trap or CMOS or BICMOSN trap technology, on the N trap, do two P+ injection rings, on P+ injection ring and N-epitaxial loayer wherein, cover metal level, cover metal level from two and draw two metal end.

A kind of PN junction partition method that is suitable for power supply polarity reversal may further comprise the steps: do two N+ implanted layers in the P trap on P type substrate, be close to the N+ injection and do the P+ injection, inject N+ from two and draw two metal end; Do two P+ injection rings in the N trap on P type substrate, on P+ injection ring and N-epitaxial loayer wherein, cover metal level, cover metal level from two and draw two metal end.

Technique effect of the present invention is: the mode that the present invention adopts the diode switching electric potential has solved the isolation technology problem of the semiconductor element of power supply polarity reversal for the semiconductor element of power supply polarity reversal provides a kind of partition method cheaply.

The present invention is further illustrated below in conjunction with accompanying drawing.

Description of drawings

Fig. 1 is the isolation diagram of bipolar process.

Fig. 2 is the isolation diagram of CMOS or BICMOS technology.

Fig. 3 is the isolation diagram of twin well process such as BCD.

Fig. 4 is the biasing of the substrate in bipolar process, CMOS or the BICMOS technology among the present invention

Fig. 5 is the biasing of the N trap in resistance trap, CMOS or the BICMOS technology among the present invention

Fig. 6 is connected as figure for the current potential of P trap and N trap in the twin well process among the present invention.

Referring to Fig. 4,, connect as Fig. 4 for the biasing of the substrate in bipolar process, CMOS or the BICMOS technology.In BJT technology, do two isolated islands in addition for two pins of polarity inversion, promptly between the P+ buried layer, open two N-epitaxial loayer windows, like this, P+ and N-have just formed the PN junction diode.For two N-better are connected with extraneous pin, on N-, inject N+, lead to A pin and B pin by metal M 1 with M2 afterwards.A just links to each other with two N-respectively with the B pin like this.In CMOS or BICMOS technology, at first be that two pins are done two less N traps on the P substrate, in the N trap, be N+ and inject the improvement connection, all inject around two N traps and does isolation with P+, P+ and N-have just formed the PN junction diode like this.And two N-are connected with the B pin with the A pin respectively with M2 by N+ injection and M1.

Wherein A and B are the outer pins of lead-out tablet, promptly are the high-low level pins that polarity inversion can occur, and the two is anti-phase, and any moment must have one for high, and one is low.

Suppose that A is a high level and B is a low level, then the N+ of B place also is low, be that N-is low, the PN junction critical conduction that forms of P+ and N-then, substrate electric potential is only than the high PN junction forward critical conduction voltage in B place (about 0.5V), for low, and the A point is a high level, then N+ of A place and N-are all height, and the PN junction that P+ and N-form is anti-inclined to one side, do not influence the operating state of circuit.For other circuit, because the B point is a potential minimum, do not have lower current potential, therefore the phenomenon of parasitic PN junction conducting can not appear.

For the biasing of the N trap in resistance trap, CMOS or the BICMOS technology, as Fig. 5.In BJT technology, the resistance trap is to realize by do N-epitaxial loayer isolated island between the P buried layer on the PSUB.In CMOS or BICMOS technology, the N trap is that the N-that is grown directly upon on the substrate injects.The two all is that N-injects the trap that forms.For this N type trap being connected to the high potential pin among A and the B, at first on N type trap, do two P+ injection rings that area is less, P+ and N-in the ring form the PN junction diode.Cover metal level then on P+ injection ring and N-epitaxial loayer wherein, metal level and N-have just formed Schottky diode like this.And the ring of P+ before can improve the puncture voltage of Schottky diode and improve its on state characteristic.Two metal M 1 link to each other with the B pin with the A pin respectively with M2.A and B are anti-phase.Suppose that A is that high B is low, the then Schottky diode conducting at A place, the PN junction that N-and P+ form is anti-inclined to one side, not conducting, and reversed bias voltage narrows down the PN junction depletion region; And the Schottky diode at B place ends, and P+ and B are all electronegative potential, and the PN junction depletion region that N-and P+ form is with broadening and block contacting of B point and epitaxial loayer.The Schottky diode conduction level is less than 0.5V, and then the N trap is biased to high level.

In conjunction with the bias mode to P substrate and N trap, the P trap is connected as Fig. 6 with the current potential of N trap in the twin well process.Be that two pins are done two N+ injections in the P trap,, inject the formation PN junction with N+ because the trap that does not have N-to form at this moment need be close to the N+ injection and do the P+ injection.Two N+ join with A pin and B pin respectively by metal M 1 and M2 equally.Like this, suppose that A is low for height B, the then PN junction conducting at B place, P+ links to each other with the P trap, makes the P trap receive potential minimum.And the PN junction at A place is anti-inclined to one side, and circuit is not exerted an influence.For the N trap, equally at first in the N trap, do two P+ rings that area is little, make P+ and N-form diode.Cover metal M 3, M4 on the N-in P+ ring and ring thereof.Like this, M3 and M4 just with its under N-form Schottky diode.M3, M4 also join with A pin and B pin respectively.Suppose that A is low for height B, the then Schottky diode conducting at A place, the PN junction that N-and P+ form is anti-inclined to one side, not conducting, and reversed bias voltage narrows down the PN junction depletion region; And the Schottky diode at B place ends, and the PN junction depletion region that N-and P+ form is with broadening and block contacting of B point and epitaxial loayer.The Schottky diode conduction level is less than 0.5V, and then the N trap is biased to high level.

Claims

1. a PN junction partition method that is suitable for power supply polarity reversal may further comprise the steps: in P type substrate bipolar process, open two N-epitaxial loayer windows between the P+ buried layer, inject N+ on the N-epitaxial loayer, inject N+ from two and draw two metal end.

2. PN junction partition method that is suitable for power supply polarity reversal, may further comprise the steps: in P type substrate and CMOS or BICMOS technology, on the P substrate, do two N traps, in the N trap, inject N+, all inject around two N traps and do isolation, inject N+ from two and draw two metal end with P+.

3. PN junction partition method that is suitable for power supply polarity reversal, may further comprise the steps: in BJT resistance trap or CMOS or BICMOSN trap technology, on the N trap, do two P+ injection rings, on P+ injection ring and N-epitaxial loayer wherein, cover metal level, cover metal level from two and draw two metal end.

4. a PN junction partition method that is suitable for power supply polarity reversal may further comprise the steps: in twin well process, do two N+ implanted layers in the P trap on P type substrate, be close to the N+ injection and do the P+ injection, inject N+ from two and draw two metal end; Do two P+ injection rings in the N trap on P type substrate, on P+ injection ring and N-epitaxial loayer wherein, cover metal level, cover metal level from two and draw two metal end.