CN101599493A - A kind of based on nanocrystalline non-volatility memorizer - Google Patents
A kind of based on nanocrystalline non-volatility memorizer Download PDFInfo
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- CN101599493A CN101599493A CNA2009100553899A CN200910055389A CN101599493A CN 101599493 A CN101599493 A CN 101599493A CN A2009100553899 A CNA2009100553899 A CN A2009100553899A CN 200910055389 A CN200910055389 A CN 200910055389A CN 101599493 A CN101599493 A CN 101599493A
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- 239000000758 substrate Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 11
- 230000000694 effects Effects 0.000 claims description 9
- 230000005641 tunneling Effects 0.000 claims description 7
- TVEXGJYMHHTVKP-UHFFFAOYSA-N 6-oxabicyclo[3.2.1]oct-3-en-7-one Chemical compound C1C2C(=O)OC1C=CC2 TVEXGJYMHHTVKP-UHFFFAOYSA-N 0.000 claims 1
- 238000011068 loading method Methods 0.000 claims 1
- 230000014759 maintenance of location Effects 0.000 abstract description 2
- 239000004065 semiconductor Substances 0.000 description 17
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
- 239000010703 silicon Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 238000007667 floating Methods 0.000 description 2
- 238000012423 maintenance Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000002679 ablation Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000010295 mobile communication Methods 0.000 description 1
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Abstract
The invention provides a kind of based on nanocrystalline non-volatility memorizer.Describedly comprise an active area based on nanocrystalline non-volatility memorizer, described active area top is used to the selection grid selecting the word line of address and be used to choose reading unit across many of configurations, many the bit lines that are used for reading of data also are set on the described active area, described bit line and described word line vertical arrangement, configuration is independently nanocrystalline between every word line and the active area, by technical scheme provided by the invention, can prevent to have influence on the data of memory integral body, so the data retention characteristics of memory provided by the invention is more stable owing to certain some electric leakage.
Description
Technical field
The present invention relates to technical field of semiconductors, particularly a kind of based on nanocrystalline non-volatility memorizer.
Background technology
At present, along with the development that science and technology is maked rapid progress, technical field of semiconductors has also obtained unprecedented exploitation, and wherein the memory industry accounts for 1/4th of whole semiconductor industry at present.The semiconductor memory that is used to store data is divided into volatile semiconductor memory and non-volatile semiconductor memory, the volatile semiconductor memory is easy to obliterated data when power interruptions, even and the non-volatility semiconductor memory still can be preserved data when power interruptions, and non-volatile semiconductor memory compares less, so non-volatile semiconductor memory has been widely used in fields such as mobile communication system, storage card.
Existing non-volatile semiconductor memory is flash memory (Flash Memory) for example, owing to have and repeatedly to carry out depositing in of information, read, action such as wipe, and the advantage that the information that deposits in also can not disappear after outage, thus become PC and electronic equipments such as digital camera egative film, individual accompanied electronic notepad a kind of non-volatility memorizer of extensively adopting.
Present flash memory adopts stacking gate, source/drain that floating grid (Floating gate) and control gate form and the selection transistor that is positioned at stacking gate one side to constitute substantially, such memory is the integral body of a conduction, therefore, when size is dwindled, during the oxide layer attenuate, because it is the integral body of a conduction, when electric leakage appears in a certain point, the data of memory integral body will be lost, and therefore adopt the memory data retentivity meeting variation of prior art.
Therefore, in carrying out the invention process, the inventor finds that there are the following problems at least in the prior art: existing non-volatile semiconductor memory adopts as storage medium, and certain any electric leakage can make the loss of data of memory integral body, so the data retentivity is not good.
Summary of the invention
In view of this, the embodiment of the invention proposed a kind of can improve stability that data keep based on nanocrystalline non-volatility memorizer.
For solving the problems of the technologies described above, the purpose of the embodiment of the invention is achieved through the following technical solutions:
A kind of based on nanocrystalline non-volatility memorizer, comprise an active area that defines on the substrate, described active area top is used to the selection grid selecting the word line of address and be used to choose reading unit across many of configurations, many the bit lines that are used for reading of data also are set on the described active area, described bit line and described word line vertical arrangement, configuration is independently nanocrystalline between every word line and the active area.
By provided by the invention based on nanocrystalline non-volatility memorizer since nanocrystalline be independently, therefore can prevent since certain some electric leakage have influence on the data of memory integral body, improved the stability of the data maintenance of memory.
Description of drawings
Figure lA is the front view that the present invention is based on the structural representation of nanocrystalline non-volatility memorizer;
Figure 1B is the vertical view that the present invention is based on the structural representation of nanocrystalline non-volatility memorizer;
Fig. 2 the present invention is based on the principle schematic that nanocrystalline non-volatility memorizer writes;
Fig. 3 the present invention is based on the principle schematic that nanocrystalline non-volatility memorizer is wiped;
Fig. 4 the present invention is based on the principle schematic that nanocrystalline non-volatility memorizer reads.
Embodiment
It is a kind of based on nanocrystalline non-volatility memorizer that the embodiment of the invention provides.
For making technical scheme of the present invention clearer, below with reference to accompanying drawing and enumerate embodiment, the present invention is described in more detail.
Please together consult Figure 1A and Figure 1B, be front view and the vertical view of the embodiment of the invention based on the structural representation of nanocrystalline non-volatility memorizer.
Described non-volatility memorizer comprises substrate (not label), and this substrate can adopt silicon base, oxygen buried layer and top layer silicon as backing material.Wherein, silicon base is played a supporting role, and oxygen buried layer plays the effect that insulation is isolated, and top layer silicon can form source, leakage and the raceway groove of this non-volatility memorizer.
Definition has an active area 10 on the described substrate, and described active area 10 tops are across disposing many word lines, the arrangement parallel to each other of described word line and word line.Word line WLS1 and the WLS2 among Figure 1A and Figure 1B for example.Described word line is mainly used in the selection of address.
Dispose nanocrystalline 20 between each word line and the active area respectively.Described nanocrystalline 20 are graininess.
Described active area 10 tops also are provided with multiple bit lines, are arranged in parallel between described bit line and the bit line, are positioned at a side of word line, and with the word line vertical arrangement.Described bit line can be formed by the conductive layer on the substrate.Bit line BL1 and the BL2 among Figure 1A and Figure 1B for example.Described bit line is mainly used in reading of data.
Grid are also selected across disposing many in described active area 10 tops, and described selection grid are positioned at the opposite side of word line, for example selection grid WL1 and the WL2 among the figure.Described selection grid are mainly used in chooses reading unit.
From said structure as can be seen, because the nanocrystalline of each word line below all is relatively independent, can prevent to influence the data of memory integral body, so the data retention characteristics of memory provided by the invention is more stable owing to certain some electric leakage.
Specify the operation principle that the present invention is based on nanocrystalline non-volatility memorizer below.
Please continue to consult Fig. 2, for the present invention is based on the principle schematic that nanocrystalline non-volatility memorizer writes.
As shown in the figure, with the annexation of memory, be divided into unit A, unit B, unit C and cells D according to word line, bit line, selection grid.
Ablation process mainly comprises:
Choose the unit that need write data;
Under the high pressure effect between substrate and the word line, from substrate, be drawn into nanocrystalline in the described data cell of choosing by the tunneling effect electronics.
Wherein, choose the concrete mode in the unit that need write data as follows:
Substrate at memory applies a negative voltage-6V, on bit line BL1, load a negative voltage-6V, on bit line BL2, load a positive voltage+1.5V, on word line WLS1, load a positive voltage+6V, on word line WLS2, load a negative voltage-2V, selecting to load a negative voltage-6V on the grid WL1, selecting to load a negative voltage-6V on the grid WL2.
At this moment, unit A is selected, unit B, unit C, cells D are all not selected, because on the Semiconductor substrate is negative voltage-6V, be that grid voltage is+6V on the word line WLS1, therefore, have bigger voltage difference between Semiconductor substrate and the grid, by tunneling effect fast electronics from substrate, move to nanocrystalline in, write data in the unit of choosing fast thereby be implemented in.
The voltage that the present embodiment memory is loaded is except above-mentioned concrete numerical value, can also be other numerical value in the certain limit, negative voltage-6V for example, can be-4V arbitrary magnitude of voltage to the-10V, negative voltage-2V can be-1V arbitrary magnitude of voltage to the-3V, positive voltage+1.5V can be arbitrary magnitude of voltage among the 0V to 4V, positive voltage+6V can be+and 4V arbitrary magnitude of voltage to the+10V.
Simultaneously, because that each unit has is independently nanocrystalline separately, the retentivity that therefore writes after the data is more stable, can be because of one of them unit electric leakage, and cause the loss of data of other unit.
See also Fig. 3, for the present invention is based on the principle schematic that nanocrystalline non-volatility memorizer is wiped.
As shown in the figure, with the annexation of memory, be divided into unit A, unit B, unit C and cells D according to word line, bit line, selection grid.
Erase process mainly comprises:
Choose the unit that needs obliterated data;
Under the high pressure effect between word line and the substrate, the electron tunneling that is stored in nanocrystalline is got back in the substrate.
Wherein, choose the concrete mode in the unit that needs obliterated data as follows:
Substrate at memory applies a positive voltage+6V, on bit line BL1, load a positive voltage+6V, on bit line BL2, load a positive voltage+6V, on word line WLS1, load a negative voltage-6V, on word line WLS2, load a positive voltage+6V, selecting to load a positive voltage+6V on the grid WL1, selecting to load a positive voltage+6V on the grid WL2.
At this moment, unit A and unit B are selected, and unit C and cells D are not selected.Because on the Semiconductor substrate is positive voltage+6V, be that grid voltage is-6V on the word line WLS1, therefore, has bigger voltage difference between Semiconductor substrate and the grid, and underlayer voltage is higher than grid voltage, by tunneling effect the electron tunneling that was stored in originally in nanocrystalline is got back in the substrate, thereby be implemented in fast erase of data in the unit of choosing.
The voltage that the present embodiment memory is loaded can also be other numerical value in the certain limit except above-mentioned concrete numerical value, and negative voltage-6V for example can be-4V arbitrary magnitude of voltage to the-10V, positive voltage+6V can be+and 4V arbitrary magnitude of voltage to the+10V.
See also Fig. 4, for the present invention is based on the principle schematic that nanocrystalline non-volatility memorizer reads.
As shown in the figure, with the annexation of memory, be divided into unit A, unit B, unit C and cells D according to word line, bit line, selection grid.
The process that reads mainly comprises:
Choose the unit that needs reading of data;
Induced current by reading bit line output reads the data in the selected cell.
Wherein, choose the concrete mode in the unit that needs reading of data as follows:
The substrate ground connection of memory loads a positive voltage+0.8V, ground connection on bit line BL2 on bit line BL1, on word line WLS1, load a positive voltage+2.5V, word line WLS2 ground connection,, selecting ground connection on the grid WL2 selecting to load a positive voltage+2.5V on the grid WL1.
At this moment, unit A is selected, unit B, unit C, cells D are all not selected, and because Semiconductor substrate ground connection is that grid voltage is+2.5V on the word line WLS1, bit line BL1 goes up and is positive voltage+0.8V, therefore, on bit line BL1, produce an induced current, read described induced current from bit line BL1, by assessing this electric current, read the data of this unit A.
The voltage that the present embodiment memory is loaded can also be other numerical value in the certain limit except above-mentioned concrete numerical value, for example positive voltage+0.8V and+2.5V can be+1V arbitrary magnitude of voltage to the+3V.
In sum, adopt provided by the invention based on nanocrystalline non-volatility memorizer since nanocrystalline be independently, therefore can prevent since certain some electric leakage have influence on the data of memory integral body, improved the stability of memory data maintenance.
More than a kind ofly be described in detail provided by the present invention based on nanocrystalline non-volatility memorizer, used specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (8)
1. one kind based on nanocrystalline non-volatility memorizer, it is characterized in that, comprise an active area that defines on the substrate, described active area top is used to the selection grid selecting the word line of address and be used to choose reading unit across many of configurations, many the bit lines that are used for reading of data also are set on the described active area, described bit line and described word line vertical arrangement, configuration is independently nanocrystalline between every word line and the active area.
2. according to claim 1ly it is characterized in that based on nanocrystalline non-volatility memorizer described selection grid are positioned at a side of described word line, described bit line is positioned at the opposite side of described word line.
3. a method that writes based on nanocrystalline non-volatility memorizer data is characterized in that, comprising:
Choose the unit that need write data;
Under the high pressure effect between substrate and the word line, from substrate, be drawn into nanocrystalline in the described data cell of choosing by the tunneling effect electronics.
4. the method that writes based on nanocrystalline non-volatility memorizer data according to claim 3 is characterized in that, the described concrete mode in the unit that need write data of choosing is:
Apply one-4V arbitrary negative voltage to the-10V at substrate;
On a bit line, load one-4V arbitrary negative voltage to the-10V, load arbitrary positive voltage among the 0V to 4V on another bit line;
On a word line, load one+4V arbitrary positive voltage to the+10V, on another word line, load one-1V arbitrary negative voltage to the-3V;
Two select on the grid all loadings-4V extremely-10V in arbitrary negative voltage.
5. the method based on nanocrystalline non-volatility memorizer data erase is characterized in that, comprising:
Choose the unit that needs obliterated data;
Under the high pressure effect between word line and the substrate, the electron tunneling that is stored in nanocrystalline is got back in the substrate.
6. the method based on nanocrystalline non-volatility memorizer data erase according to claim 5 is characterized in that, the described concrete mode in the unit that needs obliterated data of choosing is:
Apply one+4V arbitrary positive voltage to the+10V at substrate;
On two bit lines, all load one+4V arbitrary positive voltage to the+10V;
On a word line, load one-4V arbitrary negative voltage to the-10V, on another word line, load one+4V arbitrary positive voltage to the+10V;
Two select on the grid all loadings+4V extremely+10V in arbitrary positive voltage.
7 one kinds of methods based on nanocrystalline non-volatility memorizer data read is characterized in that, comprising:
Choose the unit that needs reading of data;
Induced current by reading bit line output reads the data in the selected cell.
8. the method based on nanocrystalline non-volatility memorizer data read according to claim 7 is characterized in that, the described concrete mode in the unit that needs reading of data of choosing is:
Substrate ground connection;
On a bit line, load one+1V arbitrary positive voltage to the+3V, another bit line ground connection;
On a word line, load one+1V arbitrary positive voltage to the+3V, another word line ground connection;
Select grid to load one+1V arbitrary positive voltage to the+3V one, another selects grid ground connection.
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| Application Number | Priority Date | Filing Date | Title |
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| CNA2009100553899A CN101599493A (en) | 2009-07-24 | 2009-07-24 | A kind of based on nanocrystalline non-volatility memorizer |
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| CNA2009100553899A CN101599493A (en) | 2009-07-24 | 2009-07-24 | A kind of based on nanocrystalline non-volatility memorizer |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103295633A (en) * | 2012-02-28 | 2013-09-11 | 中国科学院微电子研究所 | 2T nanocrystalline memory array and operation method thereof |
| CN104517652A (en) * | 2014-09-30 | 2015-04-15 | 上海华虹宏力半导体制造有限公司 | Method for improving FLASH reliability |
-
2009
- 2009-07-24 CN CNA2009100553899A patent/CN101599493A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103295633A (en) * | 2012-02-28 | 2013-09-11 | 中国科学院微电子研究所 | 2T nanocrystalline memory array and operation method thereof |
| CN103295633B (en) * | 2012-02-28 | 2016-04-13 | 中国科学院微电子研究所 | 2T nanocrystalline memory array and operation method thereof |
| CN104517652A (en) * | 2014-09-30 | 2015-04-15 | 上海华虹宏力半导体制造有限公司 | Method for improving FLASH reliability |
| CN104517652B (en) * | 2014-09-30 | 2017-10-24 | 上海华虹宏力半导体制造有限公司 | Improve the method for FLASH reliabilities |
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Application publication date: 20091209 |