CN101594151A - LDPC sign indicating number decoder - Google Patents
LDPC sign indicating number decoder Download PDFInfo
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- CN101594151A CN101594151A CNA2009100544419A CN200910054441A CN101594151A CN 101594151 A CN101594151 A CN 101594151A CN A2009100544419 A CNA2009100544419 A CN A2009100544419A CN 200910054441 A CN200910054441 A CN 200910054441A CN 101594151 A CN101594151 A CN 101594151A
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Abstract
The present invention relates to a kind of LDPC sign indicating number decoder of supporting any various code rate, comprise input buffer module, control module, calculation process module, intermediate store, microinstruction storage, exchanging network module, verification module, output buffer module and internet, adopt the structure of part parallel; It stores different code rate information into microinstruction storage based on the control mode of microcommand, with this code check is separated with hardware configuration, has realized on the basis that does not increase hardware costs, to the support of any multi code Rate of Chinese character; The decoder line is very regular, has reduced the complexity of line widely; Can effectively reduce the design cycle of digital communication system, improve design efficiency.
Description
Technical field
The present invention relates to a kind of LDPC sign indicating number decoder of supporting any various code rate, can directly apply to the decoding of forward error correction channel, belong to the radio digital communication technical field.
Background technology
In modern digital communication systems. the design of error correction coding is an important component part that guarantees reliable data transmission because it can detect and the correction signal transmission course in the mistake introduced.Adopt forward error correction coding (FEC) can significantly improve transmission reliability.LDPC (LowDensity Parity Check) sign indicating number is a kind of forward error correction coding technology, also claims the Gallager sign indicating number.At present, the LDPC sign indicating number has become the focus of chnnel coding circle research, has obtained extensive application in fields such as radio communication, satellite communications.The LDPC sign indicating number is a kind of linear block codes, and codeword structure is determined by check matrix.Consider hard-wired cost, the LDPC sign indicating number that uses in various standards at present all is a quasi-cyclic LDPC code, the check matrix of quasi-cyclic LDPC code is made up of a series of circulation submatrixs, so-called circulation submatrix is meant that each provisional capital is the ring shift right of lastrow in the submatrix, and first row is the ring shift right of last column; Each row all is that the circulation of previous column moves down, and first row are that the circulation of last row moves down.It is better than Turbo code, and its performance is more near shannon limit, and the retardation ratio Turbo code is little, thereby is more suitable for being applied in the system of high data rate.FEC technology based on the LDPC sign indicating number has been used in China Digital TV ground transmission standard (DTMB) and the European Digital Television satellite transmits standard standards such as (DVB-S2).
In order to satisfy different service requests and to adapt to different channel circumstances, and make whole system more flexible, the LDPC sign indicating number in each standard has all been introduced multi code Rate of Chinese character, as the LDPC sign indicating number in the DVB-S2 standard, just includes 11 kinds of code checks.And present too fixing, problems such as the proportional increase of code check number that can not adapt to variation and the hardware resource and the support of code check neatly of ubiquity decoding architecture in the communication system are unfavorable for the multiplexing of resource.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of LDPC sign indicating number decoder, can realize supporting to plant arbitrarily the decoding of code check on the basis that does not increase hardware resource.
The present invention solves the technical scheme that such scheme takes: a kind of LDPC sign indicating number decoder, support any various code rate, comprise input buffer module, control module, calculation process module, intermediate store, microinstruction storage, exchanging network module, verification module and output buffer module, adopt the structure of part parallel, on data throughput and chip area, obtain suitable compromise
Described microinstruction storage is divided into system configuration information district and decoding microinstruction field; Described system configuration information district has stored the initial address Add of decoding microinstruction field of different code checks and the correction factor Yita of different code checks; The specifying information of different code checks has been stored in described decoding microinstruction field, comprises submatrix address and submatrix side-play amount,
Described decoder also comprises microinstruction storage, exchanging network module;
Described intermediate store comprises check node memory, variable node memory.
Described calculation process module is made up of 360 concurrent operation processing units.
Wherein, input buffer module links to each other with the calculation process module by check node memory, exchanging network module; Output buffer module links to each other with the calculation process module by the verification module; The variable node memory directly links to each other with the calculation process module; Control module links to each other with microinstruction storage with check node memory, exchanging network module, calculation process module, variable node memory, verification module respectively.
Control module is mainly used in accepts outside configuration information, the address pointer of control microinstruction storage; Microinstruction storage is divided into system configuration information district and decoding microinstruction field; Wherein the system configuration information district has stored the initial address Add of decoding microinstruction field of different code checks and the correction factor Yita of different code checks; The specifying information of different code checks has been stored in described decoding microinstruction field, comprises submatrix address and submatrix side-play amount in the check matrix.Control module decoding when initial at first according to the configuration information of outside, it is code rate information, system configuration information district in microinstruction storage reads the information of phase code rate and comes initialization system, after the information that obtains beginning to decipher, jump to the initial address of the decoding microinstruction field of this code check again, begin decoding.In the process of decoding, the redirect of the address pointer of microinstruction storage is to be controlled according to the system mode of a last clock by the state machine in the control module.
Described calculation process module is made up of 360 concurrent operation processing units, and each submatrix of parallel processing is divided the check matrix of different code checks according to the number of parallel processing element.For different check matrixes, the hardware arithmetic element does not change, and has only changed the number that needs the submatrix handled, has realized on the basis that does not change the hardware handles number of unit support to multi code Rate of Chinese character.
Described input buffer module storage input one frame channel data carries out decoding initialization then; The output buffer module is after frame data are finished decoding, and storage hard decision result exports in proper order by the clock beat then.
The memory width of described check node memory, variable node memory and exchanging network module is determined by the number of concurrent operation processing unit, exchanging network module is passed through in the output of check-node, the confidence level of submatrix is shifted, send into operation processing unit by regular network configuration, eliminate the chip internal wiring and block up.
The invention has the beneficial effects as follows:
1, adopt microinstruction storage and partition method thereof, on the basis that increases any hardware cost hardly, realized the decoder to the LDPC of any various code rate, as the LDPC sign indicating number in the DVB-S2 standard, this method has very strong operability and flexibility;
2, in check node memory and variable node memory, the concurrent operation unit links to each other with the memory of fixing, no longer the difference with code check changes, the intermediate data transmission can come flexibly, finish efficiently by switching network, therefore the decoder line is very regular, has reduced the complexity of line widely;
3, use the design cycle that design of encoder that this scheme realizes LDPC can reduce digital communication system, improve design efficiency.
Description of drawings
Fig. 1 is a LDPC sign indicating number decoder general frame block diagram of the present invention;
Fig. 2 is a LDPC sign indicating number decoder microinstruction storage subregion schematic diagram of the present invention;
Fig. 3 is the microinstruction format schematic diagram in system configuration information district in the microinstruction storage;
Fig. 4 is the microinstruction format schematic diagram of decoding microinstruction field in the microinstruction storage.
Embodiment
The structure of LDPC sign indicating number decoder of the present invention comprises input buffer module, control module, calculation process module, intermediate store, microinstruction storage, exchanging network module, verification module and output buffer module as shown in Figure 1.Wherein control module is used to accept the address pointer of outside configuration information and control microinstruction storage; The microinstruction storage essential record control microcommand and the corresponding check matrix information of the configuration information of system and various code checks, as shown in Figure 2, microinstruction storage is divided into system configuration information district and decoding microinstruction field; Described system configuration information district has stored the initial address Add of decoding microinstruction field of different code checks and the correction factor Yita of different code checks; The specifying information of different code checks has been stored in described decoding microinstruction field, comprises submatrix address and submatrix side-play amount.
For the different check matrix of different code checks, wherein submatrix is extracted with the simple parameters form, comprise the address information of submatrix and submatrix side-play amount with respect to unit matrix.And decode procedure is carried out abstract, and it is reduced to several different decoding states, the positional information and the side-play amount of decoding state, submatrix are represented with the form of microcommand, and be stored in decoding microinstruction field in the microinstruction storage, as shown in Figure 3.Whole like this decode procedure just can be controlled with the microcommand block that has parameter, and data path only need peek according to the parameter that microcommand passes over, calculate, write back and get final product.
Control module decoding when initial at first according to the configuration information of outside, it is code rate information, system configuration information district in microinstruction storage reads the information of phase code rate and comes initialization system, after the information that obtains beginning to decipher, jump to the initial address of the decoding microinstruction field of this code check again, begin decoding.Every kind of concrete code check correspondence one section microcommand program wherein, in the process of decoding, control module only need be controlled the redirect of the address pointer of microinstruction storage simply according to state machine, read corresponding microcommand, be may command whole system operation flow process, the decoder no longer code check with concrete is relevant.
The data result of intermediate treatment is stored in check node memory and the variable node memory, and the concurrent operation unit links to each other with the memory of fixing, and no longer the difference with code check changes, and the intermediate data transmission can come flexibly, finish efficiently by switching network.Therefore the line of LDPC sign indicating number decoder of the present invention is very regular, has reduced the complexity of line widely.In addition, the exchange parameter of control switching network can be left concentratedly in memory with the form of microcommand, and this design feature makes hardware configuration be independent of concrete code check becomes possibility.
Control state machine in the control module is a most important parts in the whole decoding system, control state machine is carried out redirect in states such as standby, decoding, output, and control state machine is only relevant with microinstruction storage, and the course of work of whole decoder all is to read the running that corresponding microcommand is controlled all modules in the microinstruction storage by control state machine to finish.
Fig. 2 is the microcommand subregion schematic diagram in the microinstruction storage, and wherein shadow-free partly is the system configuration information district, and all the other dash areas are microcommand pieces of the different code checks of representative.Deposit in system configuration information district shown in Figure 3 is parameters such as the initial address of every kind of code check microcommand piece and improvement factor; Control state machine in the control module enters wait state then coming initialization system according to the information in the exterior arrangement information reading system configuration information district.If need decoding, then the address pointer of control state machine control microinstruction storage constantly circulates in certain microcommand piece and moves.
The process of decoding is the alternation procedure that constantly carries out twice line scanning.In line scanning, need provide the address at each submatrix place in the check matrix, and corresponding side-play amount; There have been these two amounts just can describe whole check matrix, changed code check and change check matrix exactly, just changed these parameters.
In the design of LDPC sign indicating number decoder of the present invention, whole decode procedure is divided into 12 states, corresponding following 12 kinds of instructions:
CONFG: configuration-direct.What followed the expression back is configuration parameter;
ENDCFG: configuration END instruction.Expression has obtained all configuration informations;
POPOUT: decoding output order.Expression decoding iterative process finishes, output hard decision result;
STDBY: standby command.The expression system is in holding state.
STRTM: decoding sign on.The beginning of expression check matrix;
STRTR: every line scanning sign on.The beginning of the every row of expression check matrix;
ENDL: instruction is finished in every line scanning.Finishing of the scanning of the every row of expression check matrix;
ENDY: line replace command.The expression one's own profession end of scan begins to scan next line;
DECR: translation instruction.The decoding of line scanning is for the first time being carried out in expression;
DECS: translation instruction.The decoding of line scanning is for the second time being carried out in expression;
ENDM: decoding END instruction.The end of expression check matrix;
GHD: obtain the hard decision information command.Represent to obtain after each iteration is finished and declare information firmly;
With Add 0 is the microcommand piece initial address Add 1～i of saved several code checks of microinstruction storage of initial address, and corresponding correction factor yita1～i; ENDCFG instruction expression configuration-direct finishes.In addition because STDBY and POPOUT instruction for special instruction, are also placed in this zone.If the special instruction that needs later on to increase other also must be placed on here.Begin to be the pairing decoding microcommand of first code check piece from Add 1, during line scanning, corresponding instruction of each submatrix in the check matrix, first writes down the address information of each submatrix and its cycle offset line by line since first row; To in requisition for supporting the how many kinds of code check, then increase how many piece microcommand pieces, increase some parameters in the system configuration information district simultaneously and get final product.
The present invention is used for the design of the outer receiver of European satellite digital television broadcasting second generation standard DVB-S2, has passed through emulation and hardware and has realized, has obtained good effect.
Claims (5)
1, a kind of LDPC sign indicating number decoder, support any various code rate, comprise input buffer module, control module, calculation process module, intermediate store, output buffer module and verification module, adopt the structure of part parallel, it is characterized in that: described decoder also comprises microinstruction storage, exchanging network module;
Described intermediate store comprises check node memory, variable node memory;
Described calculation process module is made up of n concurrent operation processing unit;
Wherein, input buffer module links to each other with the calculation process module by check node memory, exchanging network module; Output buffer module links to each other with the calculation process module by the verification module; The variable node memory directly links to each other with the calculation process module; Control module links to each other with microinstruction storage with check node memory, exchanging network module, calculation process module, variable node memory, verification module respectively.
2, LDPC sign indicating number decoder according to claim 1 is characterized in that: described microinstruction storage is divided into system configuration information district and decoding microinstruction field; Described system configuration information district has stored the initial address Add of decoding microinstruction field of different code checks and the correction factor Yita of different code checks; The specifying information of different code checks has been stored in described decoding microinstruction field, comprises submatrix address and submatrix side-play amount in the check matrix.
3, LDPC sign indicating number decoder according to claim 1, it is characterized in that: described calculation process module is made up of 360 concurrent operation processing units, each submatrix of parallel processing is divided the check matrix of different code checks according to the number of parallel processing element.
4, LDPC sign indicating number decoder according to claim 1 is characterized in that: described input buffer module storage input one frame channel data, carry out decoding initialization then; The output buffer module is after frame data are finished decoding, and storage hard decision result exports in proper order by the clock beat then.
5, LDPC sign indicating number decoder according to claim 1, it is characterized in that: the memory width of described check node memory, variable node memory and exchanging network module is determined by the number of concurrent operation processing unit, exchanging network module is passed through in the output of check-node, the confidence level of submatrix is shifted, sends into operation processing unit by regular network configuration.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104901766A (en) * | 2014-03-03 | 2015-09-09 | 联想(北京)有限公司 | Channel decoding device and method |
| CN112134570A (en) * | 2020-08-16 | 2020-12-25 | 复旦大学 | Multi-mode LDPC decoder applied to deep space communication |
| CN112260698A (en) * | 2019-07-22 | 2021-01-22 | 上海高清数字科技产业有限公司 | Dynamic correction factor configuration method in LDPC decoder |
| CN112350736A (en) * | 2019-07-22 | 2021-02-09 | 上海高清数字科技产业有限公司 | Dynamic correction factor configuration method in LDPC decoder |
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2009
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104901766A (en) * | 2014-03-03 | 2015-09-09 | 联想(北京)有限公司 | Channel decoding device and method |
| CN104901766B (en) * | 2014-03-03 | 2019-07-26 | 联想(北京)有限公司 | Channel decoding device and method |
| CN112260698A (en) * | 2019-07-22 | 2021-01-22 | 上海高清数字科技产业有限公司 | Dynamic correction factor configuration method in LDPC decoder |
| CN112350736A (en) * | 2019-07-22 | 2021-02-09 | 上海高清数字科技产业有限公司 | Dynamic correction factor configuration method in LDPC decoder |
| CN112134570A (en) * | 2020-08-16 | 2020-12-25 | 复旦大学 | Multi-mode LDPC decoder applied to deep space communication |
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Application publication date: 20091202 |