CN101593733B - Encapsulation structure - Google Patents
Encapsulation structure Download PDFInfo
- Publication number
- CN101593733B CN101593733B CN2009101512260A CN200910151226A CN101593733B CN 101593733 B CN101593733 B CN 101593733B CN 2009101512260 A CN2009101512260 A CN 2009101512260A CN 200910151226 A CN200910151226 A CN 200910151226A CN 101593733 B CN101593733 B CN 101593733B
- Authority
- CN
- China
- Prior art keywords
- unit
- cavity wall
- wall limit
- encapsulating structure
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Micromachines (AREA)
Abstract
The invention provides an encapsulation structure, which comprises a cover plate, unit cavities, cutting ways, solder pad areas and clearance areas, wherein the unit cavities are positioned on the cover plate and discretely arranged; each unit cavity comprises a cavity and a unit cavity wall positioned on the periphery of the cavity; the cutting ways are positioned between adjacent unit cavities; the solder pad areas are positioned on edges of unit cavity walls and discretely arranged; the clearance areas are positioned in areas on the edges of the unit cavity walls excluding the solder pad areas; and corresponding edges of the unit cavity walls of the adjacent unit cavities are partially connected through the cutting ways. The corresponding edges of the unit cavity walls of the adjacent unit cavities are partially connected through the cutting ways on the cover plate, so the bonding force between the cavity walls and chips can be improved, and the problem that the mechanical stress generated in a subsequent V-shaped groove cutting process makes the cavity walls and the chips peel off to cause large-area yield loss is prevented.
Description
Technical field
The application relates to the semiconductor packages field, relates in particular to a kind of encapsulating structure.
Background technology
The crystal wafer chip dimension encapsulation (Wafer Level Chip Size Packaging, WLCSP) technology is that the full wafer wafer is carried out cutting the technology that obtains single finished chip again after the packaging and testing, the chip size after the encapsulation is consistent with nude film.The crystal wafer chip dimension encapsulation technology changes the pattern of conventional package such as ceramic leadless chip carrier (Ceramic Leadless Chip Carrier), organic leadless chip carrier (Organic LeadlessChip Carrier) and digital-code camera module formula, has complied with that market is light day by day, little, short to microelectronic product, thinning and low priceization requirement.It is highly microminiaturized that chip size after crystal wafer chip dimension encapsulation technology encapsulation has reached, chip cost along with chip size reduce significantly reduce with the increase of wafer size.The crystal wafer chip dimension encapsulation technology be IC can be designed, technology that wafer manufacturing, packaging and testing, substrate manufacturing integrate, be the focus and the developing tendency in future of current encapsulation field.
The Chinese invention patent application discloses a kind of encapsulating structure and manufacture method thereof based on the manufacturing of crystal wafer chip dimension encapsulation technology for 200610096808.X number.As shown in Figure 1, described encapsulating structure comprises the cover plate 105 (glass) with cavity wall 110, the chip 120 with weld pad 115 and sheet glass 130, and it constitutes the encapsulating structure of the sandwich of glass-chip-glass jointly.The surface that is formed with semiconductor device of described chip 120 is connected with cavity wall 110 by weld pad 115; Clamping has insulating barrier between the first surface of the back side of chip 120 and sheet glass 130; Another surface portion of glassy layer 130 is covered with first solder mask layer and position pedestal (unmarked) thereon; Described pedestal is realized being electrically connected by metal level with weld pad 115.
In above-mentioned patent application, and the concrete layout of the cavity wall 110 of unexposed its cover plate 105, but prior art discloses the cavity wall structure on a kind of cover plate, as shown in Figure 2, comprise the chamber, unit 100 that is positioned on the cover plate, 200,300,400, chamber, described unit 100,200,300,400 discrete arranging, chamber, described unit comprises cavity and is positioned at cavity cavity wall limit, unit on every side, comprise cavity 101 and be positioned at cavity 101 unit cavity wall 102 on every side such as chamber, unit 100, chamber, unit 200 comprises cavity 201 and is positioned at cavity 201 unit cavity wall 202 on every side, chamber, unit 300 comprises cavity 301 and is positioned at cavity 301 unit cavity wall 302 on every side, chamber, unit 400 comprises cavity 401 and is positioned at cavity 401 unit cavity wall 402 on every side, described cavity 101,201,301, device region on the 401 unit chip region that are used to hold on follow-up and the bonding wafer of backboard.
In conjunction with Fig. 1, can know, said units cavity wall 102,202,302,402 will carry out bonding with the wafer that has weld pad 115, need then cover plate and bonding with it wafer are carried out mechanical hemisection to form V-shaped groove, therefore, unit cavity wall 102,202,302,402 need bear certain mechanical stress, because cavity wall plays a part to support cover plate, also will bear certain gravity simultaneously.But owing to be not hollow on the unit cavity wall 102,202,302,402 with weld pad 115 bonding places, reduced the adhesion of unit cavity wall 102,202,302,402 and wafer relatively, the mechanical stress that produces in follow-up V-shaped groove cutting technique makes cavity wall and wafer peel off easily, thereby causes the large tracts of land yield loss.
Summary of the invention
The application's technical problem to be solved provides a kind of encapsulating structure that can bear higher mechanical stress.
For solving the problems of the technologies described above, the application provides a kind of encapsulating structure, comprising: cover plate; The chamber, unit is positioned on the cover plate and discrete arranging, and chamber, described unit comprises cavity and is positioned at cavity each cavity wall limit, unit on every side; Cutting Road is between the adjacent cells chamber; Pad zone is positioned on each cavity wall limit, unit and discrete arranging; Interstitial area, on each cavity wall limit, unit zone outside the pad zone; The corresponding unit cavity wall limit in adjacent cells chamber partly connects via Cutting Road.
Described part is connected to corresponding connection of at least one pad zone on the corresponding unit cavity wall limit in adjacent cells chamber.
Each pad zone that described part is connected on the corresponding unit cavity wall limit in adjacent cells chamber connects with corresponded manner one by one.
The pad zone that described part is connected on the corresponding unit cavity wall limit in adjacent cells chamber connects so that interval mode is corresponding.
Described part be connected on the corresponding unit cavity wall limit in adjacent cells chamber per two pad zones and between interstitial area with corresponding connection of pad zone mode at interval.
Cavity wall limit, described unit comprises two end portions, and described two end portions is an interstitial area, and the two end portions that described part is connected on the corresponding unit cavity wall limit in adjacent cells chamber connects.
Described encapsulating structure also comprises wafer, described wafer is divided into discrete unit chip region and the passage between the adjacent cells chip region, described unit chip region is divided into device region and is positioned at the bonding pad of device region periphery, have between described device region and the bonding pad at interval, be formed with discrete weld pad in the described bonding pad, described bonding pad is corresponding with the cavity wall limit, unit on the cover plate, described wafer upper channel is corresponding with the Cutting Road on the cover plate, be formed with the isolation strip between described device region and the bonding pad, all have between described isolation strip and device region and the bonding pad at interval.
Described isolation strip is in cavity wall limit, unit after described wafer and the described cover plate pressing and the centre position between the wafer device region.
Be spaced apart 40 μ m～250 μ m between described isolation strip and the device region.
Be spaced apart 40 μ m～250 μ m between described isolation strip and the bonding pad.
The width of described isolation strip is 3 μ m～20 μ m,
Described isolation strip is identical with wafer device region height.
Described isolation strip material is a kind of or its combination in polymer, silicon nitride, silica or the silicon oxynitride.
Compare with the prior art scheme, the technical program is set to partly connect via Cutting Road by the corresponding unit cavity wall limit in adjacent cells chamber on the cover board, can improve the power that is connected between cavity wall and the chip, prevent that the mechanical stress that produces in the follow-up V-shaped groove cutting technique from peel off cavity wall and chip, causes the problem of large tracts of land yield loss.
Simultaneously, in order to prevent in cavity wall and chip pressing process, the curing glue that plays adhesive effect too much overflows the micro lens that pollutes the device region on the chip, the technical program is set to partly connect rather than all connect via Cutting Road by the corresponding unit cavity wall limit in adjacent cells chamber, form the space like this in disjunct Cutting Road position, adjacent cells cavity wall limit, can hold unnecessary curing glue like this.
The technical program can prevent further in cavity wall and chip pressing process that also by form the isolation strip between device region on the wafer and bonding pad the curing glue that plays adhesive effect overflows the problem of polluting micro lens.
Description of drawings
Fig. 1 is a prior art encapsulating structure schematic diagram;
Fig. 2 is the floor map of looking up of encapsulating structure cavity wall shown in Figure 1;
Fig. 3 is the structural representation of the cavity wall of the first embodiment of the present invention;
Fig. 4 is the structural representation of the cavity wall of the second embodiment of the present invention;
Fig. 5 is the structural representation of the cavity wall of the third embodiment of the present invention;
Fig. 6 is the structural representation of the cavity wall of the fourth embodiment of the present invention;
The structural representation of the wafer of Fig. 7 fifth embodiment of the present invention.
Embodiment
The present invention is set to partly connect via Cutting Road by the corresponding unit cavity wall limit in adjacent cells chamber on the cover board, can improve the power that is connected between cavity wall and the chip, prevent that the mechanical stress that produces in the follow-up V-shaped groove cutting technique from peel off cavity wall and chip, causes the problem of large tracts of land yield loss.
Simultaneously, in order to prevent in cavity wall and chip pressing process, the curing glue that plays adhesive effect too much overflows the micro lens that pollutes the device region on the chip, the present invention is set to partly connect rather than all connect via Cutting Road by the corresponding unit cavity wall limit in adjacent cells chamber, form the space in disjunct Cutting Road position, adjacent cells cavity wall limit, can hold unnecessary curing glue like this.
The technical program can prevent further in cavity wall and chip pressing process that also by form the isolation strip between device region on the wafer and bonding pad the curing glue that plays adhesive effect overflows the problem of polluting micro lens.
Technique scheme is suitable for the encapsulation field of image sensor dice encapsulation, MEMS Chip Packaging and LED light-emitting diode.
Be encapsulated as example with image sensor dice below, the embodiment to the application is elaborated in conjunction with the accompanying drawings.
The present invention at first provides a kind of encapsulating structure, comprising: cover plate; The chamber, unit is positioned on the cover plate and discrete arranging, and chamber, described unit comprises cavity and be positioned at unit cavity wall around the cavity, and described cavity is used for the device region on the accomodating unit chip region, described unit cavity wall comprise around each cavity wall limit, unit; Cutting Road is between the adjacent cells chamber; Pad zone is positioned on each cavity wall limit, unit and discrete arranging; Interstitial area is positioned on each cavity wall limit, unit regional outside the pad zone; The corresponding unit cavity wall limit in adjacent cells chamber partly connects via Cutting Road.
With reference to figure 3, provide the structural representation of the cavity wall of the first embodiment of the present invention.Comprise:
Cover plate, integral body does not illustrate, and its overall structure sees also 105 of Fig. 1;
Chamber, unit 100,200,300,400, be positioned on the cover plate and discrete arranging, chamber, unit on the described cover plate is arranged in array, present embodiment is that example is illustrated with chamber, four unit, chamber, described unit 100,200,300,400 comprise cavity 101 respectively, 201,301,401 and lay respectively at cavity 101,201,301, unit cavity wall 102 around 401,202,302,402, described cavity 101,201,301,401 are used to hold the device region on the follow-up bonding with it unit chip region, described unit cavity wall 102,202,302,402 comprise around each cavity wall limit, unit of arranging, such as cavity wall limit, the unit 102a～102d in chamber, unit 100, cavity wall limit, the unit 202a～202d in chamber, unit 200, cavity wall limit, the unit 302a～302d in chamber, unit 300, cavity wall limit, the unit 402a～402d in chamber, unit 400;
Cutting Road 10 is between the adjacent cells chamber; Between adjacent chamber, unit 100 and chamber, unit 200, between the adjacent chamber, unit 200 and chamber, unit 300, between the adjacent chamber, unit 300 and chamber, unit 400, and between the adjacent chamber, unit 400 and chamber, unit 100;
Pad zone, be positioned on each cavity wall limit, unit and discrete arranging, such as the pad zone 203 on the pad zone 103 on the 102a～102d of cavity wall limit, unit, cavity wall limit, the unit 202a～202d, the pad zone 303 on the 302a～302d of cavity wall limit, unit, the pad zone 403 on the 402a～402d of cavity wall limit, unit;
Interstitial area, on each cavity wall limit, unit zone outside the pad zone.
The corresponding unit cavity wall limit in adjacent cells of the present invention chamber partly connects via Cutting Road, and described part connects such as connecting at least one pad zone correspondence on the corresponding unit cavity wall limit in adjacent cells chamber.
As an embodiment, each pad zone that described part is connected on the corresponding unit cavity wall limit in adjacent cells chamber connects with corresponded manner one by one, please refer to Fig. 3 particularly, pad zone 203 corresponding connections on pad zone 103 on the 102a of cavity wall limit, unit and cavity wall limit, the unit 202a, pad zone 403 corresponding connections on pad zone 203 on the 202b of cavity wall limit, unit and cavity wall limit, the unit 402d, pad zone 303 corresponding connections on pad zone 403 on the 402a of cavity wall limit, unit and cavity wall limit, the unit 302a, pad zone 103 corresponding connections on pad zone 303 on the 302d of cavity wall limit, unit and cavity wall limit, the unit 102b, the corresponding connection of pad zone on the remaining element cavity wall limit is enumerated no longer one by one at this.
In the present embodiment, by each pad zone on the corresponding unit cavity wall limit in adjacent cells chamber is connected with corresponded manner one by one, interstitial area outside the pad zone forms the space in position, corresponding cutting road, solidify in the glue bond process follow-up the employing with wafer, these spaces can hold unnecessary curing glue, the lenticule on the curing glue stain wafer that prevents to overflow.
Simultaneously, the corresponding unit cavity wall limit part ways of connecting in adjacent cells of the present invention chamber can also be out of shape to some extent, please refer to Fig. 4, is the structural representation of the cavity wall of the second embodiment of the present invention.
The implication that various piece and label thereof are represented among Fig. 4 is identical with the counterpart of Fig. 3 among first embodiment, does not add detailed description at this.
As shown in Figure 4, the pad zone that is connected on the corresponding unit cavity wall limit in adjacent cells chamber of described part connects so that interval mode is corresponding.For example the pad zone 203 on the pad zone 103 on the 102a of unit cavity wall limit and cavity wall limit, the unit 202a is with the corresponding connection of mode of a pad zone at interval of a pad zone, pad zone 403 on pad zone 203 on the 202b of cavity wall limit, unit and cavity wall limit, the unit 402d is with the corresponding connection of the mode in an interval, pad zone 303 on pad zone 403 on the 402a of cavity wall limit, unit and cavity wall limit, the unit 302a is with the corresponding connection of the mode in an interval, pad zone 103 on pad zone 303 on the 302d of cavity wall limit, unit and cavity wall limit, the unit 102b is with the corresponding connection of the mode in an interval, the corresponding connection of pad zone on the remaining element cavity wall limit is enumerated no longer one by one at this.
Simultaneously, the corresponding unit cavity wall limit part ways of connecting in adjacent cells of the present invention chamber can also be out of shape to some extent, please refer to Fig. 5, is the structural representation of the cavity wall of the third embodiment of the present invention.
As shown in Figure 5, described part be connected on the corresponding unit cavity wall limit in adjacent cells chamber per two pad zones and between interstitial area with corresponding connection of pad zone mode at interval.Such as per two pad zones 103 on the 102a of cavity wall limit, unit and between interstitial area and cavity wall limit, unit 202a on per two pad zones 203 and between interstitial area with the corresponding connection of mode of a pad zone at interval, the corresponding connection of pad zone on the remaining element cavity wall limit is enumerated no longer one by one at this.
Simultaneously, each cavity wall limit, unit of the present invention comprises two end portions and mid portion, and described two end portions is an interstitial area, and described mid portion is for having first pad zone till last pad zone on this limit from this limit.
Please refer to Fig. 6, be the structural representation of the cavity wall of the fourth embodiment of the present invention.
As shown in Figure 6, the two end portions that described part is connected on the corresponding unit cavity wall limit in adjacent cells chamber connects, and the definition of described two end portions please refer to foregoing description.
Because the Cutting Road that forms between the existing adjacent cells cavity wall limit all forms in forming cavity technology simultaneously, its bottom flushes with cavity bottom, therefore the corresponding ways of connecting of at least one pad zone on the cavity wall limit, unit among above-mentioned first to fourth embodiment of the present invention can be by improving formation to existing technology, such as removing by need the junction in forming cavity technology, not carve on said units cavity wall limit, remove the part that need not to link to each other and carve, form the space; Can also by form in the Cutting Road respectively with above-mentioned corresponded manner one by one, interval mode, per two pad zones and between interstitial area form the structure of present embodiment every a pad zone mode or each two ends, cavity wall limit, unit at Cutting Road corresponding position packing material, its concrete formation technology those skilled in the art know by inference easily according to existing photoetching technique and etching technique, do not add detailed description at this.
Simultaneously; the present invention gives a kind of encapsulating structure of more optimizing; i.e. the 5th embodiment; covering plate structure in the described encapsulating structure can adopt the structure among above-mentioned first embodiment to the, four embodiment; but to improving, form the fifth embodiment of the present invention, certain combination according to the 5th embodiment and preceding four embodiment with the corresponding crystal circle structure of cover plate; different technical schemes can be formed, protection scope of the present invention should be too do not limited at this.
As shown in Figure 7, be the structural representation of the wafer of the fifth embodiment of the present invention.Comprise wafer, described wafer is divided into discrete unit chip region 500,600,700,800, form passage 50 between the adjacent cells chip region, for example form passage 50 (all the other and the like) between unit chip region 500 and the unit chip region 600, the Cutting Road 10 on the cover plate in described passage 50 and the previous embodiment is corresponding.
Described unit chip region 500,600,700,800 are divided into device region 501 respectively, 601,701,801 and be positioned at device region 501,601,701, the bonding pad 502 of 801 peripheries, 602,702,802, described device region 501,601,701,801 and bonding pad 502,602,702, have respectively between 802 at interval, described bonding pad 502,602,702, be formed with discrete weld pad 503 in 802,603,703,803, described device region 501,601,701,801 and the isolation strip of follow-up formation and the chamber, unit 101 on the previous embodiment cover plate 100,201,301,401 is corresponding, described bonding pad 502,602,702,802 with previous embodiment in cover plate on unit cavity wall 102,202,302,402 is corresponding, described weld pad 503,603,703,803 respectively with previous embodiment in pad zone 103,203,303,403 is corresponding.
Also be respectively arranged with isolation strip 504,604,704,804 between described device region 501,601,701,801 and the bonding pad 502,602,702,802, all have between described isolation strip 504,604,704,804 and device region 501,601,701,801 and the bonding pad 502,602,702,802 at interval.
Described isolation strip 504,604,704,804 is in cavity wall limit, unit after described wafer and the described cover plate pressing and the centre position between the wafer device region.
Corresponding interval between each isolation strip 504,604,704,804 and each device region 501,601,701,801 is 40 μ m～250 μ m, on the cover plate on each unit and the wafer interval between each unit basic identical, but admit of a little error.
Corresponding interval between each isolation strip 504,604,704,804 and each bonding pad 502,602,702,802 is 40 μ m～250 μ m, after also being cover plate and wafer pressing, be spaced apart 40 μ m～250 μ m on each isolation strip 504,604,704,804 and the cover plate between the cavity wall limit, unit, on the cover plate on each unit and the wafer each unit basic identical, but admit of a little error.
The wide of each isolation strip 504,604,704,804 is 3 μ m～20 μ m.
Because the device region of wafer is formed with lenticule and following semiconductor device layer thereof, therefore the height of described isolation strip 504,604,704,804 can not be lower than lenticular height, and promptly described isolation strip 504,604,704,804 will be determined according to the height of the semiconductor device layer of device region on the wafer apart from the height of crystal column surface.Basically, described isolation strip is identical with wafer device region height.
In the present embodiment, described isolation strip can be a kind of in polymer, silicon nitride, silica or the silicon oxynitride or combination.When being polymer, such as being polytetrafluoroethylene etc.Certainly, described isolation strip also can be other insulating properties materials, but in order to save cost, preferably adopts material comparatively common in the standard CMOS process, such as silica, silicon nitride or silicon oxynitride.
Because the coupling part among first, second, third embodiment all is positioned at the pad zone on the cover plate, and follow-uply can produce mechanical stress when carrying out mechanical hemisection, described coupling part can be played the effect of buffering to mechanical stress, thereby protection weldering gesture is avoided damage; In addition because the existence of coupling part, follow-up carry out electroless plating in, the weld pad on the wafer also can further be protected in described coupling part, prevents the weld pad corrosion.Therefore, more preferred aforementioned first, second, third embodiment of technical scheme of the present invention and with the combination of the 5th embodiment.
Above embodiment all is the examples that are encapsulated as with optical sensor chip, but the invention is not restricted to this, the encapsulation of devices such as semiconductor integrated circuit chip, thermal sensor chip, mechanics sensor chip or microcomputer electric component also can be adopted described encapsulating structure of the application and method for packing, equally also can improve the power that is connected between cavity wall and the chip, prevent that the mechanical stress that produces in the follow-up V-shaped groove cutting technique from peel off cavity wall and chip, causes the purpose of the problem of large tracts of land yield loss.
Though the present invention discloses as above with preferred embodiment, the present invention is defined in this.Any those skilled in the art without departing from the spirit and scope of the present invention, all can do various changes and modification, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (13)
1. encapsulating structure comprises:
Cover plate;
The chamber, unit is positioned on the cover plate and discrete arranging, and chamber, described unit comprises cavity and is positioned at cavity each cavity wall limit, unit on every side;
Cutting Road is between the adjacent cells chamber;
Pad zone is positioned on each cavity wall limit, unit and discrete arranging;
Interstitial area, on each cavity wall limit, unit zone outside the pad zone; It is characterized in that,
The corresponding unit cavity wall limit in adjacent cells chamber is carried out part via Cutting Road and is connected.
2. encapsulating structure as claimed in claim 1 is characterized in that, described part is connected to corresponding connection of at least one pad zone on the corresponding unit cavity wall limit in adjacent cells chamber.
3. encapsulating structure as claimed in claim 2 is characterized in that, each pad zone that described part is connected on the corresponding unit cavity wall limit in adjacent cells chamber connects with corresponded manner one by one.
4. encapsulating structure as claimed in claim 2 is characterized in that, the pad zone that described part is connected on the corresponding unit cavity wall limit in adjacent cells chamber connects so that interval mode is corresponding.
5. encapsulating structure as claimed in claim 2 is characterized in that, described part be connected on the corresponding unit cavity wall limit in adjacent cells chamber per two pad zones and between interstitial area with corresponding connection of pad zone mode at interval.
6. encapsulating structure as claimed in claim 1 is characterized in that, cavity wall limit, described unit comprises two end portions, and described two end portions is an interstitial area, and the two end portions that described part is connected on the corresponding unit cavity wall limit in adjacent cells chamber connects.
7. as each described encapsulating structure in the claim 1 to 6, it is characterized in that, described encapsulating structure also comprises wafer, described wafer is divided into discrete unit chip region and the passage between the adjacent cells chip region, described unit chip region is divided into device region and is positioned at the bonding pad of device region periphery, have between described device region and the bonding pad at interval, be formed with discrete weld pad in the described bonding pad, described bonding pad is corresponding with the cavity wall limit, unit on the cover plate, described wafer upper channel is corresponding with the Cutting Road on the cover plate, be formed with the isolation strip between described device region and the bonding pad, all have between described isolation strip and device region and the bonding pad at interval.
8. encapsulating structure as claimed in claim 7 is characterized in that, described isolation strip is in cavity wall limit, unit after described wafer and the described cover plate pressing and the centre position between the wafer device region.
9. encapsulating structure as claimed in claim 7 is characterized in that, is spaced apart 40 μ m～250 μ m between described isolation strip and the device region.
10. encapsulating structure as claimed in claim 7 is characterized in that, is spaced apart 40 μ m～250 μ m between described isolation strip and the bonding pad.
11. encapsulating structure as claimed in claim 7 is characterized in that, the width of described isolation strip is 3 μ m～20 μ m,
12. encapsulating structure as claimed in claim 7 is characterized in that, described isolation strip is identical with wafer device region height.
13. encapsulating structure as claimed in claim 7 is characterized in that, described isolation strip material is a kind of or its combination in polymer, silicon nitride, silica or the silicon oxynitride.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101512260A CN101593733B (en) | 2009-06-29 | 2009-06-29 | Encapsulation structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101512260A CN101593733B (en) | 2009-06-29 | 2009-06-29 | Encapsulation structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101593733A CN101593733A (en) | 2009-12-02 |
| CN101593733B true CN101593733B (en) | 2011-04-06 |
Family
ID=41408312
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101512260A Active CN101593733B (en) | 2009-06-29 | 2009-06-29 | Encapsulation structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101593733B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106098661B (en) * | 2013-08-05 | 2019-01-22 | 日月光半导体制造股份有限公司 | Semiconductor subassembly and its manufacturing method |
| CN105513974B (en) * | 2016-01-11 | 2018-06-19 | 苏州工业园区纳米产业技术研究院有限公司 | A kind of silicon cap capping method of based single crystal circle |
-
2009
- 2009-06-29 CN CN2009101512260A patent/CN101593733B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101593733A (en) | 2009-12-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI619218B (en) | Chip package and method for forming the same | |
| CN103077933B (en) | Three-dimensional chip integrates to wafer scale | |
| US8624371B2 (en) | Methods of fabrication of package assemblies for optically interactive electronic devices and package assemblies therefor | |
| CN104078479B (en) | The wafer-level packaging method of imageing sensor and image sensor package structure | |
| US20100327465A1 (en) | Package process and package structure | |
| CN103367382B (en) | A kind of wafer-level packaging method of image sensor chip | |
| CN103137632A (en) | Interposer package for CMOS image sensor and method for making the same | |
| CN106206485A (en) | Imageing sensor module and preparation method thereof | |
| CN103996684A (en) | Image sensor structure and packaging method thereof | |
| CN102024766A (en) | Integrated circuit package system with through semiconductor vias and method of manufacture thereof | |
| TWI598859B (en) | Electronic Device And method for fabricating the same | |
| CN101159279A (en) | Semiconductor image sensor die and production method thereof, semiconductor image sensor module, image sensor device, optical device element, and optical device module | |
| KR20160108664A (en) | semiconductor package and method for manufacturing of the same | |
| TW201914058A (en) | Semiconductor package structure | |
| TW200522379A (en) | Image sensor package ahd method for manufacturing the same | |
| JP2010166021A (en) | Semiconductor device, and manufacturing method thereof | |
| TWI236747B (en) | Manufacturing process and structure for a flip-chip package | |
| KR20200017240A (en) | Semiconductor package, Package on Package device and method of fabricating the same | |
| CN114400233A (en) | Image sensor package and method of manufacturing the same | |
| JP2018182225A (en) | Semiconductor device manufacturing method and semiconductor device | |
| CN101593733B (en) | Encapsulation structure | |
| CN101162711A (en) | Packaging cover board, chip packaging structure and manufacturing method thereof | |
| US20090014827A1 (en) | Image sensor module at wafer level, method of manufacturing the same, and camera module | |
| TW200832724A (en) | Semiconductor package with encapsulant delamination-reducing structure and method of making the package | |
| US20080061425A1 (en) | Chip package structure and fabricating method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |