CN101593683A - Grid and forming method thereof - Google Patents
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- CN101593683A CN101593683A CNA2008101136605A CN200810113660A CN101593683A CN 101593683 A CN101593683 A CN 101593683A CN A2008101136605 A CNA2008101136605 A CN A2008101136605A CN 200810113660 A CN200810113660 A CN 200810113660A CN 101593683 A CN101593683 A CN 101593683A
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Abstract
A kind of grid formation method comprises: form gate dielectric layer in substrate; On described gate dielectric layer, form polysilicon layer; With boron fluoride ion described polysilicon layer is carried out the operation of mixing; The polysilicon layer that graphical experience is mixed and operated forms grid.Can in the process of improving the cmos device electric property, strengthen its reliability.A kind of grid is formed on the gate dielectric layer, is formed with boron ion and fluorine ion in described grid.Can make the cmos device that comprises described grid have the electricity and the reliability of improvement.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, particularly a kind of grid and forming method thereof.
Background technology
CMOS (Complementary Metal Oxide Semiconductor) (CMOS) device, for example metal oxide semiconductcor field effect transistor (MOSFETs) generally uses in the manufacture process of very lagre scale integrated circuit (VLSIC) (ULSI).How improving cmos device electric property (as reducing the power loss demand), is the constant pursuit of technological development.
For improving the electric property of cmos device, industry has been carried out many trials, provided in the Chinese patent application of " CN 1610065A " as the publication number of announcing on April 27th, 2005, in the practice, usually plant n type impurity (as phosphorus) by the polycrystalline silicon grid layer in the nmos device being carried out pre-(pre-doping) operation of mixing with cloth, perhaps the polycrystalline silicon grid layer in the PMOS device is carried out the pre-operation of mixing and plant p type impurity (as boron), to form polysilicon gate with cloth.Described pre-doping operation is in order to improve the drive current of cmos device.
With boron is example, if cloth is planted p type impurity in the PMOS device, adopts ion implantation technology usually, and ion source is BE
3, in the practice, can pass through BF
3Ionization is to produce different kinds of ions, as B
+, B
10 +, B
11 +, BF
+, BF
2 +, F
+And F
2 +, then, when described ion passes through analyzer magnet, isolate B
+, B
10 +Or B
11 +And be injected in the described PMOS device.
In addition, form described grid and and then form cmos device after, possess suitable reliability during the described cmos device work that also requires to form.In the practice, the process modification (forming technology as improving gate oxide and/or source/drain region) that need carry out many processing procedures usually in the cmos device processing procedure is with the reliability of cmos device as described in strengthening.
In sum, in the traditional handicraft, for the electric property that improves cmos device and strengthen its reliability, need to carry out multistep process modification, trivial operations.
Summary of the invention
The invention provides a kind of grid formation method, can in the process of improving the cmos device electric property, strengthen its reliability; The invention provides a kind of grid, can make the cmos device that comprises described grid have the electricity and the reliability of improvement.
A kind of grid formation method provided by the invention comprises:
In substrate, form gate dielectric layer;
On described gate dielectric layer, form polysilicon layer;
With boron fluoride ion described polysilicon layer is carried out the operation of mixing;
The polysilicon layer that graphical experience is mixed and operated forms grid.
Alternatively, described boron fluoride ion obtains by following steps:
The ion implantor platform is introduced in the boron fluoride ion source;
The ionization operation is carried out in the boron fluoride ion source of introducing, formed cluster ion;
Separate described cluster ion, obtain boron fluoride ion.
Alternatively, the step of separating described cluster ion comprises:
Adopt voltage bias technology to carry out first lock out operation, obtain the cation group;
Adopt ion analysis technology that described cation group is carried out second lock out operation, obtain boron fluoride ion.
Alternatively, described boron fluoride ion source is BF
3Alternatively, described boron fluoride ion comprises BF
+And BF
2 +In a kind of or its combination; Alternatively, when carrying out described doping operation, implantation dosage be the 1E5 atom/square li～2E5 atom/square centimeter; Alternatively, when carrying out described doping operation, the injection energy is 2kev～5kev.
A kind of grid provided by the invention is formed on the gate dielectric layer, is formed with boron ion and fluorine ion in described grid.
Alternatively, the implantation dosage of described boron ion is 1E5 atom/square centimeter～2E5 atom/square centimeter; Alternatively, the implantation dosage of described fluorine ion is 1E5 atom/square centimeter～4E5 atom/square centimeter.
Compared with prior art, technique scheme has the following advantages:
The grid formation method that technique scheme provides, by utilizing boron fluoride ion described polysilicon layer is carried out the operation of mixing, in the primary ions implant operation of described polysilicon layer, to introduce boron ion and fluorine ion simultaneously, can be under the prerequisite that does not increase operating procedure, both can be by in the grid that forms, having introduced in order to the boron ion that improves device charge carrier situation to improve device performance, can in the grid that forms, introduce fluorine ion in order to the passivation defective bit again with the enhance device reliability; That is, can in the process of improving the cmos device electric property, strengthen its reliability;
The grid that technique scheme provides, by in described grid, being formed with boron ion and fluorine ion, both can be by having introduced in order to the boron ion that improves device charge carrier situation to improve device performance, again can be by introducing fluorine ion in order to the passivation defective bit with the enhance device reliability; The electricity and the reliability of the cmos device that comprises described grid are all improved.
Description of drawings
Fig. 1 is the schematic flow sheet of the formation grid of aid illustration grid provided by the invention formation method embodiment;
Fig. 2 is that the reliability that comprises the device of the grid of using prior art and grid formation method embodiment provided by the invention acquisition detects the data comparison diagram.
Embodiment
Although below with reference to accompanying drawings the present invention is described in more detail, wherein represented the preferred embodiments of the present invention, be to be understood that those skilled in the art can revise the present invention described here and still realize advantageous effects of the present invention.Therefore, following description is appreciated that extensive instruction for those skilled in the art, and not as limitation of the present invention.
For clear, whole features of practical embodiments are not described.In the following description, be not described in detail known function and structure, because they can make the present invention because unnecessary details and confusion.Will be understood that in the exploitation of any practical embodiments, must make a large amount of implementation details, for example, change into another embodiment by an embodiment according to relevant system or relevant commercial restriction to realize developer's specific objective.In addition, will be understood that this development may be complicated and time-consuming, but only be routine work to those skilled in the art.
In the following passage, with way of example the present invention is described more specifically with reference to accompanying drawing.Will be clearer according to following explanation and claims advantages and features of the invention.It should be noted that accompanying drawing all adopts very the form of simplifying and all uses non-ratio accurately, only in order to convenient, the purpose of the aid illustration embodiment of the invention lucidly.
As shown in Figure 1, the concrete steps of formation grid comprise:
Step 11: in substrate, form gate dielectric layer.
Go up the definition device active region and finish shallow trench isolation at substrate (substrate) from the described substrate of back formation.Described substrate is including but not limited to the silicon materials that comprise semiconductor element, and for example the silicon of monocrystalline, polycrystalline or non crystalline structure or SiGe (SiGe) also can be silicon-on-insulators (SOI).
Described gate dielectric layer can comprise silicon oxide layer or silicon oxynitride layer.Described silicon oxide layer can utilize thermal oxidation technology to obtain, and described thermal oxidation technology can use high-temperature oxydation equipment or oxidation furnace carries out.The process that forms described silicon oxide layer can comprise thermal oxidation and detect step, specifically can use any traditional technology, does not repeat them here.The step that forms described silicon oxynitride layer comprises: at first form silicon oxide layer, then, to described silicon oxide layer carry out the uncoupling pecvd nitride (decoupledplasma nitridation, DPN) and the post-nitridation anneal operation.
Step 12: on described gate dielectric layer, form polysilicon layer.
Can adopt low pressure chemical vapor phase deposition (LPCVD) technology to form described polysilicon layer.In the practice, need usually described polysilicon layer is carried out the operation of mixing, in order to adjust the resistance of described polysilicon; Described doping operation utilizes ion implantation technology to carry out, and described doping operation is carried out described ion implant operation technology and can be adopted any traditional method, does not repeat them here.
In theory, by the polysilicon layer in the nmos device being carried out n type (as phosphorus) doping operation, perhaps the polysilicon layer in the PMOS device is carried out p type (as boron) doping operation.Described doping operation is in order to improve the drive current of cmos device.
But, in the actual production, consider the side effect of important function, technical maturity degree when execution described doping operate and the described doping operation of grid in device, usually only nmos device is introduced the doping operation of polysilicon layer, and the PMOS device is not introduced the doping operation of polysilicon layer.
In theory, as if doped p type impurity in the PMOS device, feasible method comprises: at first, consider that the vapour pressure of boron is very low under the simple substance form, 2000 degrees centigrade of needs even above high temperature could gasify it, so the ion source that adopts is BF usually
3Secondly, by with BF
3Ionization is to produce different kinds of ions, as B
+, B
10 +, B
11 +, BF
+, BF
2 +, F
+And F
2 +At last, isolate B
+, B
10 +Or B
11 +And be injected in the described PMOS device.
Yet actual production is found, inject B in described PMOS device
+, B
10 +Or B
11 +The time, be difficult to control and inject ion so that it arrives the predetermined degree of depth, that is, be difficult to the effect of control device performance improvement.
Think after the present inventor analyzes that use the reason that said method is difficult to the effect of control device performance improvement and be: the quality of injecting ion is less, with the bigger ion ratio of quality, under the effect of identical power, be easier to change movement tendency, in other words, more be not easy to control.Thus, the present inventor proposes, and selects for use the injection ion with bigger quality to become the direction of enhance device performance improvement effect.
In addition, do not wish again under the prerequisite of enhance device performance improvement effect, to worsen its reliability, therefore, how not only improve the reliability that device performance improves effect but also enhance device and become the subject matter that the present invention endeavours to solve.
Thus, the present inventor provides a kind of grid formation method, with BF
3For ion source produces different kinds of ions (as B
+, B
10 +, B
11 +, BF
+, BF
2 +, F
+And F
2 +) the middle BF that selects
+And/or BF
2 +As injecting ion, can in the primary ions implant operation of described polysilicon layer, introduce boron ion and fluorine ion simultaneously, can be under the prerequisite that does not increase operating procedure, both can be by in the grid that forms, having introduced in order to the boron ion that improves device charge carrier situation to improve device performance, can in the grid that forms, introduce fluorine ion in order to the passivation defective bit again with the enhance device reliability; That is, can in the process of improving the cmos device electric property, strengthen its reliability.
Step 13: described polysilicon layer is carried out the operation of mixing with boron fluoride ion.
Described boron fluoride ion comprises BF
+And BF
2 +In a kind of or its combination.When carrying out described doping operation, implantation dosage is 1E5 atom/square centimeter～2E5 atom/square centimeter, as 1.5E5 atom/square centimeter; When carrying out described doping operation, the injection energy is 2kev～5kev, as 3kev, 4kev.
Described boron fluoride ion obtains by following steps:
Step 131: the ion implantor platform is introduced in the boron fluoride ion source.Described boron fluoride ion source is BF
3Described ion implantor platform can be the implant machine (ion implantor platform) that company of Applied Materials produces.
Step 132: the ionization operation is carried out in the boron fluoride ion source of introducing, formed cluster ion.Described cluster ion comprises B
+, B
10 +, B
11 +, BF
+, BF
2 +, F
+, F
2 +With other ions.
Step 133: separate described cluster ion, obtain boron fluoride ion.
The step of separating described cluster ion comprises:
Step 1331: adopt voltage bias technology to carry out first lock out operation, obtain the cation group.Described cation group comprises B
+, B
10 +, B
11 +, BF
+, BF
2 +, F
+And F
2 +Utilize extraction electrode that described cation is inhaled to negative electric field in the described voltage bias technology, and make described cation form ion beam; Utilize the inhibition electrode that described ion beam pack is become parallel line, make it pass through the ion implantor platform.
Step 1332: adopt ion analysis technology that described cation group is carried out second lock out operation.Obtain boron fluoride ion.Different ions in the ion beam has different atomic mass units.Magnetic ion analyzer in the ion implantor platform can be separated the foreign ion (being boron fluoride ion among the present invention) of needs from the ion beam that mixes.Magnet in the analyzer can make the running orbit of ion be deflected into arc.For certain magnetic field intensity, heavy ion can not deflect into suitable angle, and the deflection of light ion is excessive, has only a kind of ion that appropriate deflection can take place, and by the center of described magnet, this ion is the impurity that is injected in the device smoothly.The radius of ion arching trajectory is by mass of ion, speed, magnetic field intensity and the electrically charged decision of ion.
Be the influence of checking the foregoing description to the effect of device performance improvement, the present inventor tests.Result of the test is as shown in table 1.
Table 1
| Selecting method | The core devices yield | Yield of devices |
| Do not introduce polysilicon layer doping operation | 6.02％ | 0 |
| Introduce polysilicon layer doping operation | 24.10％ | 4.82％ |
As shown in Table 1, after the introducing boron fluoride ion mixes operation in polysilicon layer, compare with the prior art of not introducing polysilicon layer doping operation, the core devices yield increases to 24.10% by 6.02%; And yield of devices (considering core devices yield and input and output device yield simultaneously) increases to 4.82% by 0.As seen, in polysilicon layer, introduce boron fluoride ion doping operation, be beneficial to the improvement of device performance.
In addition, be the influence of checking the foregoing description to the device electric property, the present inventor has carried out the leakage current detection to the test piece of using in the above-mentioned test.Testing result as shown in Figure 2.As shown in Figure 2, curve 1 and 2 is not introduced polysilicon layer doping operation and introduces the polysilicon layer doping leakage current testing result when operating respectively in order to sign.As seen from Figure 2, compare with the data that curve 1 indicates, in the data that curve 2 indicates along with saturation current value (I
Dsat) increase, leakage current (I
Off) increase slowlyer; Perhaps, when causing identical leakage current, required saturation current value is bigger; In other words, introducing boron fluoride ion doping operation back device electric property improves.
The present inventor also considers, only the PMOS device introduced P type ion usually, therefore, also the PMOS device carried out the reliability detection, and the testing result that testing result is recorded when only introducing the boron ion in polysilicon layer contrasts.Correction data is as shown in table 2.
The reliability testing that described PMOS device is carried out comprise the negative bias thermal instability test (negative bias temperature instability, NBTI).Testing time continues 10000 seconds.Provide corresponding two groups of grid voltage (V
g=1.9V and V
g=data contrast 2.0V) time.
Table 2
| Inject ion | V gLeakage current rate of change during=1.9V | V gLeakage current rate of change during=2.0V |
| BF 2 + | 6.65％ | 7.20％ |
| B | 7.50％ | 8.45％ |
As shown in Table 2, introduce boron fluoride ion and mix after the operation in polysilicon layer, compare when boron ion polysilicon layer mixes operation with only introducing, the leakage current rate of change decreases.As example, V
gLeakage current rate of change during=1.9V reduces to 6.65% by 7.50%; And V
gLeakage current rate of change during=2.0V reduces to 7.20% by 8.45%.As seen, in polysilicon layer, introduce boron fluoride ion doping operation, be beneficial to the raising of device reliability.
In sum, the grid formation method that technique scheme provides, by utilizing boron fluoride ion described polysilicon layer is carried out the operation of mixing, in the primary ions implant operation of described polysilicon layer, to introduce boron ion and fluorine ion simultaneously, can be under the prerequisite that does not increase operating procedure, both can be by in the grid that forms, having introduced in order to the boron ion that improves device charge carrier situation to improve device performance, can in the grid that forms, introduce fluorine ion in order to the passivation defective bit again with the enhance device reliability; That is, can in the process of improving the cmos device electric property, strengthen its reliability.
Step 14: the polysilicon layer that graphical experience is mixed and operated forms grid.
The using plasma etching technics is carried out described graphical operation.
Be formed with boron ion and fluorine ion in the described grid that obtains.The grid that technique scheme forms, by in described grid, being formed with boron ion and fluorine ion, both can be by having introduced in order to the boron ion that improves device charge carrier situation to improve device performance, again can be by introducing fluorine ion in order to the passivation defective bit with the enhance device reliability; The electricity and the reliability of the cmos device that comprises described grid are all improved.
In other words, the present invention also provides a kind of grid, and described grid is formed on the gate dielectric layer, is formed with boron ion and fluorine ion in described grid.Described fluorine ion is in order to the passivation defective bit, thereby the reduction interface trap density is beneficial to the enhance device reliability; Described boron ion improves the device electric property then in order to improve device charge carrier situation.Especially, the implantation dosage of described boron ion is 1E5 atom/square centimeter～2E5 atom/square centimeter, as 1.5E5 atom/square centimeter; The implantation dosage of described fluorine ion is 1E5 atom/square centimeter～4E5 atom/square centimeter, as 1.5E5 atom/square centimeter, 2E5 atom/square centimeter or 3E5 atom/square centimeter.(utilize described grid to improve the test of device electric property and reliability and related data, do not repeat them here referring to the associated description among the embodiment of explanation grid formation method.)
What need emphasize is that not elsewhere specified step all can use conventional methods acquisition, and concrete technological parameter is determined according to product requirement and process conditions.
Although the present invention has been described and has enough described embodiment in detail although describe by the embodiment at this, the applicant does not wish by any way the scope of claims is limited on this details.Other to those skilled in the art advantage and improvement are conspicuous.Therefore, relative broad range the invention is not restricted to represent and the specific detail of describing, equipment and the method and the illustrative example of expression.Therefore, can depart from these details and do not break away from the spirit and scope of the total inventive concept of applicant.
Claims (10)
1. a grid formation method is characterized in that, comprising:
In substrate, form gate dielectric layer;
On described gate dielectric layer, form polysilicon layer;
With boron fluoride ion described polysilicon layer is carried out the operation of mixing;
The polysilicon layer that graphical experience is mixed and operated forms grid.
2. grid formation method according to claim 1 is characterized in that, described boron fluoride ion obtains by following steps:
The ion implantor platform is introduced in the boron fluoride ion source;
The ionization operation is carried out in the boron fluoride ion source of introducing, formed cluster ion;
Separate described cluster ion, obtain boron fluoride ion.
3. grid formation method according to claim 2 is characterized in that, the step of separating described cluster ion comprises:
Adopt voltage bias technology to carry out first lock out operation, obtain the cation group;
Adopt ion analysis technology that described cation group is carried out second lock out operation, obtain boron fluoride ion.
4. grid formation method according to claim 2 is characterized in that: described boron fluoride ion source is BF
3
5. grid formation method according to claim 1 and 2 is characterized in that: described boron fluoride ion comprises BF
+And BF
2 +In a kind of or its combination.
6. grid formation method according to claim 1 is characterized in that: when carrying out described doping operation, the implantation dosage of boron fluoride ion is 1E5 atom/square centimeter～2E5 atom/square centimeter.
7. grid formation method according to claim 1 is characterized in that: when carrying out described doping operation, the injection energy is 2kev～5kev.
8. a grid is formed on the gate dielectric layer, it is characterized in that: be formed with boron ion and fluorine ion in described grid.
9. grid according to claim 8 is characterized in that: the implantation dosage of described boron ion is 1E5 atom/square centimeter～2E5 atom/square centimeter.
10. grid according to claim 8 is characterized in that: the implantation dosage of described fluorine ion is 1E5 atom/square centimeter～4E5 atom/square centimeter.
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|---|---|---|---|
| CN2008101136605A CN101593683B (en) | 2008-05-29 | 2008-05-29 | Grid and formation method thereof |
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| CN101593683B CN101593683B (en) | 2011-03-23 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102353882A (en) * | 2011-06-09 | 2012-02-15 | 北京大学 | Method for testing trap density and position of gate dielectric layer of semiconductor device |
| CN104425226A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Floating gate and forming method thereof, and flash memory unit and forming method thereof |
| CN110957340A (en) * | 2019-12-25 | 2020-04-03 | 上海华力微电子有限公司 | CMOS image sensor and manufacturing method thereof |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5629221A (en) * | 1995-11-24 | 1997-05-13 | National Science Council Of Republic Of China | Process for suppressing boron penetration in BF2 + -implanted P+ -poly-Si gate using inductively-coupled nitrogen plasma |
| US6153456A (en) * | 1998-01-14 | 2000-11-28 | Vlsi Technology, Inc. | Method of selectively applying dopants to an integrated circuit semiconductor device without using a mask |
| CN1134051C (en) * | 2000-12-19 | 2004-01-07 | 中国科学院微电子中心 | Method for generating extended super-shallow source-drain region by combining amorphous pre-injection of Ge with low energy injection |
| JP2002314064A (en) * | 2001-04-11 | 2002-10-25 | Rohm Co Ltd | Manufacturing method of semiconductor device |
| CN1206711C (en) * | 2002-03-28 | 2005-06-15 | 华邦电子股份有限公司 | Method for preparing self-aligning silicide of metal oxide semiconductor |
| JP4345895B2 (en) * | 2005-10-20 | 2009-10-14 | 日新イオン機器株式会社 | Ion source operation method and ion implantation apparatus |
-
2008
- 2008-05-29 CN CN2008101136605A patent/CN101593683B/en active Active
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102353882A (en) * | 2011-06-09 | 2012-02-15 | 北京大学 | Method for testing trap density and position of gate dielectric layer of semiconductor device |
| CN102353882B (en) * | 2011-06-09 | 2014-02-19 | 北京大学 | Method for testing trap density and position of gate dielectric layer of semiconductor device |
| US9018968B2 (en) | 2011-06-09 | 2015-04-28 | Peking University | Method for testing density and location of gate dielectric layer trap of semiconductor device |
| CN104425226A (en) * | 2013-08-20 | 2015-03-18 | 中芯国际集成电路制造(上海)有限公司 | Floating gate and forming method thereof, and flash memory unit and forming method thereof |
| CN104425226B (en) * | 2013-08-20 | 2017-12-29 | 中芯国际集成电路制造(上海)有限公司 | Floating boom and forming method thereof, flash cell and forming method thereof |
| CN110957340A (en) * | 2019-12-25 | 2020-04-03 | 上海华力微电子有限公司 | CMOS image sensor and manufacturing method thereof |
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| CN101593683B (en) | 2011-03-23 |
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