CN101588329A - Spread spectrum communication multiphase matching wave filter capture circuit and design method thereof - Google Patents
Spread spectrum communication multiphase matching wave filter capture circuit and design method thereof Download PDFInfo
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- CN101588329A CN101588329A CNA2008100979219A CN200810097921A CN101588329A CN 101588329 A CN101588329 A CN 101588329A CN A2008100979219 A CNA2008100979219 A CN A2008100979219A CN 200810097921 A CN200810097921 A CN 200810097921A CN 101588329 A CN101588329 A CN 101588329A
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Abstract
The invention discloses a spread spectrum communication multiphase matching wave filter capture circuit and a design method thereof. An M=m*n multiphase matching wave filter divides M additive operations into m groups to carry out, each group of additive operations finishes the additive operation of n data and then m groups of results are summated by a production line so as to obtain a final result. A traditional matching wave filter is in two special structures of the multiphase matching wave filter, under other conditions, the multiphase matching wave filter compromises circuit speed and circuit area, and reasonable multiphase decomposition can reduce the circuit area on the premise of ensuring the circuit speed.
Description
Technical field
The present invention relates to spread spectrum communication baseband signal capture technique field, particularly a kind of matching wave filter capture circuit and method for designing thereof.
Background technology
Matched filter is finished local spreading code and the related operation of importing data, promptly
H[i wherein] be local spreading code, x (i) is the input data, y (n) be local spreading code and the related operation result who imports data.The tradition matched filter has two kinds of implementations: directly I type and directly II type implementation.The direct I type implementation of matched filter as shown in Figure 1, the input storage is in shift register, with corresponding the multiplying each other of local spreading code of same length, the result who obtains sues for peace by add tree, finishes related operation then.The structure of add tree as shown in Figure 2, the input data bit width of every grade of adder is identical, adder is fully utilized, so circuit area is less, but add tree inputs to and has multistage adder between output, so time-delay is bigger.The direct II type implementation of matched filter after input data and all local spreading codes multiply each other, is sued for peace by the adder between streamline as shown in Figure 3 step by step.Only there is an adder between streamline, so the time-delay of circuit is less.But carrying out along with summation, the summed result span is increasing, data bit width also increases accordingly, and another input of adder is h[i] x (i), this data bit width remains unchanged always, so two input data bit widths of adder are inconsistent, progression is high more, data bit width differs bigger and bigger, and adder is not fully utilized, and causes very big circuit area.
Summary of the invention
The purpose of this invention is to provide a kind of leggy (PloyPhase) matched filter, this multiphase matching wave filter is compared with the direct I type implementation of equal length, littler time-delay is arranged, compare with the direct II type implementation of equal length, littler area is arranged, well reach the compromise of time-delay and area, improved circuit performance.
Multiphase matching wave filter method for designing provided by the invention is such: establishing this matched filter length is M, coefficient sequence be h[0], h[1] ... h[M-1)] }, the leggy that carries out M=m*n decomposes, the physical significance of this matched filter length is: the progression of matched filter, the physical significance of coefficient sequence is: local spreading code carries out the sequence after the corresponding sampling, the physical significance of m and n is: the leggy decomposition coefficient, m and n are integer and m*n equals M, and this method for designing in turn includes the following steps:
1) the input data move into the shift register that length is M successively, and when each rising edge clock arrived, the data in all shift registers moved right, and the data of low order end are moved out of, and new input data are moved into the high order end of shift register;
2) leggy for M=m*n decomposes, and from the shift register high order end, every m level is extracted a signal out, extracts n signal { d altogether out
0, d
1D
N-1;
3) M also every m of local spreading code takes out one, obtains the 0th group of local spread spectrum codes C
0=h[0], h[m] ... h[m* (n-1)] }, the 1st group of local spread spectrum codes C
1=h[1], h[m+1] ... h[m* (n-1)+1] }, and the like, organize local spread spectrum codes C until m-1
M-1=h[m-1], h[2m-1] ... h[mn-1] }, obtain m altogether and organize local spreading code, every group of n data;
4) the 0th group of local spread spectrum codes C
0N data with { d
0, d
1D
N-1Correspondence multiplies each other, and sues for peace by add tree again, obtains the 0th part and S
0=h[0] d
0+ h[m] d
1+ ... + h[m* (n-1)] d
N-1, the 1st group of local spread spectrum codes C
1N data with { d
0, d
1D
N-1Correspondence multiplies each other, and sues for peace by add tree again, obtains the 1st part and S
1=h[1] d
0+ h[m+1] d
1+ ... + h[m* (n-1)+1] d
N-1, and the like, organize local spread spectrum codes C until m-1
M-1With { d
0, d
1D
N-1Correspondence multiplies each other and addition, obtains m-1 partly and S
M-1=h[m-1] d
0+ h[2m-1] d
1+ ... + h[mn-1] d
N-1
5) S
M-1Through behind the one-level register with S
M-2Addition obtains m-2 level summed result A
M-2, A
M-2Through behind the one-level register with S
M-3Addition obtains m-3 level summed result A
M-3, and the like, until A
1Through behind the one-level register with S
0Addition obtains the 0th grade of summed result A
0, A
0Be final correlated results y (n);
During above-mentioned M=m*n decomposes, work as m=1, during n=M, step 2) every grade of shift register is all extracted signal out in, extracts M signal altogether out, local spreading code only can obtain one group in the step 3), and be exactly h[0], h[1] ... h[M] } itself, the two correspondence multiplies each other, addition promptly obtains final result again, so the heterogeneous decomposition of M=1*M just obtains direct I type implementation.
Work as m=M, during n=1, step 2) M level shift register only can be extracted a signal out in, promptly import data itself, local spreading code will be removed the M group in the step 3), and every group is had only 1 data, importing data then multiplies each other with M local spreading code respectively, sue for peace by the M level production line of step 5) at last, obtain final result, so the multinomial decomposition of M=M*1 just obtains direct II type implementation.
In other cases, multiphase matching wave filter is divided into m group with M add operation to carry out, every group of add operation of finishing n data, and then finish the summation that m organizes the result by streamline, obtain final result.Compare with M the add operation of once finishing of direct I type implementation, reduced operand, improved arithmetic speed.Compare S in the multiphase matching wave filter with direct II type implementation
0To S
M-1Summation operation can finish with add tree, adder has obtained more fully utilizing, and has reduced circuit area.
The invention provides the multiphase matching wave filter method for designing and point out that direct I type and direct II type matched filter are two kinds of special circumstances of multiphase matching wave filter, reasonably carrying out leggy decomposes, can avoid big time-delay of direct I type implementation and the direct big area of II type implementation, well reach the compromise of speed and area.
Description of drawings
Introduce principle, structure, characteristics and the implementation thereof of multiphase matching wave filter of the present invention in detail below in conjunction with accompanying drawing:
The direct I type of Fig. 1 matched filter
The add tree structure of the direct I type of Fig. 2 matched filter
The direct II type of Fig. 3 matched filter
The data chainning of Fig. 4 multiphase matching wave filter
The summation chain of Fig. 5 multiphase matching wave filter
The data chainning of the multiphase matching wave filter of Fig. 6 M=12 (decomposition of 3*4 leggy)
The summation chain of the multiphase matching wave filter of Fig. 7 M=12 (decomposition of 3*4 leggy)
Embodiment
At first introduce the principle of multiphase matching wave filter, for simplicity, a kind of leggy of introducing the matched filter of length M=12 earlier decomposes (M=3*4 decomposition), and all the other decomposition are similar.If the transfer function of matched filter is H (z)=h[0]+h[1] z
-1+ ... + h[10] z
-10+ h[11] z
-11, per three of the data item in the expression formula is taken out one, can obtain three groups of data, four every group, as shown in the formula:
H(z)＝(h[0]+h[3]z
-3+h[6]z
-6+h[9]z
-9)+(h[1]z
-1+h[4]z
-4+h[7]z
-7+h[10]z
-10)+(h[2]z
-2+h[5]z
-5+h[8]z
-8+h[11]z
-11)
＝(h[0]+h[3]z
-3+h[6]z
-6+h[9]z
-9)+z
-1(h[1]+h[4]z
-3+h[7]z
-6+h[10]z
-9)+z
-2(h[2]+h[5]z
-3+h[8]z
-6+h[11]z
-9)
=S
0+ z
-1S
1+ z
-2S
2S wherein
0=h[0]+h[3] z
-3+ h[6] z
-6+ h[9] z
-9, S
1=h[1]+h[4] z
-3+ h[7] z
-6+ h[10] z
-9S
2=h[2]+h[5] z
-3+ h[8] z
-6+ h[11] z
-9
Can realize S earlier like this
0, S
1And S
2, addition behind the suitable time-delay then just can realize H (z).As shown in Figure 6: A, B, C, D is respectively 1, z
-3, z
-6And z
-9, among Fig. 7
Be many input add tree,
Be two input summers, so S has been finished in Fig. 7 lower part
0, S is finished in the centre
1, finish S above
2, S then
1Through one-level time-delay, S
2After the two-stage time-delay, add together, just obtained polyphase structure S
0+ z
-1S
1+ z
-2S
2
Fig. 6 is called data chainning, finishes the shifting function of data.Fig. 7 is called the summation chain, finishes summation operation.Summation is carried out in two steps.The first step is finished the additions of four input data, and each input data bit width is identical, and this is by among Fig. 6
Add tree is finished.Second step with the result of upper level register and
The result carry out addition, by among Fig. 6
Adder is finished,
Two input signal bit wides of adder are different, and one is the input data bit width, another previous stage register data bit wide.
As represented among Fig. 7, the leggy implementation is 12 all add operations to be divided into 3 times carry out, and finishes the addition of four numbers at every turn, utilizes three class pipeline with three results added again, obtains final result.To utilize add tree once to finish all 12 add operations different, also with direct II type that 12 add operation mean allocation are different to 12 level production lines with direct I type for these.As shown in table 1.
The contrast of three kinds of matched filter implementations of table 1.
| The add operation sum | Addition is realized circuit | Every grade of add operation of finishing | |
| Direct I type | 12 | 12 input add tree | 12 |
| Direct II type | 12 | 12 grades of flowing |
1 |
| Polyphase structure | 12 | 3 grades of flowing water | 4 |
As can be seen from Table 1, directly the I type is finished 12 add operations by add tree, and time-delay is maximum.Directly only need to finish 1 add operation between the every level production line of II type, so time-delay is minimum.Every grade of needs of polyphase implementation are finished 4 add operations, and time-delay is placed in the middle.
On area, directly the addition of I type is finished by add tree, and wherein two of adder input data bit widths are the same, so each adder all is fully used the circuit area minimum.Directly the input bit wide of each adder of II type is all different, one is the input data bit width, another previous stage register data bit wide, and it is always big more greater than importing data bit width and arriving the back more, so directly the adder of II type is not fully utilized the circuit area maximum.In the leggy implementation
The input data bit width of add tree is the same,
Adder input data bit width is different, so polyphase implementation mode area is moderate.
The leggy that is generalized to M=m*n decomposes, and comprises following design procedure successively:
1) the input data move into the shift register that length is M successively, and from the shift register high order end, every m level is extracted a signal out, extracts n signal { d altogether out
0, d
1D
N-1, as shown in Figure 4.
2) M also every m of local spreading code takes out one, obtains m altogether and organizes local spreading code, and every group of n data are respectively the 0th group of local spread spectrum codes C
0=h[0], h[m] ... h[m* (n-1)] }, the 1st group of local spread spectrum codes C
1=h[1], h[m+1] ... h[m* (n-1)+1] }, and the like, organize local spread spectrum codes C up to m-1
M-1=h[m-1], h[2m-1] ... h[mn-1] }.
3) C
0N data with { d
0, d
1D
N-1Correspondence multiplies each other, and passes through
Obtain S after the add tree summation
0=h[0] d
0+ h[m] d
1+ ... + h[m* (n-1)] d
N-1C
1N data with { d
0, d
1D
N-1Correspondence multiplies each other, and passes through
As obtaining S after the summation of method tree
1=h[1] d
0+ h[m+1] d
1+ ... + h[m* (n-1)+1] d
N-1And the like, up to C
M-1With { d
0, d
1D
N-1Correspondence multiplies each other, and passes through
The add tree summation obtains S
M-1=h[m-1] d
0+ h[2m-1] d
1+ ... + h[mn-1] d
N-1, as shown in Figure 5.
4) S
M-1, S
M-2S
1, S
0Carry out corresponding delay and summation by streamline, obtain final correlated results, as shown in Figure 5, A wherein
M-2～A
0Summed result for the corresponding stage streamline.
During above-mentioned M=m*n decomposes, work as m=1, during n=M, every grade of shift register is all extracted signal out in the step 1), extracts M signal altogether out, step 2) local spreading code only can obtain one group in, and be exactly h[0], h[1] ... h[M] } itself, the two correspondence multiplies each other, addition promptly obtains final result again, so the heterogeneous decomposition of M=1*M just obtains direct I type implementation.
Work as m=M, during n=1, M level shift register only can be extracted a signal out in the step 1), promptly import data itself, step 2) in local spreading code will be removed M group, every group is had only 1 data, importing data then multiplies each other with M local spreading code respectively, sue for peace by the M level production line of step 4) at last, obtain final result, so the multinomial decomposition of M=M*1 just obtains direct II type implementation.
In other cases, multiphase matching wave filter is divided into m group with M add operation to carry out, every group of add operation of finishing n data, and then finish the summation that m organizes the result by streamline, obtain final result.Compare with M the add operation of once finishing of direct I type implementation, reduced operand, improved arithmetic speed.Compare S in the multiphase matching wave filter with direct II type implementation
0To S
M-1Summation operation can finish with add tree, adder has obtained more fully utilizing, and has reduced circuit area.
Claims (6)
1, a kind of method for designing of multiphase matching wave filter, if this matched filter length is M, coefficient sequence be h[0], h[1] ... h[M-1)] }, the leggy that carries out M=m*n decomposes, the physical significance of this matched filter length is: the progression of matched filter, the physical significance of coefficient sequence is: local spreading code carries out the sequence after the corresponding sampling, the physical significance of m and n is: the leggy decomposition coefficient, m and n are integer and m*n equals M, it is characterized in that this method for designing in turn includes the following steps:
1) the input data move into the shift register that length is M successively, and when each rising edge clock arrived, the data in all shift registers moved right, and the data of low order end are moved out of, and new input data are moved into the high order end of shift register;
2) leggy for M=m*n decomposes, and from the shift register high order end, every m level is extracted a signal out, extracts n signal { d altogether out
0, d
1D
N-1;
3) M also every m of local spreading code takes out one, obtains the 0th group of local spread spectrum codes C
0=h[0], h[m] ... h[m* (n-1)] }, the 1st group of local spread spectrum codes C
1=h[1], h[m+1] ... h[m* (n-1)+1] }, and the like, organize local spread spectrum codes C until m-1
M-1=h[m-1], h[2m-1] ... h[mn-1] }, obtain m altogether and organize local spreading code, every group of n data;
4) the 0th group of local spread spectrum codes C
0N data with { d
0, d
1D
N-1Correspondence multiplies each other, and sues for peace by add tree again, obtains the 0th part and S
0=h[0] d
0+ h[m] d
1+ ... + h[m* (n-1)] d
N-1, the 1st group of local spread spectrum codes C
1N data with { d
0, d
1D
N-1Correspondence multiplies each other, and sues for peace by add tree again, obtains the 1st part and S
1=h[1] d
0+ h[m+1] d
1+ ... + h[m* (n-1)+1] d
N-1, and the like, organize local spread spectrum codes C until m-1
M-1With { d
0, d
1D
N-1Correspondence multiplies each other and addition, obtains m-1 partly and S
M-1=h[m-1] d
0+ h[2m-1] d
1+ ... + h[mn-1] d
N-1
5) S
M-1Through behind the one-level register with S
M-2Addition obtains m-2 level summed result A
M-2, A
M-2Through behind the one-level register with S
M-3Addition obtains m-3 level summed result A
M-3, and the like, until A
1Through behind the one-level register with S
0Addition obtains the 0th grade of summed result A
0, A
0It is final correlated results.
2, the method for designing of multiphase matching wave filter according to claim 1 is characterized in that: the method for designing of matched filter is a kind of general method for designing, is not subject to the type and the length of spreading code.
3, a kind of multiphase matching wave filter carries out the M=m*n leggy and decomposes, and it is characterized in that: work as m=1, during n=M, this multiphase matching wave filter changes direct I type matched filter into.
4, multiphase matching wave filter according to claim 3 is characterized in that: work as m=M, during n=1, this multiphase matching wave filter changes direct II type matched filter into.
5, multiphase matching wave filter according to claim 3, it is characterized in that: when m is the integer of 1＜m＜M, this multiphase matching wave filter is divided into the m group with M add operation to carry out, every group of add operation of finishing n data by add tree, adder input data bit width in the add tree is the same, and then finish m group result's summation by streamline, obtain final correlated results.
6, multiphase matching wave filter according to claim 3 is characterized in that: when m was the integer of 1＜m＜M, the circuit delay of this multiphase matching wave filter was less than direct I type matched filter, and circuit area is less than direct II type matched filter.
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Cited By (1)
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| CN106656106A (en) * | 2016-12-26 | 2017-05-10 | 哈尔滨工程大学 | Frequency domain adaptive matched filter method |
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| US20030067963A1 (en) * | 1998-12-11 | 2003-04-10 | Miller Timothy R. | Mode controller for signal acquisition and tracking in an ultra wideband communication system |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106656106A (en) * | 2016-12-26 | 2017-05-10 | 哈尔滨工程大学 | Frequency domain adaptive matched filter method |
| CN106656106B (en) * | 2016-12-26 | 2019-04-23 | 哈尔滨工程大学 | A kind of frequency domain adaptive matched-filter approach |
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Application publication date: 20091125 |