CN1297294A - Multi-phase differential digital match filter for CDMA and its implementing method - Google Patents

Abstract

A CDMA multi-phase differential digital match filter is composed of latch, more multipliers, more adders, more delay units and a differential feedback unit. Its advantages are the least number of MAC units, high versatility, small chip area, low power consumption and high frequency.

Description

Multi-phase differential digital match filter for CDMA and its implementation

The present invention relates to a kind of multi-phase differential digital match filter for CDMA and its implementation, belong to the code division multiplex system technical field of using spread spectrum.

In Direct-Spread code division multiple access (DS/CDMA) system, spreading code is in core status, and all key technologies all are to launch around spreading code.People utilize the good correlation properties of pseudo noise code to realize the search identification of travelling carriage to the base station, obtain clock synchronization accurately; Estimate by the time-delay of capture circuit realizing route on the other hand.Early stage people adopt simple sliding correlation method that spreading code is caught, although this method has the simple advantage of realization, but it is often very long that the shortcoming of its maximum is caught consumed time exactly, to the high speed wireless data transmission fast synchronously, the requirement of catching fast can't satisfy.Adopt passive digital matched filter can greatly shorten capture time, the capture time of theoretical proof digital matched filter is the shortest.But it is long more that matched filter also exists spreading code, and tap number is many more, takies the big more defective of hardware resource, limited its application.Nowadays Shang Yong matched filter tap number mostly is 64 most.Along with making rapid progress of very large scale integration technology, the cost of matched filter has had remarkable decline now, has progressively obtained being extensive use of.

Matched filter is actually finishes following computing: $R\left(n\right)=\underset{i=0}{\overset{N-1}{\mathrm{\Σ}}}{a}_i{x}_{i+n}---\left(1\right)$

Wherein, ${\left\{a_i\right\}}_{i=0}^{N-1}$ Be local coefficient sequence, $\{x_i{\}}_{i=0}^{\∞}$ Be receiving sequence, the correlation of gained is calculated in R (n) expression.Generally speaking, the coefficient sequence value ± 1}, and receiving sequence is through the quantized values sequence after the A/D conversion.

The shared hardware resource of digital matched filter is divided into two classes: the one, and every grade delay unit number, the 2nd, every grade multiplication and adder unit (hereinafter to be referred as MAC).The growth that all is directly proportional with tap number of these two kinds of resources makes that the scale of hardware matched filter is extremely huge.Usually the performance of estimating filter mainly contains three indexs: the hardware resource that takies (also claiming effective area), consumed power and maximum operating frequency.Area occupied is little, and consumed power is few, and the operating frequency height is the target that the designer pursues.

Traditional matched filter structure has two kinds, as shown in Figure 1 and Figure 2.Wherein Figure 1 shows that centralized horizontal matched filter, the multiplication of this each tap of filter and addition are to distinguish computing, at first multiplying are carried out in each tap, implement add operation in the product set to each tap then.This structure need a huge adding network, and when tap number was a lot, adding network must be used pipelining owing to adopt concentrated computing, had increased the complexity of control.In a word, this filter area occupied is big, the power consumption height, and maximum operating frequency is low.Figure 2 shows that distributed matched filter, this filter segment ground has overcome the defective of centralized horizontal matched filter, it adopts the distributed arithmetic structure, calculate multiplication and addition respectively in each tap, make that like this its operating frequency can be very high, but still exist the bigger weakness of area occupied.

Generally speaking, behind the exponent number of given filter and the quantization level number, just determine the number of delay unit, can not reduce it again, this just impels people to study the internal performance of spreading code, reduces the number of MAC as far as possible.

The purpose of this invention is to provide a kind of multi-phase differential digital match filter for CDMA, the structure of this matched filter has minimum MAC unit number, thereby can reduce chip area, improves operating frequency.

Another object of the present invention provides a kind of implementation method of multi-phase differential digital match filter for CDMA.

The implementation method of multi-phase differential digital match filter for CDMA of the present invention is such: the list entries of establishing received signal for ... x _NX ₀, the coefficient sequence of this matched filter is { b _N-q-1, b _N-q-2..., b _i..., b ₁, b ₀; the physical significance of this list entries is: the binary bit sequence that the quantification of sampling to received signal obtains; the physical significance of this coefficient sequence is: represent the fixing coefficient taken advantage of in each tap of this matched filter, it typically is the binary sequence of 1 bit; Wherein: the q phase place is represented leggy, and q is an integer; N represents the progression or the tap number of the matched filter of conventional method, and N is an integer; It is characterized in that: this implementation method comprises the steps: at least

(1) above-mentioned list entries is under clock signal drives, from x ₀Latch is sent in beginning in regular turn, with guarantee between the quantization bit synchronously;

(2), send into an input of each all particular factor multipliers simultaneously by data/address bus through each signal of the list entries behind the latch;

(3) send into each particular factor of this matched filter correspondence respectively at another input of above-mentioned each multiplier, i.e. b _N+q-1Send into the left end of multiplier (321), b _N+q-2Send into the left end of multiplier (322), and the like, until b ₀Send into the left end of multiplier (326);

(4), the result of gained is delivered to simultaneously accordingly input, i.e. a y of above-mentioned each adder respectively through the multiplying of above-mentioned each multiplier ₁Send into an input of adder (331), y ₂Deliver to an input of adder (332), and the like, until y _N+q-1Deliver to an input of adder (335);

(5) send into the correlation of depositing in each delay unit respectively at another input of above-mentioned each adder, i.e. the z that exports from delay unit (341) ₁Send into another input of adder (331), from the z of delay unit (342) output ₂Deliver to another input of adder (332), and the like, until z from delay unit (345) output _N+q-1Deliver to another input of adder (335); And be positioned at the output y of the multiplier (326) of final stage ₀Then directly send into delay unit (341); Above-mentioned each delay unit all is clock cycle of time-delay to be about to signal output;

(6) add operation of above-mentioned each adder of process, the result of gained is sent into the next stage delay unit adjacent with this adder successively, delay unit (342) is sent in the output that is adder (331), delay unit (343) is sent in the output of adder (332), and the like, send into delay unit (346) until the output of adder (335);

(7) the output V (n) that is positioned at top delay unit (346) sends into the adder (336) of its front end, so that output U (n) addition with differential feedback unit, this differential feedback unit is made up of q delay unit, and promptly the output R (n) of this matched filter exports the last output result that just can obtain this matched filter through the output valve U (n) that obtains of q delay unit (347) and V (n) after by adder (336) addition.

Particular factor sequence { the b of matched filter in the said method _N-q-1, b _N-q-2..., b _i..., b ₁, b ₀Obtain according to following formula: suppose that multi-phase differential digital match filter wherein is the q phase place, then:

In the formula, coefficient a _iIt is the coefficient of traditional matched filter.

Least significant end at matched filter is provided with a differential feedback unit, and this differential feedback unit is made up of a plurality of delay unit, and the number of a plurality of delay units wherein equates with the number of the leggy of this filter.

The method of this phase difference can be widely used in the matched filter as the multiple binary sequence of 64 tap Hadamard sequences multi-phase differential digital match filters in the IS95 system, mobile communication, radar, Digital Signal Processing class.

Multi-phase differential digital match filter of the present invention is achieved in that establishing it has the q phase place, is characterized in that: include following parts: the latch that list entries is latched; Back at this latch is connected with N+q multiplier by data/address bus, and each multiplier of these multipliers all is that an one input links to each other with the output of this latch by bus, and its another input is then sent into a specific coefficient sequence; An input of the adder that the output of above-mentioned each grade multiplier is all corresponding with it links to each other, another input of these adders then links to each other with the output of its upper level delay unit, and the output of these adders then links to each other with the input of its next stage delay unit respectively; The output of the output of the last grade delay unit and a differential feedback unit is connected to an adder, and the summation gained result of this adder is exactly final correlation; Also comprise a differential feedback unit, this differential feedback unit is made up of the continuous institute of a plurality of delay units, and the number of a plurality of delay units wherein equates with the number of the leggy of this filter, the input of this differential feedback unit is the correlation of matched filter output, and its output valve then is connected to the input of the adder of the last grade.

The specific coefficient that above-mentioned multiplier is taken advantage of is sequence { b _N-q-1, b _N-q-2..., b _i..., b ₁, b ₀, the algorithm of this sequence is as follows: suppose that multi-phase differential digital match filter wherein is the q phase place, then:

In the formula, coefficient a _iIt is the coefficient of traditional matched filter.

Above-mentioned particular factor multiplier, adder, delay unit and differential feedback unit can adopt on-site programmable gate array FPGA (Field Programmable Gate Array) integrated chip to realize it.

This multi-phase differential digital match filter can adopt application-specific integrated circuit ASIC (Application SpecificIntegrated Circuit) chip to make.

Characteristics of the present invention provide a kind of concrete structure of multi-phase differential digital match filter device, and the multi-phase differential that this matched filter uses is a kind of universal method, not at certain specific sign indicating number.Utilize algorithm of the present invention, can reduce chip area effectively, reduce power consumption, improve operating frequency.

Introduce Filter Structures of the present invention, characteristics and its implementation in detail below in conjunction with accompanying drawing:

Fig. 1 is the structural representation of traditional centralized horizontal matched filter.

Fig. 2 is the structural representation of traditional distributed matched filter.

Fig. 3 is the structural representation of multi-phase differential digital match filter of the present invention.

Fig. 4 is a Maxplus II gate leve simulation waveform schematic diagram.

At first introduce the operation principle of multi-phase differential implementation method: can find out by above-mentioned (1) formula, if a _i=0, then corresponding M AC unit can omit.Document " A Pipelined Digital Differential Matched Filter FPGA Implementation ﹠amp; VLSI Design " (" use FPGA and VLSI design and realize streamline digital differential matched filter " publishes in IEEE 1996CUSTOM INTEGRATED CIRCUITS CONFERENCE, pp75-78) thought of adjacent difference has been proposed, utilize the distance of swimming distribution character of m sequence, reduced the MAC unit.But this method only sequence to specific is effective, and does not consider the further intrinsic characteristic of sequence.The present invention then is extended to it arbitrary interval difference, is called multi-phase differential.

For sake of convenience, the sequence that claims the sequence interleaving of former binary sequence and q phase place of its delay to subtract each other gained is a q phase difference sequence.

In order to calculate correlation R (n), at first calculate the difference of correlation, be called difference correlation D (n): $D\left(n\right)=R\left(n\right)-R(n-q)$ $\underset{i=-1}{\overset{N-1}{\mathrm{\Σ}}}{b}_i{x}_{i+n}$ $\underset{i=0}{\overset{l-1}{\mathrm{\Σ}}}(-a_i)x_{i+n-q}+\underset{i=1}{\overset{N-1}{\mathrm{\Σ}}}(a_{i-q}-a_i)x_{i+n-q}$ $\underset{i=N}{\overset{N+l-1}{\mathrm{\Σ}}}{a}_{i-q}{x}_{i+n-q}----\left(2\right)$ By following formula as seen, D (n) is the poor of R (n) and R (n-q), and R (n-q) is the correlation that calculates than R (n) Zao q clock cycle.After calculating D (n), R (n-q) addition with previous preservation just can obtain correct correlation result.Because the multi-phase differential matched filter will calculate the task of R (n) and be converted into calculating difference correlation D (n), so gain the name.

According to definition, sequence $\{b_i{\}}_{i=0}^{N+l-1}$ Be former sequence ${\left\{a_i\right\}}_{i=0}^{N-1}$ Q phase difference sequence, can get following corresponding relation by following formula:

If q=0, then difference sequence deteriorates to former sequence; If q=1 then is adjacent difference sequence, can analogize successively.Can obtain matched filter of the present invention by formula (2), its structure is referring to shown in Figure 3.

If list entries be ... x _NX ₀, the coefficient sequence of matched filter is { b _N-q-1, b _N-q-2..., b _i..., b ₁, b ₀.The elementary cell that empty frame 1 is this matched filter among the figure, it mainly is made up of multiplication and add operation unit (MAC) and delay unit.Whole filter by these elementary cell 1 continuous cascades, combine.And another empty frame 2 is differential feedback unit, supposes that it is the q phase difference, and then this unit is made of q delay unit, is used for storing a previous q result.Matched filter of the present invention includes following parts: the latch 31 that list entries is latched; Back at this latch 31 is connected with N+q multiplier 321 by data/address bus, 322 ..., 326, each a input of these multipliers all is to link to each other by the output of bus with this latch 31, and its another input is then sent into a numerical value of above-mentioned particular factor sequence; An input of the adder that the output of above-mentioned each grade multiplier is all corresponding with it links to each other, i.e. the output y of multiplier 321 _N+q-1Link to each other the output y of multiplier 322 with the input of adder 335 _N+q-2Link to each other with the input of adder 334, and the like, until the output y of multiplier 325 ₁Link to each other with the input of adder 331; The output y of last multiplier 326 ₀Directly link to each other with the input of delay unit 341, another input of these adders then links to each other with the output of its upper level delay unit, i.e. the output z of delay unit 341 ₁Link to each other the output z of delay unit 342 with the input of adder 331 ₂Link to each other with the input of adder 332, and the like, until the output z of delay unit 345 _N+q-1Link to each other with the input of adder 335; The output of these adders then links to each other with the input of its next stage delay unit respectively, it is the input that the output of adder 331 is connected to delay unit 342, the output of adder 332 is connected to the input of delay unit 343, and the like, be connected to the input of delay unit 346 until the output of adder 335; The output of the output of the last grade delay unit 346 and a differential feedback unit 2 is connected to adder 336, and the summation gained result of this adder 336 is exactly final correlation; This differential feedback unit 2 is made up of 347 continuous of a plurality of delay units, and the number of a plurality of delay units 347 wherein equates with the number of the leggy of this filter, the input of this differential feedback unit 2 is correlation R (n) of this matched filter output, and its output valve U (n) then is connected to the input of the adder 336 of the last grade.

The sequence that the particular factor that above-mentioned each multiplier is taken advantage of is formed is { b _N-q-1, b _N-q-2..., b _i..., b ₁, b ₀, the algorithm of this sequence is as follows: suppose that multi-phase differential digital match filter wherein is the q phase place, then:

In the formula, coefficient a _iIt is the coefficient of traditional matched filter.

The list entries that the workflow of q phase difference matched filter of the present invention comprises the steps: to establish received signal at least for ... x _NX ₀, the coefficient sequence of this matched filter is { b _N-q-1, b _N-q-2..., b _i..., b ₁, b ₀; the physical significance of this list entries is: the binary bit sequence that the quantification of sampling to received signal obtains; the physical significance of this coefficient sequence is: represent the fixing coefficient taken advantage of in each tap of this matched filter, it typically is the binary sequence of 1 bit; Wherein: the q phase place is represented leggy, and q is an integer; N represents the progression or the tap number of the matched filter of conventional method, and N is an integer;

(1) above-mentioned list entries is under clock signal drives, from x ₀Latch 31 is sent in beginning in regular turn, with guarantee between the quantization bit synchronously;

(2) each signal of list entries behind the process latch 31 is (with x ₀Be example), send into an input of all particular factor multipliers simultaneously by data/address bus, promptly deliver to an input of each multiplier 321,322,323,324,325,326 respectively;

(3) send into each coefficient of the correspondence of this matched filter respectively at another input of above-mentioned each multiplier, i.e. b _N+q-1Send into the left end of multiplier 321, b _N+q-2Send into the left end of multiplier 322, and the like, until b ₀Send into the left end of multiplier 326;

(4), the result of gained is delivered to simultaneously accordingly input, i.e. a y of above-mentioned each adder respectively through the multiplying of above-mentioned each multiplier ₁Send into an input of adder 331, y ₂Deliver to an input of adder 332, and the like, until y _N+q-1Deliver to an input of adder 335;

(5) send into the correlation of depositing in each delay unit respectively at another input of above-mentioned each adder, i.e. the z that exports from delay unit 341 ₁Send into another input of adder 331, from the z of delay unit 342 outputs ₂Deliver to another input of adder 332, and the like, until z from delay unit 345 outputs _N+q-1Deliver to another input of adder 335; And be positioned at the output y of the multiplier 326 of final stage ₀Then directly send into delay unit 341; Above-mentioned each delay unit all is clock cycle of time-delay to be about to signal output;

(6) add operation of above-mentioned each adder of process, the result of gained is sent into the next stage delay unit adjacent with this adder successively, delay unit 342 is sent in the output that is adder 331, delay unit 343 is sent in the output of adder 332, and the like, send into delay unit 346 until the output of adder 335;

(7) the output V (n) that is positioned at top delay unit (346) sends into the adder (336) of its front end, so that output U (n) addition with differential feedback unit, this differential feedback unit is made up of q delay unit, and promptly the output R (n) of this matched filter exports the last output result that just can obtain this matched filter through the output valve U (n) that obtains of q delay unit (347) and V (n) after by adder (336) addition.

This differential configuration can distribute from the distance of swimming of sequence and be explained.Q phase difference is poor corresponding to two elements (value ± 1) of q the position that be separated by in the former sequence, if these two elements equate, is called the equal distance of swimming, otherwise, be called and do not wait the distance of swimming.Their poor value ± 2, ± 1,0}.If distance of swimming characteristic is good, equate that promptly distance of swimming number is many, then can obtain morely 0, can greatly reduce the MAC unit number.

Spreading code commonly used has the synchronous code of m sequence, Gold (Ge De) sign indicating number and particular design among the CDMA.Development personnel of the present invention have carried out statistical analysis to the distance of swimming distribution of these yards, use the multi-phase differential principle, have found the optimum digital matched filter structure of they correspondences.Especially for employed Primary Synchronisation Code in WCDMA (the Wide-band Code Division Multiple Access) system, write the leggy digital matched filter program of this sign indicating number with common hardware descriptive language VHDL, carry out emulation and checking, confirmed the superiority of multi-phase differential principle.

A. example one: the Primary Synchronisation Code multi-phase differential digital match filter in the WCDMA system

Be asynchronous sequential relationship between each base station in the WCDMA system, adopt 18 different rank Gold sign indicating numbers as base station identity code, in order to set up initial synchronisation, 3G agreement (3 fast in the mobile terminal ^RdGeneration Partnership Project; TechnicalSpecification Group Radio Access Network; Spreading and modulation (FDD) (3G TS 25.213V.3.1.1 (1999-12))) synchronous Cell searching algorithm of three steps is proposed.Wherein, the first step will be pursued the search that chip calculates correlation to the Primary Synchronisation Code in the descending synchronous signal channel (Primary Synchronous Code is called for short PSC).In order to shorten search time, the best approach is to use matched filter to carry out correlation reception, and this just requires to design a digital matched filter with 256 taps.

According to standard, the PSC sign indicating number adopts broad sense level Golay (Gray) sign indicating number, and this yard has good autocorrelation performance aperiodic, and its building method is as follows:

u=<u ₁,u ₂,…,u ₁₆>=<1,1,1,1,1,1,-1,-1,1,-1,1,-1,1,-1,-1,1>(4)

C _pac=＜u,u,u,-u,-u,u,-u,-u,u,u,u,-u,u,-u,u,u>(5)

Sequence u is the broad sense hierarchical sequence of code length 16, is 16 Golay (Gray) sequence modulation with u with another code length, obtains the Primary Synchronisation Code of code length N=256.

According to the multi-phase differential principle, each phase distance of swimming distribution of PSC sequence that researcher of the present invention has used computer statistics obtains statistics as shown in table 1.

The q phase difference distance of swimming distribution (q=0..12) of table 1.PSC sequence

????q	?0	?1	?2	?3	?4	?5	?6	?7	?8	?9	?10	?11	?12
														Do not wait distance of swimming number	256	?138	?99	?124	?134	?127	?169	?113	?140	?167	?141	?153	?146
The MAC unit number	255	?137	?98	?123	?133	?126	?168	?112	?139	?166	?140	?152	?145

By table as seen, adopt former sequence, promptly the pairing MAC unit number of q=0 item is 255, and adopts 2 phase difference, only needs 98 MAC unit, saves 62% MAC unit than conventional method.Therefore, the applicant selects the difference sequence of the Primary Synchronisation Code of q=2 to make the tap coefficient of matched filter.

B. example two: the multi-phase differential digital match filter of Gold sign indicating number

For code length N=63, be f preferably to proper polynomial ₁(x)=1+x+x ⁶And f ₂(x)=1+x+x ²+ x ⁵+ x ⁶The Gold sign indicating number, according to heterogeneous differential principle, obtain distance of swimming distribution statistics result as shown in table 2.

The q phase difference distance of swimming distribution (q=0..12) of table 2.Gold sign indicating number

????q	?0	?1	?2	?3	?4	?5	?6	?7	?8	?9	?10	?11	?12
														Do not wait distance of swimming number	63	?33	?42	?27	?37	?46	?39	?42	?52	?45	?46	?49	?45
The MAC unit number	62	?32	?41	?26	?36	?45	?38	?41	?51	?44	?45	?48	?44

By table as seen, adopt former sequence (q=0 item correspondence), need 62 MAC unit, and adopt 3 phase difference, only need 26 MAC unit, save 58% MAC unit than conventional method.Therefore, can select the difference sequence of the Gold sign indicating number of q=3 to make the tap coefficient of matched filter.

For Primary Synchronisation Code (PSC), researcher of the present invention has designed FPGA (Field Programmable Gate Array) chip.Its main design parameter is as follows: because the signal to noise ratio of spread-spectrum signal is very low, received signal adopts 8bit to quantize, to improve the signal detection probability.Correlation adopts 16bit to quantize.Describe the structure of 2 phase difference digital matched filters with VHDL language, the FPGA Express that re-uses Synopsys company carries out comprehensively, uses the emulation of Maxplus II, the wiring of altera corp at last, to chip programming.What the present invention adopted is the FLEX10KE family chip.

Gate leve simulation waveform after Fig. 4 has provided comprehensively, the maximum (also claiming correlation peak) that can calculate correlation according to quantification gradation is 7F00h, minimum value is E040h (all representing with 16 systems).On correct time location, peak value occurred as can be seen from FIG., illustrated that simulation result is entirely true.

Claims (8)

1, a kind of implementation method of multi-phase differential digital match filter, the list entries of establishing received signal for ... x _NX ₀, the coefficient sequence of this matched filter is { b _N-q-1, b _N-q-2..., b _i..., b ₁, b ₀; the physical significance of this list entries is: the binary bit sequence that the quantification of sampling to received signal obtains; the physical significance of this coefficient sequence is: represent the fixing coefficient taken advantage of in each tap of this matched filter, it typically is the binary sequence of 1 bit; Wherein: the q phase place is represented leggy, and q is an integer; N represents the progression or the tap number of the matched filter of conventional method, and N is an integer; It is characterized in that: this implementation method comprises the steps: that at least (1) above-mentioned list entries is under clock signal drives, from x ₀Latch is sent in beginning in regular turn, with guarantee between the quantization bit synchronously;

(2), send into an input of all particular factor multipliers simultaneously by data/address bus through each signal of the list entries behind the latch;

(3) send into each particular factor of this matched filter correspondence respectively at another input of above-mentioned each multiplier, i.e. b _N+q+1Send into the left end of multiplier (321), b _N+q-2Send into the left end of multiplier (322), and the like, until b ₀Send into the left end of multiplier (326);

(4), the result of gained is delivered to simultaneously accordingly input, i.e. a y of above-mentioned each adder respectively through the multiplying of above-mentioned each multiplier ₁Send into an input of adder (331), y ₂Deliver to an input of adder (332), and the like, until y _N+q-1Deliver to an input of adder (335);

(5) send into the correlation of depositing in each delay unit respectively at another input of above-mentioned each adder, i.e. the z that exports from delay unit (341) ₁Send into another input of adder (331), from the z of delay unit (342) output ₂Deliver to another input of adder (332), and the like, until z from delay unit (345) output _N+q-1Deliver to another input of adder (335); And be positioned at the output y of the multiplier (326) of final stage ₀Then directly send into delay unit (341); Above-mentioned each delay unit all is clock cycle of time-delay to be about to signal output;

(6) add operation of above-mentioned each adder of process, the result of gained is sent into the next stage delay unit adjacent with this adder successively, delay unit (342) is sent in the output that is adder (331), delay unit (343) is sent in the output of adder (332), and the like, send into delay unit (346) until the output of adder (335);

(7) the output V (n) that is positioned at top delay unit (346) sends into the adder (336) of its front end, so that output U (n) addition with differential feedback unit, this differential feedback unit is made up of q delay unit, and promptly the output R (n) of this matched filter exports the last output result that just can obtain this matched filter through the output valve U (n) that obtains of q delay unit (347) and V (n) after by adder (336) addition.

2, the implementation method of multi-phase differential digital match filter as claimed in claim 1 is characterized in that: the particular factor sequence { b of matched filter in the said method _N-q-1, b _N-q-2..., b _i..., b ₁, b ₀Obtain according to following formula:

Suppose that multi-phase differential digital match filter wherein is the q phase place, then:

In the formula, coefficient a _iIt is the coefficient of traditional matched filter.

3, the implementation method of multi-phase differential digital match filter as claimed in claim 1, it is characterized in that: the least significant end at matched filter is provided with a differential feedback unit, this differential feedback unit is made up of a plurality of delay unit, and the number of a plurality of delay units wherein equates with the number of the leggy of this filter.

4, the implementation method of multi-phase differential digital match filter as claimed in claim 1 is characterized in that: the method for this phase difference can be applied in the matched filter as the multiple binary sequence of 64 tap Hadamard sequences multi-phase differential digital match filters in the IS95 system, mobile communication, radar, Digital Signal Processing class.

5, a kind of multi-phase differential digital match filter, establishing it has the q phase place, it is characterized in that: include following parts: the latch that list entries is latched; Back at this latch is connected with N+q multiplier by data/address bus, and each in these multipliers all is that an input links to each other with the output of this latch by bus, and another input is then sent into a specific coefficient; An input of the adder that the output of above-mentioned each grade multiplier is all corresponding with it links to each other, another input of these adders then links to each other with the output of its upper level delay unit, and the output of these adders then links to each other with the input of its next stage delay unit respectively in addition; The output of the output of the last grade delay unit and a differential feedback unit is connected to an adder, and the summation gained result of this adder is exactly final correlation; Above-mentioned differential feedback unit is made up of the continuous institute of a plurality of delay units, and the number of a plurality of delay units wherein equates with the number of the leggy of this filter, the input of this differential feedback unit is the correlation of this matched filter output, and its output valve then is connected to the input of the adder of the last grade.

6, multi-phase differential digital match filter as claimed in claim 5 is characterized in that: it is to put in order according to it to take from sequence { b that above-mentioned each multiplier is taken advantage of each specific coefficient _N-q-1, b _N-q-2..., b _i..., b ₁, b ₀Each numerical value, the algorithm of this sequence is as follows:

Suppose that multi-phase differential digital match filter wherein is the q phase place, then:

In the formula, coefficient a _iIt is the coefficient of traditional matched filter.

7, multi-phase differential digital match filter as claimed in claim 5 is characterized in that: above-mentioned particular factor multiplier, adder, delay unit and differential feedback unit can adopt on-site programmable gate array FPGA (Field ProgrammableGate Array) integrated chip to realize it.

8, multi-phase differential digital match filter as claimed in claim 5 is characterized in that: this multi-phase differential digital match filter can adopt application-specific integrated circuit ASIC (Application Specific Integrated Circuit) chip to make.

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