CN101587858B - Semiconductor device interconnected structure and manufacturing method thereof - Google Patents
Semiconductor device interconnected structure and manufacturing method thereof Download PDFInfo
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- CN101587858B CN101587858B CN 200810112506 CN200810112506A CN101587858B CN 101587858 B CN101587858 B CN 101587858B CN 200810112506 CN200810112506 CN 200810112506 CN 200810112506 A CN200810112506 A CN 200810112506A CN 101587858 B CN101587858 B CN 101587858B
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Abstract
The invention relates to a manufacturing method for a semiconductor device interconnected structure. The manufacturing method comprises the steps of providing a semiconductor device interconnected structure matrix provided with interlevel dielectrics, and forming a compound medium layer on the semiconductor device interconnected structure matrix. The compound medium layer comprises a bottom cover layer arranged on the bottom of the compound medium layer, a sandwich layer arranged in a sandwich layer groove, and a top cover layer arranged on the top of the compound medium layer, wherein the sandwich layer groove is arranged in the bottom cover layer. The invention also provides the semiconductor device interconnected structure. The invention adopts the compound medium layer as the top coverlayer, improves the mechanical strength of the whole interconnected structure and ensures that a chip is not easy to break in the use process. The material with higher thermal conduction in the top c over layer can easily and timely dissipate the heat generated in the working process of the chip, ensures that the chip cannot be burned down due to overhigh temperature and ensures the working efficiency and the stability of the chip.
Description
Technical field
The present invention relates to the semiconductor fabrication techniques field, specifically, relate to a kind of semiconductor device interconnected structure and preparation method thereof.
Background technology
A challenge being run into of integrated circuit (IC) design and manufacturing field now is how to reduce signal transmission RC to postpone (Resistive Capacitive delay), to this, a kind of method that prior art has adopted is that aluminum interconnecting is replaced with copper interconnecting line, reduces the lead series resistance; Also having a kind of method is the parasitic capacitance that reduces between the plain conductor, and this can realize by (Porous) low-k (Low k) material or the air-gap (Air Gap) of structure porous in the dielectric layer between plain conductor.
In addition, when integrated circuit was worked, owing to flowing of electric current in the circuit, and lead had certain impedance, so can produce some heats inevitably in the circuit.After the integrated circuit characteristic size entered deep-submicron, it is particularly outstanding that this problem becomes.Because device density continues to increase on the chip, thus for chip structure can efficiently radiates heat requirement more and more higher.
Prior art discloses a kind of structure of making the method for autoregistration nanometer cylindricality air-gap and making thus, especially a kind of method of on substrate 100, making low k, ultralow k and extremely low k multilayer interconnect structure, as shown in Figure 1.Wherein, dielectric 102 is kept apart interconnection line structure 104 in the horizontal, has the nanoscale space 106 that is vertically oriented in the described dielectric 102, and said structure constitutes the semiconductor device interconnected structure matrix jointly.On the semiconductor device interconnected structure matrix, form electromigration barriers layer or diffusion impervious layer 108, cover described semiconductor device interconnected structure matrix.Described dielectric 102, interconnection line structure 104 and electromigration barriers layer or diffusion impervious layer 108 form the complete metal interconnecting layer of one deck.Above-mentioned dielectric 102 is the inter-level dielectric of this metal interconnecting layer, and interconnection line structure 104 is the plain conductor in this metal interconnecting layer, and electromigration barriers layer or diffusion impervious layer 108 are the cap layer of this metal interconnecting layer.
In application number is 200510004583.6 Chinese patent application, can also find more information relevant with technique scheme.
The method of existing making semiconductor device interconnected structure uses general dielectric layer to be formed on the semiconductor device interconnected structure matrix, the inter-level dielectric of the porous in the sealing inter-level dielectric, thereby the air-gap opening that perhaps seals in the inter-level dielectric forms air-gap in inter-level dielectric, though the parasitic capacitance that can reduce like this between the semiconductor device interconnected structure plain conductor postpones to reduce signal transmission RC, but simultaneously owing to existing loose structure or air-gap in the inter-level dielectric, also can reduce the mechanical strength of whole interconnection structure, chip is in use become to rupture easily, lose electric connection between the interconnection structure plain conductor, the circuit cisco unity malfunction; And loose structure or air-gap also can reduce the thermal conductivity of whole interconnection structure usually, the heat that circuit is produced in the course of the work in the chip can not be distributed soon, may cause chip internal to burn, and then have influence on the operating efficiency and the stability of entire chip because temperature is too high.
Summary of the invention
The problem that the present invention solves provides a kind of semiconductor device interconnected structure and preparation method thereof, has improved the mechanical strength of interconnection structure.
For addressing the above problem, the invention provides a kind of manufacture method of semiconductor device interconnected structure, comprising: the matrix of the semiconductor device interconnected structure with inter-level dielectric is provided; On the semiconductor device interconnected structure matrix, form compound medium layer.
Alternatively, the method for described formation compound medium layer comprises: form bottom cap rock and top cover photoresist layer on inter-level dielectric successively; Patterning top cover photoresist layer defines the shape of sandwich of layers groove; With the top cover photoresist layer is mask, and etching bottom cap rock forms the sandwich of layers groove to desired depth; In the sandwich of layers groove, form sandwich of layers; Form surface cover at bottom cap rock and sandwich of layers surface.
Alternatively, the method for described formation compound medium layer comprises: form the bottom cap rock on inter-level dielectric; In the cap rock of bottom, form first sandwich of layers; Form intermediate cap layer at bottom cap rock and first sandwich of layers surface; In intermediate cap layer, form second sandwich of layers; Form surface cover in intermediate cap layer and second sandwich of layers surface.
Alternatively, the method for described formation compound medium layer comprises: form the bottom cap rock on inter-level dielectric; Form sandwich of layers in the cap rock of bottom, described sandwich of layers has stairstepping; Form surface cover at bottom cap rock and sandwich of layers surface.
Alternatively, the method for described formation compound medium layer comprises: form the bottom cap rock on inter-level dielectric; In the cap rock of bottom, form sandwich of layers; Form surface cover at bottom cap rock and sandwich of layers surface; In compound medium layer, form the opening that runs through the compound medium layer upper and lower surface.
Alternatively, having air-gap opening or described inter-level dielectric in the described inter-level dielectric is the advanced low-k materials of porous.
Alternatively, the method for described formation sandwich of layers is a sputtering method.
Alternatively, described sandwich of layers has plane pattern.
Alternatively, described plane pattern comprises the geometric figure of parallel lines, intersecting straight lines or various regular and irregulars.
Alternatively, described plane pattern occupy whole bottom cap rock in the horizontal direction or occupy the bottom cap rock a part.
The present invention also provides a kind of semiconductor device interconnected structure, comprising: be positioned at the semiconductor device interconnected structure matrix with inter-level dielectric on the Semiconductor substrate; Also comprise the compound medium layer that is positioned on the semiconductor device interconnected structure matrix.
Alternatively, described compound medium layer comprises: be positioned at the bottom cap rock of compound medium layer bottom, have the sandwich of layers groove in the cap rock of described bottom; Be arranged in the sandwich of layers of sandwich of layers groove; Be positioned at the surface cover at compound medium layer top.
Alternatively, described compound medium layer comprises: be positioned at the bottom cap rock of compound medium layer bottom, have the first sandwich of layers groove in the cap rock of described bottom; Be arranged in first sandwich of layers of the first sandwich of layers groove; Be positioned at the intermediate cap layer of the bottom cap rock and first sandwich of layers top; Be arranged in the second sandwich of layers groove of intermediate cap layer; Be arranged in second sandwich of layers of the second sandwich of layers groove; Be positioned at the surface cover at compound medium layer top.
Alternatively, described compound medium layer comprises: be positioned at the bottom cap rock of compound medium layer bottom, have the sandwich of layers groove of stairstepping in the cap rock of described bottom; Be arranged in the sandwich of layers of sandwich of layers groove, described sandwich of layers has the inverted steps shape; Be positioned at the surface cover at compound medium layer top.
Alternatively, the method for described formation compound medium layer comprises: be positioned at the bottom cap rock of compound medium layer bottom, have the sandwich of layers groove in the cap rock of described bottom; Be arranged in the sandwich of layers of sandwich of layers groove; Be positioned at the surface cover at compound medium layer top; In compound medium layer, also has the opening that runs through the compound medium layer upper and lower surface.
Alternatively, having air-gap opening or described inter-level dielectric in the described inter-level dielectric is the advanced low-k materials of porous.
Alternatively, described sandwich of layers is a metal.
Alternatively, described sandwich of layers has plane pattern.
Alternatively, described plane pattern comprises the geometric figure of parallel lines, intersecting straight lines or various regular and irregulars.
Alternatively, described plane pattern occupy whole bottom cap rock in the horizontal direction or occupy the bottom cap rock a part.
Compared with prior art; the present invention has the following advantages: use compound medium layer to protect the inter-level dielectric of each layer metal interconnecting layer as cap layer in the process of making semiconductor device interconnected structure; make whole interconnection structure have higher mechanical strength, guarantee that chip in use is not easy fracture.Compound medium layer makes advanced low-k materials that whole interconnection structure can either use porous as inter-level dielectric, also can form air-gap in inter-level dielectric, reduces the parasitic capacitance between the metal interconnecting wires, finally reduces integrated circuit signal transmission RC and postpones.
In addition, adopt the high metal material of mechanical strength as sandwich of layers in the compound medium layer, can increase the mechanical strength of entire semiconductor device interconnection structure further, like this, can form some air-gap openings in advance in the inter-level dielectric, perhaps inter-level dielectric adopts the advanced low-k materials of porous, and is unlikely to the mechanical strength of entire semiconductor device interconnection structure is caused bigger influence.In addition, adopt metal material in the compound medium layer, have high thermal, and then the heat that easily chip is produced in the course of the work distributes in time, make that chip is unlikely to burn because temperature is too high, guarantee the operating efficiency and the stability of entire chip.
Description of drawings
Fig. 1 is a kind of cross-sectional view that comprises the semiconductor interconnect structure of autoregistration nanometer cylindricality air-gap that prior art forms;
Fig. 2 is the method flow schematic diagram of the formation semiconductor device interconnected structure of one embodiment of the present of invention;
Fig. 3 is the method flow schematic diagram of compound medium layer of the formation semiconductor device interconnected structure of one embodiment of the present of invention;
Fig. 4 to Figure 18 is the cross-sectional view of the formation semiconductor device interconnected structure of the first embodiment of the present invention;
Figure 19 to Figure 22 is the cross-sectional view of the cap layer in the formation semiconductor device interconnected structure of other embodiment of the present invention.
Embodiment
The present invention uses compound medium layer to protect the inter-level dielectric of each layer metal interconnecting layer as cap layer in the process of making semiconductor device interconnected structure; make whole interconnection structure have higher mechanical strength, guarantee that chip in use is not easy fracture.Compound medium layer makes advanced low-k materials that whole interconnection structure can either use porous as inter-level dielectric, also can form air-gap in inter-level dielectric, reduces the parasitic capacitance between the metal interconnecting wires, finally reduces integrated circuit signal transmission RC and postpones.
In addition, adopt the high material of mechanical strength can increase the mechanical strength of entire semiconductor device interconnection structure further in the compound medium layer, like this, can form some air-gap openings in advance in the inter-level dielectric, perhaps inter-level dielectric adopts the advanced low-k materials of porous, and is unlikely to the mechanical strength of entire semiconductor device interconnection structure is caused bigger influence.Can also adopt the higher material of thermal conductivity in the compound medium layer, and then the heat that easily chip is produced in the course of the work distributes in time, make that chip is unlikely to burn because temperature is too high, guarantee the operating efficiency and the stability of entire chip.
The invention will be further described below in conjunction with specific embodiments and the drawings, but should not limit protection scope of the present invention with this.
Fig. 2 is the method flow schematic diagram of the formation semiconductor device interconnected structure of one embodiment of the present of invention.As shown in Figure 2, comprising: execution in step S201 provides the matrix of the semiconductor device interconnected structure with inter-level dielectric; Execution in step S202 forms compound medium layer on the semiconductor device interconnected structure matrix.
Fig. 3 is the method flow schematic diagram of compound medium layer of the formation semiconductor device interconnected structure of one embodiment of the present of invention.As shown in Figure 3, comprising: execution in step S301 forms bottom cap rock and top cover photoresist layer successively on inter-level dielectric; Execution in step S302, patterning top cover photoresist layer defines the shape of sandwich of layers groove; Execution in step S303 is a mask with the top cover photoresist layer, and etching bottom cap rock forms the sandwich of layers groove to desired depth; Execution in step S304 forms sandwich of layers in the sandwich of layers groove; Execution in step S305 forms surface cover at bottom cap rock and sandwich of layers surface.
Fig. 4 to Figure 18 is the cross-sectional view of the formation semiconductor device interconnected structure of the first embodiment of the present invention, wherein, Fig. 4 to Figure 10 illustrates the step that forms the air-gap opening in semiconductor device interconnected structure of the first embodiment of the present invention, to form the semiconductor device interconnected structure matrix; Figure 11 to Figure 18 illustrates the step that forms compound medium layer on the semiconductor device interconnected structure matrix of the first embodiment of the present invention, thereby forms the complete metal interconnecting layer of one deck of semiconductor device interconnected structure.
As shown in Figure 4, on Semiconductor substrate 200, form first barrier layer 202, first dielectric layer 204, second barrier layer 206, second dielectric layer 208 and first photoresist layer 210 successively.
As shown in Figure 5, graphical first photoresist layer 210 defines the shape of post groove; Be mask with first photoresist layer 210 then, etching second dielectric layer 208, second barrier layer 206 and first dielectric layer, 204 to first barrier layers 202 stop successively, form post groove 212 and 214.
As shown in Figure 6, remove first photoresist layer 210 after, form the packed layer 216 and second photoresist layer 218 successively on the surface of the post groove 212,214 and second dielectric layer 208, described packed layer 216 fills up post groove 212 and 214.
As shown in Figure 7, graphical second photoresist layer 218 defines the shape of post groove or groove respectively; Be mask with second photoresist layer 218 then,, form post groove 212 ' at the original position etching packed layer 216 of as shown in Figure 5 post groove 212; At the original position etching packed layer 216 of as shown in Figure 5 post groove 214, etching packed layer 216 and second dielectric layer, 208 to second barrier layers 206 stop successively then, form groove 222, and the below of groove 222 is formed with through hole 220, and both form dual-damascene structure.
As shown in Figure 8, remove second photoresist layer 218 and packed layer 216 successively after, form the 3rd barrier layer 224 at crystal column surface.
As shown in Figure 9, in post groove 212, groove 222 and through hole 220, form conductive layer 226, and whole crystal column surface is chemically mechanically polished to exposes the 3rd barrier layer 224 and stop.
As shown in figure 10, form the 3rd photoresist layer 228 on the 3rd barrier layer 224 and conductive layer 226 surfaces; Patterning the 3rd photoresist layer 228 defines the shape of air-gap; With the 3rd photoresist layer 228 is mask, and etching the 3rd barrier layer 224, second dielectric layer 208, second barrier layer 206 and first dielectric layer, 204 to first barrier layers 202 stop successively, forms air-gap opening 230,232 and 234.
So far, the step that forms the air-gap opening in the inter-level dielectric of semiconductor device interconnected structure is all finished, next will form compound medium layer as cap layer above inter-level dielectric, occluded air crack opening forms final needed semiconductor device interconnected structure.
As shown in figure 11, remove the 3rd photoresist layer 228, form bottom cap rock 236 and top cover photoresist layer 238 successively at crystal column surface.
In the present embodiment, the material of described bottom cap rock 236 can be silicon dioxide, silicon nitride, silicon oxynitride or carborundum; The described method that forms bottom cap rock 236 can be CVD (Chemical Vapor Deposition) method, plasma enhanced CVD method or high-density plasma chemical vapor deposition method; The thickness of described bottom cap rock 236 can be 500～5000 dusts; Be used for being enclosed in the air-gap opening 230,232 and 234 that forms in the inter-level dielectric, make it form air- gap 230a, 232a and 234a and provide mechanical support for the cap layer of follow-up formation semiconductor device interconnected structure.
In the present embodiment, the thickness concrete example of described bottom cap rock 236 is as 500 dusts, 1000 dusts, 1500 dusts, 2000 dusts, 2500 dusts, 3000 dusts, 3500 dusts, 4000 dusts, 4500 dusts and 5000 dusts etc., preferred 1000～2500 dusts.
In the present embodiment, in order above the inter-level dielectric of semiconductor device interconnected structure, to form follow-up cap layer with comparalive ease, and be unlikely to because the air-gap opening is excessive, the cap layer material does not have enough adhesive force and is filled in the air-gap in the process of deposit, the material of easy volatilization after also can before forming bottom cap rock 236, in the air-gap opening, filling a kind of being heated in advance, carbon doped oxide pore former material (Carbon-doped oxideporogen material) for example, polymethyl methacrylate (Polymethyl methacrylate, PMMA), silsesquioxane sill (Silsesquioxane (SSQ) based material), diamond-like-carbon (Diamond-like carbon, DLC), hydrogeneous silicates (Hydrogen silsesquioxane, HSQ), inorganic polymer (Inorganic polymer), norcamphane based polyalcohol (Norborene-based polymer), unorganic glass (Inorganic glass) or water soluble resin (Water soluble resin) etc.After forming cap layer, on cap layer, open some apertures then, make the material that originally is filled in the air-gap volatilization of being heated, so also can in the inter-level dielectric of semiconductor device interconnected structure, form needed air-gap.
As shown in figure 12, patterning top cover photoresist layer 238 defines the shape of sandwich of layers groove, is mask with top cover photoresist layer 238 then, and cap rock 236 desired depth to the bottom cap rock 236 in etching bottom forms sandwich of layers groove 240.
In the present embodiment, described lithographic method can be dry etching method or wet etching method; The degree of depth of described sandwich of layers groove 240 can be 250～2500 dusts.
In the present embodiment, the degree of depth concrete example of described sandwich of layers groove 240 is as 250 dusts, 500 dusts, 750 dusts, 1000 dusts, 1250 dusts, 1500 dusts, 1750 dusts, 2000 dusts, 2250 dusts and 2500 dusts etc., preferred 500～1250 dusts.
As shown in figure 13, in sandwich of layers groove 240, form sandwich of layers 242, and polish with the upper surface of chemical mechanical polishing method to bottom cap rock 236 and sandwich of layers 242.
In the present embodiment, the material of described sandwich of layers 242 can be metal; Described sandwich of layers 242 has certain plane pattern in bottom cap rock 236, the geometric figure (as shown in figure 16) that comprises parallel lines (as shown in figure 14), intersecting straight lines (as shown in figure 15) or various regular and irregulars, described plane pattern occupy whole bottom cap rock 236 (as shown in figure 14) in the horizontal direction or occupy the part (as shown in figure 17) of bottom cap rock 236; The method of described formation sandwich of layers 242 can be sputtering method; Described sandwich of layers 242 has mechanical strength and high thermal preferably, be used for strengthening the mechanical strength and the heat-conducting effect of entire semiconductor device interconnection structure, the heat that can with comparalive ease chip be produced in the course of the work distributes in time like this.
As shown in figure 18, form surface cover 244 at bottom cap rock 236 and sandwich of layers 242 surfaces.
In the present embodiment, the material of described surface cover 244 can be silicon dioxide, silicon nitride, silicon oxynitride or carborundum; The method of described formation surface cover 244 can be CVD (Chemical Vapor Deposition) method, plasma enhanced CVD method or high-density plasma chemical vapor deposition method; The thickness of described surface cover 244 can be 500～5000 dusts; Be used for being enclosed in the sandwich of layers 242 in the bottom cap rock 236 of semiconductor device interconnected structure, and provide enough mechanical support for the entire semiconductor device interconnection structure.
In the present embodiment, the thickness concrete example of described surface cover 244 is as 500 dusts, 1000 dusts, 1500 dusts, 2000 dusts, 2500 dusts, 3000 dusts, 3500 dusts, 4000 dusts, 4500 dusts and 5000 dusts etc., preferred 1000～2500 dusts.
In the present embodiment, for example be to cover inter-level dielectric with this compound medium layer that comprises sandwich of layers, air-gap opening in the sealing inter-level dielectric, the method that forms the cap layer of interconnection structure with compound medium layer that is provided among the present invention also can be used for generally not having in the interconnection structure of air-gap at inter-level dielectric, can play mechanical strength that improves the entire semiconductor device interconnection structure and the effect that increases radiating effect equally.
Figure 19 to Figure 22 is the cross-sectional view of the cap layer in the formation semiconductor device interconnected structure of other embodiment of the present invention.Can see that in conjunction with Figure 14 to Figure 17 and Figure 19 to Figure 22 it is diversified using the cap layer in the semiconductor device interconnected structure that method of the present invention forms.The compound medium layer as cap layer that will use as the present invention, its concrete structure is except the structure described in first embodiment, can also be as shown in figure 19, on the substrate 400 of representing interconnection structure interlayer medium, be formed with bottom cap rock 402, in bottom cap rock 402, be embedded with first sandwich of layers 404, upper surface in the bottom cap rock 402 and first sandwich of layers 404 is formed with surface cover 406, in surface cover 406, be embedded with second sandwich of layers 408, the plane contact at the lower surface of described second sandwich of layers 408 and bottom cap rock 402 and first sandwich of layers, 404 places, upper surface in the surface cover 406 and second sandwich of layers 408 is coated with the 3rd cap layer 410 at last, forms the cap layer of final semiconductor device interconnected structure.The cap layer of said structure makes that the mechanical strength of entire semiconductor device interconnection structure is stronger owing to used more dielectric layer and sandwich of layers to form final compound medium layer, and conductivity of heat is better.
In the present invention, described cap layer structure can also be as shown in figure 20, on the substrate 500 of representing interconnection structure interlayer medium, be formed with bottom cap rock 502, in bottom cap rock 502, be embedded with first sandwich of layers 504, upper surface in the bottom cap rock 502 and first sandwich of layers 504 is formed with surface cover 506, in surface cover 506, be embedded with second sandwich of layers 508, the lower surface of described second sandwich of layers 508 does not contact with the plane of bottom cap rock 502 with first sandwich of layers, 504 places, upper surface in the surface cover 506 and second sandwich of layers 508 is coated with the 3rd cap layer 510 at last, forms the cap layer of final semiconductor device interconnected structure.The cap layer intermediate cap layer of said structure is thicker, can further improve the mechanical strength and the conductivity of heat of semiconductor device interconnected structure.
In the present invention, described cap layer structure can also be as shown in figure 21, on the substrate 600 of representing interconnection structure interlayer medium, be formed with bottom cap rock 602, in bottom cap rock 602, be embedded with sandwich of layers 604, and the cross section of described sandwich of layers 604 has the pattern of inverted steps shape, and it can exceed the plane at cap rock 602 places, bottom, and the upper surface in bottom cap rock 602 and sandwich of layers 604 is coated with surface cover 606 at last, forms the cap layer of final semiconductor device interconnected structure.The cap layer sandwich of layers groove of said structure is stairstepping, make sandwich of layers better with the tack of bottom cap rock in forming process, but also can the more sandwich of layers medium of deposit, these factors can improve the mechanical strength and the conductivity of heat of semiconductor device interconnected structure.
In the present invention, described cap layer structure can also be as shown in figure 22, on the substrate 700 of representing interconnection structure interlayer medium, be formed with bottom cap rock 702, be embedded with sandwich of layers 704 in the described bottom cap rock 702, upper surface in bottom cap rock 702 and sandwich of layers 704 is formed with surface cover 706, in this cap layer, form some at last and run through the opening (Perforation) of whole top cover layer upper and lower surface, the material that is used for the easy volatilization that existing another kind is pre-charged with by the heated air crack makes its volatilization of being heated finally form the method for air-gap, and forms final semiconductor device interconnected structure.
Except the above embodiments; before described identical with the present invention as long as form this compound medium layer in the present invention as the thought of the cap layer of semiconductor device interconnected structure; its method and product all fall within the scope of rights protection of the presently claimed invention, should not do too much restriction to this at this.
The present invention uses compound medium layer to protect the inter-level dielectric of each layer metal interconnecting layer as cap layer in the process of making semiconductor device interconnected structure; make whole interconnection structure have higher mechanical strength, guarantee that chip in use is not easy fracture.Compound medium layer makes advanced low-k materials that whole interconnection structure can either use porous as inter-level dielectric, also can form air-gap in inter-level dielectric, reduces the parasitic capacitance between the metal interconnecting wires, finally reduces integrated circuit signal transmission RC and postpones.
In addition, adopt the high material of mechanical strength can increase the mechanical strength of entire semiconductor device interconnection structure further in the compound medium layer, like this, can form some air-gap openings in advance in the inter-level dielectric, perhaps inter-level dielectric adopts the advanced low-k materials of porous, and is unlikely to the mechanical strength of entire semiconductor device interconnection structure is caused bigger influence.Can also adopt the higher material of thermal conductivity in the compound medium layer, and then the heat that easily chip is produced in the course of the work distributes in time, make that chip is unlikely to burn because temperature is too high, guarantee the operating efficiency and the stability of entire chip.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can make possible change and modification, so protection scope of the present invention should be as the criterion with the scope that claim of the present invention was defined.
Claims (48)
1. the manufacture method of a semiconductor device interconnected structure is characterized in that, comprising:
Semiconductor device interconnected structure with inter-level dielectric matrix is provided;
On the semiconductor device interconnected structure matrix, form compound medium layer;
The method of described formation compound medium layer comprises:
On inter-level dielectric, form bottom cap rock and top cover photoresist layer successively;
Patterning top cover photoresist layer defines the shape of sandwich of layers groove;
With the top cover photoresist layer is mask, and etching bottom cap rock forms the sandwich of layers groove to desired depth;
In the sandwich of layers groove, form sandwich of layers;
Form surface cover at bottom cap rock and sandwich of layers surface.
2. the manufacture method of semiconductor device interconnected structure according to claim 1 is characterized in that, having air-gap opening or described inter-level dielectric in the described inter-level dielectric is the advanced low-k materials of porous.
3. the manufacture method of semiconductor device interconnected structure according to claim 1 is characterized in that, the method for described formation sandwich of layers is a sputtering method.
4. the manufacture method of semiconductor device interconnected structure according to claim 1 is characterized in that, described sandwich of layers has plane pattern.
5. the manufacture method of semiconductor device interconnected structure according to claim 4 is characterized in that, described plane pattern comprises the geometric figure of parallel lines, intersecting straight lines or various regular and irregulars.
6. the manufacture method of semiconductor device interconnected structure according to claim 4 is characterized in that, described plane pattern occupies whole bottom cap rock in the horizontal direction or occupies the part of bottom cap rock.
7. the manufacture method of a semiconductor device interconnected structure is characterized in that, comprising:
Semiconductor device interconnected structure with inter-level dielectric matrix is provided;
On the semiconductor device interconnected structure matrix, form compound medium layer;
The method of described formation compound medium layer comprises:
On inter-level dielectric, form the bottom cap rock;
In the cap rock of bottom, form the first sandwich of layers groove;
In the described first sandwich of layers groove, form first sandwich of layers;
Form intermediate cap layer at bottom cap rock and first sandwich of layers surface;
In intermediate cap layer, form the second sandwich of layers groove;
In the described second sandwich of layers groove, form second sandwich of layers;
Form surface cover in intermediate cap layer and second sandwich of layers surface.
8. the manufacture method of semiconductor device interconnected structure according to claim 7 is characterized in that, having air-gap opening or described inter-level dielectric in the described inter-level dielectric is the advanced low-k materials of porous.
9. the manufacture method of semiconductor device interconnected structure according to claim 7 is characterized in that, the method for described formation first sandwich of layers and second sandwich of layers is a sputtering method.
10. the manufacture method of semiconductor device interconnected structure according to claim 7 is characterized in that, described first sandwich of layers and second sandwich of layers have plane pattern.
11. the manufacture method of semiconductor device interconnected structure according to claim 10 is characterized in that, described plane pattern comprises the geometric figure of parallel lines, intersecting straight lines or various regular and irregulars.
12. the manufacture method of semiconductor device interconnected structure according to claim 10 is characterized in that, described plane pattern occupies whole bottom cap rock in the horizontal direction or occupies the part of bottom cap rock.
13. the manufacture method of a semiconductor device interconnected structure is characterized in that, comprising:
Semiconductor device interconnected structure with inter-level dielectric matrix is provided;
On the semiconductor device interconnected structure matrix, form compound medium layer;
The method of described formation compound medium layer comprises:
On inter-level dielectric, form the bottom cap rock;
Form the sandwich of layers groove in the cap rock of bottom, form sandwich of layers in described sandwich of layers groove, described sandwich of layers has the inverted steps shape;
Form surface cover at bottom cap rock and sandwich of layers surface.
14. the manufacture method of semiconductor device interconnected structure according to claim 13 is characterized in that, having air-gap opening or described inter-level dielectric in the described inter-level dielectric is the advanced low-k materials of porous.
15. the manufacture method of semiconductor device interconnected structure according to claim 13 is characterized in that, the method for described formation sandwich of layers is a sputtering method.
16. the manufacture method of semiconductor device interconnected structure according to claim 13 is characterized in that, described sandwich of layers has plane pattern.
17. the manufacture method of semiconductor device interconnected structure according to claim 16 is characterized in that, described plane pattern comprises the geometric figure of parallel lines, intersecting straight lines or various regular and irregulars.
18. the manufacture method of semiconductor device interconnected structure according to claim 16 is characterized in that, described plane pattern occupies whole bottom cap rock in the horizontal direction or occupies the part of bottom cap rock.
19. the manufacture method of a semiconductor device interconnected structure is characterized in that, comprising:
Semiconductor device interconnected structure with inter-level dielectric matrix is provided;
On the semiconductor device interconnected structure matrix, form compound medium layer;
The method of described formation compound medium layer comprises:
On inter-level dielectric, form the bottom cap rock;
In the cap rock of bottom, form the sandwich of layers groove;
In described sandwich of layers groove, form sandwich of layers;
Form surface cover at bottom cap rock and sandwich of layers surface;
In compound medium layer, form the opening that runs through the compound medium layer upper and lower surface.
20. the manufacture method of semiconductor device interconnected structure according to claim 19 is characterized in that, having air-gap opening or described inter-level dielectric in the described inter-level dielectric is the advanced low-k materials of porous.
21. the manufacture method of semiconductor device interconnected structure according to claim 19 is characterized in that, the method for described formation sandwich of layers is a sputtering method.
22. the manufacture method of semiconductor device interconnected structure according to claim 19 is characterized in that, described sandwich of layers has plane pattern.
23. the manufacture method of semiconductor device interconnected structure according to claim 22 is characterized in that, described plane pattern comprises the geometric figure of parallel lines, intersecting straight lines or various regular and irregulars.
24. the manufacture method of semiconductor device interconnected structure according to claim 22 is characterized in that, described plane pattern occupies whole bottom cap rock in the horizontal direction or occupies the part of bottom cap rock.
25. a semiconductor device interconnected structure comprises:
Be positioned at the semiconductor device interconnected structure matrix on the Semiconductor substrate with inter-level dielectric;
It is characterized in that, also comprise the compound medium layer that is positioned on the semiconductor device interconnected structure matrix;
Described compound medium layer comprises:
Be positioned at the bottom cap rock of compound medium layer bottom, have the sandwich of layers groove in the cap rock of described bottom;
Be arranged in the sandwich of layers of sandwich of layers groove;
Be positioned at the surface cover at compound medium layer top.
26. the manufacture method of semiconductor device interconnected structure according to claim 25 is characterized in that, having air-gap opening or described inter-level dielectric in the described inter-level dielectric is the advanced low-k materials of porous.
27. semiconductor device interconnected structure according to claim 25 is characterized in that, described sandwich of layers is a metal.
28. semiconductor device interconnected structure according to claim 25 is characterized in that, described sandwich of layers has plane pattern.
29. semiconductor device interconnected structure according to claim 28 is characterized in that, described plane pattern comprises the geometric figure of parallel lines, intersecting straight lines or various regular and irregulars.
30. semiconductor device interconnected structure according to claim 28 is characterized in that, described plane pattern occupies whole bottom cap rock in the horizontal direction or occupies the part of bottom cap rock.
31. a semiconductor device interconnected structure comprises:
Be positioned at the semiconductor device interconnected structure matrix on the Semiconductor substrate with inter-level dielectric;
It is characterized in that, also comprise the compound medium layer that is positioned on the semiconductor device interconnected structure matrix; Described compound medium layer comprises:
Be positioned at the bottom cap rock of compound medium layer bottom, have the first sandwich of layers groove in the cap rock of described bottom;
Be arranged in first sandwich of layers of the first sandwich of layers groove;
Be positioned at the intermediate cap layer of the bottom cap rock and first sandwich of layers top;
Be arranged in the second sandwich of layers groove of intermediate cap layer;
Be arranged in second sandwich of layers of the second sandwich of layers groove;
Be positioned at the surface cover at compound medium layer top.
32. the manufacture method of semiconductor device interconnected structure according to claim 31 is characterized in that, having air-gap opening or described inter-level dielectric in the described inter-level dielectric is the advanced low-k materials of porous.
33. semiconductor device interconnected structure according to claim 31 is characterized in that, described first sandwich of layers and second sandwich of layers are metal.
34. semiconductor device interconnected structure according to claim 31 is characterized in that, described first sandwich of layers and second sandwich of layers have plane pattern.
35. semiconductor device interconnected structure according to claim 34 is characterized in that, described plane pattern comprises the geometric figure of parallel lines, intersecting straight lines or various regular and irregulars.
36. semiconductor device interconnected structure according to claim 34 is characterized in that, described plane pattern occupies whole bottom cap rock in the horizontal direction or occupies the part of bottom cap rock.
37. a semiconductor device interconnected structure comprises:
Be positioned at the semiconductor device interconnected structure matrix on the Semiconductor substrate with inter-level dielectric;
It is characterized in that, also comprise the compound medium layer that is positioned on the semiconductor device interconnected structure matrix; Described compound medium layer comprises:
Be positioned at the bottom cap rock of compound medium layer bottom, have the sandwich of layers groove of stairstepping in the cap rock of described bottom;
Be arranged in the sandwich of layers of sandwich of layers groove, described sandwich of layers has the inverted steps shape;
Be positioned at the surface cover at compound medium layer top.
38. the manufacture method according to the described semiconductor device interconnected structure of claim 37 is characterized in that, having air-gap opening or described inter-level dielectric in the described inter-level dielectric is the advanced low-k materials of porous.
39., it is characterized in that described sandwich of layers is a metal according to the described semiconductor device interconnected structure of claim 37.
40., it is characterized in that described sandwich of layers has plane pattern according to the described semiconductor device interconnected structure of claim 37.
41., it is characterized in that described plane pattern comprises the geometric figure of parallel lines, intersecting straight lines or various regular and irregulars according to the described semiconductor device interconnected structure of claim 40.
42., it is characterized in that described plane pattern occupies whole bottom cap rock in the horizontal direction or occupies the part of bottom cap rock according to the described semiconductor device interconnected structure of claim 40.
43. a semiconductor device interconnected structure comprises:
Be positioned at the semiconductor device interconnected structure matrix on the Semiconductor substrate with inter-level dielectric;
It is characterized in that, also comprise the compound medium layer that is positioned on the semiconductor device interconnected structure matrix; Described compound medium layer comprises:
Be positioned at the bottom cap rock of compound medium layer bottom, have the sandwich of layers groove in the cap rock of described bottom;
Be arranged in the sandwich of layers of sandwich of layers groove;
Be positioned at the surface cover at compound medium layer top;
In compound medium layer, also has the opening that runs through the compound medium layer upper and lower surface.
44., it is characterized in that having air-gap opening or described inter-level dielectric in the described inter-level dielectric is the advanced low-k materials of porous according to the described semiconductor device interconnected structure of claim 43.
45., it is characterized in that described sandwich of layers is a metal according to the described semiconductor device interconnected structure of claim 43.
46., it is characterized in that described sandwich of layers has plane pattern according to the described semiconductor device interconnected structure of claim 43.
47. the semiconductor device interconnected structure according to claim 46 is stated is characterized in that, described plane pattern comprises the geometric figure of parallel lines, intersecting straight lines or various regular and irregulars.
48., it is characterized in that described plane pattern occupies whole bottom cap rock in the horizontal direction or occupies the part of bottom cap rock according to the described semiconductor device interconnected structure of claim 46.
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| CN102487057B (en) * | 2010-12-03 | 2014-03-12 | 中芯国际集成电路制造(北京)有限公司 | Metal front dielectric layer and preparation method thereof |
| CN103165517B (en) * | 2011-12-08 | 2015-04-15 | 中芯国际集成电路制造(上海)有限公司 | Method for reducing interlayer dielectric layer dielectric constant |
| CN103165523B (en) * | 2011-12-19 | 2015-08-05 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of interconnection structure |
| US9161461B2 (en) * | 2012-06-14 | 2015-10-13 | Zhuhai Advanced Chip Carriers & Electronic Substrate Solutions Technologies Co. Ltd. | Multilayer electronic structure with stepped holes |
| CN106548977B (en) * | 2016-10-26 | 2020-06-09 | 上海集成电路研发中心有限公司 | Manufacturing method of air gap structure |
| CN116564852A (en) * | 2023-05-05 | 2023-08-08 | 纳宇半导体材料(宁波)有限责任公司 | Jig for sintering interconnection and patch between semiconductor devices and method for interconnection and patch |
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| CN101009266A (en) * | 2006-01-27 | 2007-08-01 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its forming method |
| CN101071789A (en) * | 2006-05-08 | 2007-11-14 | 国际商业机器公司 | Multilayer interconnect structure containing air gaps and method for making |
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| CN101009266A (en) * | 2006-01-27 | 2007-08-01 | 台湾积体电路制造股份有限公司 | Semiconductor structure and its forming method |
| CN101071789A (en) * | 2006-05-08 | 2007-11-14 | 国际商业机器公司 | Multilayer interconnect structure containing air gaps and method for making |
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