CN101577268A - Package structure for stacked type integrated circuit chip - Google Patents
Package structure for stacked type integrated circuit chip Download PDFInfo
- Publication number
- CN101577268A CN101577268A CN 200810099204 CN200810099204A CN101577268A CN 101577268 A CN101577268 A CN 101577268A CN 200810099204 CN200810099204 CN 200810099204 CN 200810099204 A CN200810099204 A CN 200810099204A CN 101577268 A CN101577268 A CN 101577268A
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- conductive
- encapsulating structure
- integrated circuit
- layer
- intermediary layer
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- 229910000679 solder Inorganic materials 0.000 claims description 27
- 239000002313 adhesive film Substances 0.000 claims description 8
- 238000003466 welding Methods 0.000 description 32
- 238000010586 diagram Methods 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000003491 array Methods 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 239000002699 waste material Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- Wire Bonding (AREA)
Abstract
The invention provides a package structure for a stacked type integrated circuit chip, comprising integrated circuit chips, a first medium layer, a circuit board and a second pattern conducting layer. The circuit board covers the integrated circuit chips and partially covers the first medium layer at least. A second medium layer is arranged between the two integrated circuit chips. The first medium layer is provided with a first surface and a second surface and is internally provided with a plurality of conducting channels (via) for providing a plurality of conducting paths between the first surface and the second surface. The first medium layer and the second medium layer respectively provide the conducting paths among the circuit board, the second pattern conducting layer and the stacked type integrated circuit chip.
Description
Technical field
The invention relates to a kind of encapsulating structure that is used for stacked type integrated circuit chip; Particularly about using the encapsulating structure of an intermediary layer as the stacked type integrated circuit chip of a conductive path.
Background technology
Along with the progress of semiconductor technology, various encapsulation technologies have been widely used in the various electronic products.Wherein, the encapsulating structure of stacked integrated circuit chip has many advantages, and is low such as: processing procedure difficulty, not increasing under the board area condition, can insert more highdensity integrated circuit (IC) chip.So when electronic product need be saved circuit board and takes up space, the stacked integrated circuit chip just became indispensable element.
Prior art has proposed to realize the encapsulation architecture of stacked integrated circuit chip, United States Patent (USP) notification number the 6th, 262, promptly disclose can the destroy or force to yield packaging system of the stacked integrated circuit chip that circuit board coats of a kind of utilization for No. 895, now extract wherein a plurality of accompanying drawings, see also Fig. 1 to Fig. 4, its Central Plains component symbol has renumberd so that explanation.
Fig. 1 illustration one circuit board 101 of can destroying or force to yield, this circuit board 101 of can destroying or force to yield comprises a upper surface 102.But have one first conductive welding pad array 104 at this upper surface 102, it comprises one first assembly welding pad 105.A lower surface 103 of this circuit board 101 of can destroying or force to yield of Fig. 2 illustration, but but but it comprises one second conductive welding pad array 106, one the 3rd conductive welding pad array 107 and one the 4th conductive welding pad array 108.But but the 3rd, the 4th conductive welding pad array 107,108 lays respectively at the side of the second conductive welding pad array 106.But this second conductive welding pad array 106 comprises one second assembly welding pad 109, but the 3rd conductive welding pad array 107 comprises one the 3rd assembly welding pad 110, but the 4th conductive welding pad array 108 comprises one the 4th assembly welding pad 111.
From the above, a conductor wire 112 links this second assembly welding pad 109, the 3rd assembly welding pad 110 and the 4th assembly welding pad 111, and defines a pattern conductive structure.This first assembly welding pad 105 has an identical weld pad figure with this second assembly welding pad 109.
Fig. 1 is illustration one chip 113 more, has a upper surface 114 and a lower surface 115.Lower surface 115 please refer to Fig. 3 than detailed structure, this lower surface 115 has a plurality of semicircle contact soldered balls 116.When this circuit board 101 of can destroying or force to yield coats this packaged chip, one right-angled intersection circle 117 when linking with this conductor wire 112, the second assembly welding pad 109 is arranged, it has a crack 118, these semicircle contact soldered ball 116 suitable implantable these cracks 118 overlap to have an identical weld pad figure with this first assembly welding pad 105 with this second assembly welding pad 109.
Chip 113 is the upper face center positions that place the circuit board 101 of can destroying or force to yield, but but folding back the 3rd, the 4th conductive welding pad array 107,108 is suitable can form one the 5th conductive welding pad array 119, as shown in Figure 4.
Structure shown in Figure 4 can be piled up in regular turn, is the encapsulation module 120 of illustration tool three stacked integrated circuit chips among the figure.
As a rule, this stacking method need comprise soldered ball, makes this stacked integrated circuit chip have thicker thickness, and soldered ball causes the crack easily at the contact place simultaneously, causes the heavy industry cost to increase.
In view of this, providing a kind of encapsulating structure that does not have the stacked integrated circuit chip of soldered ball, make the integral thickness reduction after the stacked package, and reduce the heavy industry cost, is an industry problem demanding prompt solution for this reason.
Summary of the invention
The object of the present invention is to provide a kind of encapsulating structure that is used for stacked type integrated circuit chip, and adopt an intermediary layer and flexible base plate between encapsulating structure and the encapsulating structure, so that a conductive path to be provided, must not re-use soldered ball whereby, increase the stacked integrated circuit chip density and need not to use the purpose of soldered ball to reach as conductive path, make the integral thickness reduction after the stacked package, and reduce the heavy industry cost.
Another object of the present invention is to provide a kind of encapsulating structure that is used for stacked type integrated circuit chip, directly a tube core that is not encapsulated as an integrated circuit (IC) chip is as yet engaged with an intermediary layer, do not comprise circuit board and solder ball pad, significantly reducing the thickness of encapsulating structure, and more simplify manufacturing process.
For reaching above-mentioned purpose, the present invention discloses a kind of encapsulating structure that is used for stacked type integrated circuit chip, comprises: an integrated circuit (IC) chip, one first intermediary layer, a circuit board.This circuit board comprises a flexible base plate, one first patterned conductive layer and one second patterned conductive layer.This integrated circuit (IC) chip comprises a tube core (die) and a plurality of solder ball pad (ball pad), is located on the surface of this tube core.This first intermediary layer is covered on the surface and these a plurality of solder ball pads of this tube core.This circuit board coats this integrated circuit (IC) chip, and at least partly covers this first intermediary layer.This flexible base plate has a first surface and a second surface, and have a plurality of conductive channels (via) in it, be communicated with this first surface and second surface, this first patterned conductive layer is formed at this second surface, see through this first intermediary layer, be electric connection with these a plurality of solder ball pads.This second patterned conductive layer is formed at this first surface, is electric connection by these a plurality of conductive channels and this first patterned conductive layer.
The present invention also discloses a kind of encapsulating structure that is used for stacked type integrated circuit chip, comprises: a tube core and an intermediary layer.This tube core has a first surface and a second surface, and comprises a plurality of weld pads (pad), is located on this second surface.This first surface has a plurality of conductive connection parts, is electrical connected with these weld pads respectively.This intermediary layer is located at the second surface of this tube core and is covered on these a plurality of weld pads and has a first surface and a second surface, and have a plurality of conductive channels (via) in it, with between this first surface and this second surface of this intermediary layer, provide a plurality of conductive paths.
Description of drawings
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, below in conjunction with accompanying drawing the specific embodiment of the present invention is elaborated, wherein:
Fig. 1 is the existing packaged chip and the circuit board upper surface schematic diagram of can destroying or force to yield;
Fig. 2 is the existing circuit board lower surface schematic diagram of can destroying or force to yield;
Fig. 3 is existing semicircle contact soldered ball and right-angled intersection circle crack schematic diagram;
Fig. 4 is existing stacked package module schematic diagram; And
Fig. 5 A to Fig. 5 D is the encapsulating structure processing flow schematic diagram that is used for stacked type integrated circuit chip of the present invention;
Fig. 6 is the generalized section of a conductive adhesive film; And
Fig. 7 is the encapsulating structure schematic diagram that another kind of the present invention is used for stacked type integrated circuit chip.
The main element symbol description:
101 circuit board 102 upper surfaces of can destroying or force to yield
But 103 lower surfaces, 104 first conductive welding pad arrays
But 105 first assembly welding pads, 106 second conductive welding pad arrays
But but 107 the 3rd conductive welding pad arrays 108 the 4th conductive welding pad array
109 second assembly welding pads 110 the 3rd assembly welding pad
111 the 4th assembly welding pads, 112 conductor wires
113 chips, 114 upper surfaces
115 lower surfaces, 116 semicircle contact soldered balls
117 right-angled intersections circle, 118 cracks
But 119 the 5th conductive welding pad arrays, 120 stacked package modules
201 integrated circuit (IC) chip, 202 tube cores
203 weld pads, 204 first intermediary layers
205 circuit boards, 206 flexible base plates
207 first surfaces, 208 second surfaces
209 second intermediary layers, 210 substrates
211 stacked integrated circuit chips, 212 conductive channels
213 soft dielectric layer, 301 tube cores
302 intermediary layers, 303 first surfaces
304 second surfaces, 305 weld pads
Embodiment
Below will explain content of the present invention by embodiment, it is the encapsulating structure that is used for stacked type integrated circuit chip about a kind of, by comprising an intermediary layer structure, conductive path between one integrated circuit (IC) chip and a circuit board is provided, and the conductive path between a plurality of integrated circuit (IC) chip, increase the stacked integrated circuit chip density and need not to use the purpose of soldered ball to reach as conductive path.Yet embodiments of the invention are not to need can implement as the described any particular environment of embodiment, application or particular form in order to restriction the present invention.Explanation about embodiment only is explaination purpose of the present invention, but not in order to restriction the present invention.It should be noted that, in following examples and the accompanying drawing, omit and do not illustrate with the non-directly related element of the present invention; And for the purpose of asking easy understanding, each interelement size relationship is to show with exaggerative slightly ratio.
Fig. 5 A to Fig. 5 D is for being used for the encapsulating structure processing flow schematic diagram of stacked type integrated circuit chip.Fig. 5 A illustrates an integrated circuit (IC) chip 201, has a circuit board 205 on it.Circuit board 205 is the circuit boards of can destroying or force to yield, and has a flexible base plate 206, one first patterned conductive layer and one second patterned conductive layer.Flexible base plate 206 has a first surface 207 and a second surface 208, and has a plurality of conductive channels (via) in it, is communicated with this first surface 207 and second surface 208.First patterned conductive layer promptly is formed at second surface 208, second patterned conductive layer promptly is formed at first surface 207, be electric connection by these a plurality of conductive channels and this first patterned conductive layer, whereby, first patterned conductive layer and this second patterned conductive layer form a plurality of conductive paths.201 of integrated circuit (IC) chip comprise a tube core (die) 202 and a plurality of solder ball pad (ball pad) 203, be located on the surface of this integrated circuit (IC) chip 201, be electrically connect with the circuit of these tube core 202 inside, meaning is that these solder ball pad 203 suitable circuit of these tube core 202 inside that can make see through these solder ball pads 203 and are electrically connect with the external world.
Fig. 5 B illustrates the surface that one first intermediary layer 204 is covered in integrated circuit (IC) chip 201, and meaning promptly is covered on tube core 202 and these solder ball pads 203.First intermediary layer 204 has a first surface and a second surface, and have a plurality of conductive channels (via) in it, with between this first surface and this second surface, a plurality of conductive paths are provided, because these conductive channels are very fine and closely woven, so each solder ball pad 203 all is electric connection with many conductive paths, electric current can be passed through smoothly, and reduce the equiva lent impedance of each solder ball pad 203.In the present embodiment, first intermediary layer 204 be a conductive adhesive film (Electrically Conductive Film, ECF), Fig. 6 illustrates the generalized section of conductive adhesive film, it comprises a plurality of conductive channels 212 and a soft dielectric layer 213, and this soft dielectric layer 213 has viscosity.But first intermediary layer 204 is the patterns on heavy industry formula ground (reworkably) in this embodiment, connects this a plurality of solder ball pads 203, when needing heavy industry with box lunch, adheres to again behind removable first intermediary layer 204 again.In other embodiments, the pattern that first intermediary layer 204 can also solidifies (curing) is solidified in the heating back and to be connected these solder ball pads 203.
Encapsulating structure schematic diagram after Fig. 5 C illustrates circuit board and destroys or force to yield.After circuit board 205 is destroyed or force to yield as can be known among the figure, can coat integrated circuit (IC) chip 201, and cover first intermediary layer 204 to small part.Whereby, first patterned conductive layer of circuit board 205 sees through first intermediary layer 204, be electric connection with these solder ball pads 203, simultaneously as aforementioned ground, first patterned conductive layer and second patterned conductive layer are to be electric connection, are electric connection so the internal circuit of tube core 202 promptly sees through second patterned conductive layer of the first surface 207 of these solder ball pads 203 and circuit board 205.One second intermediary layer 209 is covered on the first surface 207 of this flexible base plate 206 that is formed with this second patterned conductive layer, is electrically connect with second patterned conductive layer.In the present embodiment, the material of second intermediary layer 209 is identical with first intermediary layer 204, is all ECF, and second intermediary layer 209 is back to these solder ball pads 203 simultaneously.What need pay special attention to is, purpose with second intermediary layer 209 provides conductive path and gives first surface 207, make its can be when piling up and other elements or circuit be electrically connect, so in other embodiments, the material of second intermediary layer 209 can be different with first intermediary layer 204.
So far, an encapsulating structure that is used for stacked type integrated circuit chip is finished.By first intermediary layer, 204 electrically connect solder ball pads 203 and circuit board 205, solder ball pad 203 be need not by more forming soldered ball, just can be electrically connect with circuit board 205, reduced the height of encapsulating structure significantly, avoiding soldered ball to melt the yield that causes overflow because of being heated when engaging process descends, therefore manufacturing process also can be simplified simultaneously, and reduces the cost of heavy industry or discarded bad encapsulating structure.What is more, more smooth for making the signal transmission, circuit board 205 can be designed to have an impedance matching.For example, by this first patterned conductive layer that is electric connection and the formed a plurality of conductive paths of this second patterned conductive layer, respectively this conductive path has an identical conductive lengths, to form impedance for matching.In this embodiment, the numerical value of this impedance matching is to be selected from the group that 50 ohms impedance match, 75 ohms impedance match, 28 ohms impedance match and combination thereof form, but not as limit, in other embodiments also can be according to the arrange in pairs or groups impedance matching of other ohmages of circuit requirements, to reach the purpose of circuit impedance coupling.Understand the technical staff of designing impedance matching, can understand the technology that how to realize impedance matching, this no longer explaining more.
Please continue 5D with reference to figure, it illustrates the stacked structure of a plurality of encapsulating structures, form stacked integrated circuit chip 211 on a substrate 210, wherein substrate 210 can be printed circuit board (PCB), flexible circuit board or semiconductor substrate or the like, being electrically connect with stacked integrated circuit chip 211, so substrate 210 is not in order to limit the scope of the invention.
Be appreciated that by Fig. 5 D second intermediary layer 209 also can face these solder ball pads 203, meaning is positioned on first substrate surface of solder ball pad 203 belows after promptly being formed at and destroying or force to yield, and the conductive path between two encapsulating structures in fact also can be provided.
Another embodiment of the present invention is to disclose the another kind of encapsulating structure that is used for stacked type integrated circuit chip, sees also Fig. 7.Be that with the main difference part of previous embodiment encapsulating structure shown in Figure 7 is directly a tube core that is not encapsulated as an integrated circuit (IC) chip as yet to be engaged with an intermediary layer, do not comprise circuit board and solder ball pad, significantly reducing the thickness of encapsulating structure, and more simplify manufacturing process.
From the above, encapsulating structure shown in Figure 7 comprises a tube core 301 and an intermediary layer 302.This tube core has a first surface 303 and a second surface 304, and comprises a plurality of weld pads (pad) 305, is located on the second surface 304, and first surface 303 has a plurality of conductive connection parts, is electrical connected with these weld pads 305 respectively.Intermediary layer 302 is located at the second surface 304 of tube core 301 and is covered on these weld pads 305.Whereby, intermediary layer 302 can be electrically connect with these conductive connection parts of these weld pads 305 and first surface 303.What need pay special attention to is because intermediary layer 302 is directly to engage with weld pad 305, need not see through solder ball pad, so can significantly reduce the thickness of encapsulating structure.
Encapsulating structure by aforementioned announcement, do not have use soldered ball (solder ball) joint and use the conductive layer of intermediary layer instead at chip as encapsulating structure, reduced the height of encapsulating structure significantly, avoid soldered ball to melt the yield decline that causes overflow during in engaging process because of being heated at contact position fracture and soldered ball, therefore manufacturing process also can be simplified simultaneously, and reduces the cost of heavy industry or discarded bad encapsulating structure.Intermediary layer can repeat to process recast can avoid waste of material and save manufacturing cost simultaneously.
The above embodiments only are used for exemplifying enforcement aspect of the present invention, and explain technical characterictic of the present invention, are not to be used for limiting protection category of the present invention.Any be familiar with this operator can unlabored change or the arrangement of the isotropism scope that all belongs to the present invention and advocated, the scope of the present invention should be as the criterion with claims.
Claims (10)
1. encapsulating structure that is used for stacked type integrated circuit chip comprises:
One integrated circuit (IC) chip comprises a tube core and a plurality of solder ball pad, is located on the surface of this tube core;
One first intermediary layer is covered on the surface and these a plurality of solder ball pads of this tube core; And
One circuit board coats this integrated circuit (IC) chip, and at least partly covers this first intermediary layer, and wherein, this circuit board comprises:
One flexible base plate has a first surface and a second surface, and has a plurality of conductive channels in it, is communicated with this first surface and second surface;
One first patterned conductive layer is formed at this second surface, sees through this first intermediary layer, is electric connection with these a plurality of solder ball pads; And
One second patterned conductive layer is formed at this first surface, is electric connection by these a plurality of conductive channels and this first patterned conductive layer.
2. encapsulating structure as claimed in claim 1 is characterized in that, this first intermediary layer has a first surface and a second surface, and has a plurality of conductive channels in it, with between this first surface and this second surface, provides a plurality of conductive paths.
3. encapsulating structure as claimed in claim 1 is characterized in that, this first intermediary layer is a conductive adhesive film.
4. encapsulating structure as claimed in claim 3 is characterized in that, this conductive adhesive film is the pattern of solidifying with, connects this a plurality of solder ball pads.
5. encapsulating structure as claimed in claim 3 is characterized in that, but this conductive adhesive film heavy industry formula ground connects these a plurality of solder ball pads.
6. encapsulating structure as claimed in claim 1 is characterized in that, also comprises one second intermediary layer, is covered on the first surface of this flexible base plate that is formed with this second patterned conductive layer.
7. encapsulating structure as claimed in claim 1 is characterized in that, this circuit board is to be designed to have an impedance matching, and this impedance matching is to be selected from following group: 50 ohms impedance match, 75 ohms impedance match, 28 ohms impedance match and combination thereof.
8. encapsulating structure as claimed in claim 7 is characterized in that, this first patterned conductive layer and this second patterned conductive layer that are electric connection form a plurality of conductive paths, and respectively this conductive path has an identical conductive lengths.
9. encapsulating structure that is used for stacked type integrated circuit chip comprises:
One tube core has a first surface and a second surface, and comprises a plurality of weld pads, is located on this second surface, and this first surface has a plurality of conductive connection parts, is electrical connected with these weld pads respectively; And
One intermediary layer is located at the second surface of this tube core and is covered on these a plurality of weld pads;
Wherein this intermediary layer has a first surface and a second surface, and has a plurality of conductive channels in it, with between this first surface and this second surface of this intermediary layer, provides a plurality of conductive paths.
10. encapsulating structure as claimed in claim 9 is characterized in that, this intermediary layer is a conductive adhesive film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810099204 CN101577268A (en) | 2008-05-08 | 2008-05-08 | Package structure for stacked type integrated circuit chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810099204 CN101577268A (en) | 2008-05-08 | 2008-05-08 | Package structure for stacked type integrated circuit chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101577268A true CN101577268A (en) | 2009-11-11 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810099204 Pending CN101577268A (en) | 2008-05-08 | 2008-05-08 | Package structure for stacked type integrated circuit chip |
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| Country | Link |
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| CN (1) | CN101577268A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738129A (en) * | 2011-03-31 | 2012-10-17 | 台湾积体电路制造股份有限公司 | Apparatus and method for increasing bandwidths of stacked dies |
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2008
- 2008-05-08 CN CN 200810099204 patent/CN101577268A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102738129A (en) * | 2011-03-31 | 2012-10-17 | 台湾积体电路制造股份有限公司 | Apparatus and method for increasing bandwidths of stacked dies |
| CN102738129B (en) * | 2011-03-31 | 2014-12-03 | 台湾积体电路制造股份有限公司 | Apparatus and method for increasing bandwidths of stacked dies |
| US8952548B2 (en) | 2011-03-31 | 2015-02-10 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method for increasing bandwidths of stacked dies |
| US9177892B2 (en) | 2011-03-31 | 2015-11-03 | Taiwan Semiconductor Manufacturing Company, Ltd. | Apparatus and method for increasing bandwidths of stacked dies |
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Open date: 20091111 |