CN101552610A - Backward direction value conversion module of data conversion system and realization method thereof - Google Patents

Abstract

The invention relates to a backward direction value conversion module of data conversion system and the realization method, that is, converting RNS into bit data stream. The method comprises: inputting the data of remainder numeral system into a three-way backward counter for evaluating remainder outputting into an all-zero comparator which controls the output of gate; the all-zero comparator monitors the output of the three-way backward counter, when the output result of any way is zero while the output result of at least one way is not zero, the remainder evaluating counter value of the zero result way adds the module value of the way and continue to the synchronous remainder evaluating operation. when adopting the operation of this mode, the remainder evaluating operation of the ways stops until the output results of all the ways are zero. The conversion module provides a data output interface for the application of RNS system in DSP system. and the application of the invention reduces memory occupation space, increases data processing speed, and develops data processing width.

Description

Data conversion system back to numerical value modular converter and implementation method

Technical field

The present invention relates to data conversion technique, particularly a kind of data conversion system is back to numerical value modular converter and implementation method.

Background technology

In recent years, Digital Signal Processing is in data-handling capacity, real-time, and speed, power consumption, the requirement of aspects such as cost is more and more high, therefore, the performance of DSP is also had higher requirement.Utilize RNS (remainder number system) to be converted to seldom integer system of separate numerical digit by the integer that numerical digit is very big, with the mathematical operation unit that utilizes RNS to make up, compare with the mathematical operation unit of binary form, not only reduced the data bit that needs processing, and can carry out parallel processing, characteristics such as no-carry processing have improved speed greatly.And, also can easily rebuild and the corresponding to integer of original date from the RNS result who obtains.Therefore, the data operation processing unit that makes up with RNS has substituted binary implementation in the design of some Programmable DSPs.And obtained to reduce cost and the characteristic of power consumption, simultaneously, also improved the frequency of streamline.The starting point of this application is to adopt parallel numerical representation method system to replace traditional numerical representation method system, calculates and handle parallel carrying out, and gets involved speed, power consumption and area for cutting that front-end algorithm solves VLSI.For designing at aspects such as high speed, low complex degree, low-power consumption, data channel found balance point preferably.It is imperative that the DSP of employing RNS system meets the tendency, and middle conversion realization must be indispensable.

Summary of the invention

The present invention be directed to the problem that now performance of DSP is had higher requirement, the back to numerical value modular converter and implementation method of a kind of data transaction (Delta-Sigma) system proposed, this module and implementation method have not only reduced taking up room of memory, improve the speed of data processing, and expanded the width of data processing.The back is applied in the Programmable DSPs system design to the numerical value modular converter, the interface of a data output is provided for data handling system.

Technical scheme of the present invention is: a kind of data conversion system back to the numerical value modular converter, comprise triple channel subtract counter, full zero comparator and gate, and the triple channel subtract counter comprises mould (2 ⁿ+ 1) counter of modulo operation, to mould 2 ⁿThe counter of modulo operation and to mould (2 ⁿ-1) counter of modulo operation, remainder number system data input triple channel subtract counter carries out complementation, outputs to full zero comparator then, and gate is according to the state of full zero comparator, carry-out bit data flow.

The back of a kind of data conversion system comprises the back to the numerical value modular converter of data conversion system to numerical value conversion implementation method, and implementation method may further comprise the steps:

1) based on (2 ⁿ-1) 2 ⁿ(2 ⁿ+ 1) module, one group of given remainder number system data R ₁, R ₂, R ₃, with R ₁, R ₂, R ₃Import respectively the triple channel subtract counter to mould (2 ⁿ-1) counter of modulo operation, to mould 2 ⁿThe counter of modulo operation and to mould (2 ⁿ+ 1) counter of modulo operation, upper edge at synchronised clock, after described three counters are carried out synchronously respectively and are subtracted 1 operation, entering multidiameter option switch carries out and zero comparison, as this moment three-channel count value be not zero entirely, gate carry-out bit data flow " 1 " is carried out synchronously once more at three counters of next clock and to be subtracted 1 operation;

2) reduce to zero and other counters when not counting 0 when any one counter, then this counter reloads the mould value of this passage in the upper edge of next clock, and continue to participate in subtracting 1 and operate, relatively experiencing n clock again up to all three counters, after having carried out subtracting for n time 1 operation, its result is zero, and gate replaces carry-out bit data flow " 1 " and " 0 ", i.e. system's balance of keeping data with high level and the low level of a clock cycle of a clock cycle;

3) alternately output to the appointment figure place, upgrade next group remainder number system data, get back to step 1) and realize that remainder number system is to the bit data stream conversion.

Beneficial effect of the present invention is: data conversion system of the present invention back to numerical value modular converter and implementation method, meeting the tendency in dsp system for the RNS system provides the interface of a data output, the utilization of this invention has reduced taking up room of memory, improve the speed of data processing, and expanded the width of data processing.

Description of drawings

Fig. 1 is for the present invention is based on the data communication system schematic diagram of Direct Digital stream (Direct Stream Digital);

Fig. 2 is back to numerical value modular converter principle schematic for data conversion system of the present invention.

Embodiment

Flow the data communication system schematic diagram of (Direct Stream Digital) as shown in Figure 1 based on Direct Digital, analog quantity is imported through behind the ADC that is made up of analog-to-digital conversion module 1 that can produce bit data stream and digital low-pass filtering 2, enter dsp system, the data width that output is identical with input and the bit data stream of clock frequency are exported the high-quality analog signal to the DAC that is made up of D/A converter module and analogue low pass filtering 7.Dsp system comprise bit data stream to the conversion 3 of RNS, based on the DSP of RNS handle 4 and RNS to the conversion 5 of bit data stream.

This system does not carry out PCM (pulse coder modulation Pulse Code Modulation) and directly introduces bit data stream, in ADC, finish filtering, in DAC, carry out demodulation, to help to improve the performance of whole system, remove because the conversion noise that quantizing noise that the restriction of pcm encoder data bit brings and digital demodulation are brought.No matter be Delta-Sigma ADC or DAC, all form by the Delta-Sigma module and the low-pass filter circuit that can produce bit data stream, the bit data stream here is to produce after adopting n over-sampling doubly, with voltage levvl of n Bits Serial data characterization, if the sampled value of accumulative total is greater than sampled value last time then export " 1 " in this cycle, if equal last time sampled value then export " 0 ".Although the bit data stream that produces has passed through low-pass filtering, but various noises still exist, therefore, in order to obtain the high-quality characteristics of signals, bit data stream can be sent into again DSP handles, if system needs analog signal output, then export to Delta-SigmaDAC by the bit data stream of DSP generation same band again.In order to obtain good " power consumption * area * speed " characteristic, adopt the DSP of RNS system to arise at the historic moment, therefore, the mutual change-over circuit of the bit data stream-RNS of said system is to realize that this function must obligato interface.

At the Delta-Sigma system, based on (2 ⁿ-1) 2 ⁿ(2 ⁿ+ 1) module proposes and has realized a kind of numerical value design of switching circuit method, the bit data stream of Delta-Sigma ADC output need not pcm encoder can send into forward direction bit data stream-RNS change-over circuit realization RNS conversion, handle so that send into, can directly send into the rear end change-over circuit for the RNS data of DSP output and realize bit data stream data reproduction under the same module based on the Programmable DSPs of RNS.Input and output have identical data width and clock frequency in the system, guarantee the consistency of input and output data.

Utilize back of the present invention to the numerical value modular converter, not only reduced taking up room of memory, improved the speed of data processing, and expanded the width of data processing.In the Programmable DSPs system design, provide the interface of a data output with RNS data-bit data stream module application for data handling system.So that be achieved based on the Programmable DSPs design of RNS.

1, Chinese remainder theorem (CRT)

Chinese remainder theorem is meant, given one group of relatively prime in twos integer: m ₁, m ₂,, m _r, each element does not have common divisor GCD (m _i, m _j)=1, wherein i ≠ j.The big or small M=m in space ₁* m ₂* m _r, be called the dynamic range of module, the expression scope be [0, M).The RNS of number X represents to be exactly (c ₁, c ₂..., c _r), c _i=X mod m _iAnd to integer: c arbitrarily ₁, c ₂... c _r, following simultaneous congruence equation group is to mould m ₁, m ₂,, m _rHave public affairs to separate:

$\left\{\begin{array}{c}x\≡c_1\left(\mathrm{mod}{m}_1\right)\\ x\≡c_2\left(\mathrm{mod}{m}_2\right)\\ x\≡c_3\left(\mathrm{mod}{m}_3\right)\end{array}\right.---\left(1\right)$

In order to illustrate that the mutual modular converter of RNS and bit data stream realizes principle, below our proof based on M, these simultaneous equations have unique separating.Suppose c, c ' ∈ Z satisfies above simultaneous equations, that is to say, to i ∈ arbitrarily 1 ..., r} all has c ≡ c _i(mod mi) and c ' ≡ c _i(modm _i).Therefore, to i ∈ arbitrarily 1 ..., there is m in r} _i| c-c '.Because m _i, m _jRelatively prime in twos, wherein i ≠ j, i.e. GCD (m _i, m _j)=1.According to following character:

(1). to any i ∈ 1 ..., r} all has gcd (m _i, M/m _i)=1.

(2). if for all i ∈ 1 ..., r} all has r _i| l, then M|l.

Can obtain m ₁* m ₂* m _r| c-c ', i.e. c ≡ c ' (mod M).That is, it separates unique under mould M.On the other hand, if c satisfies simultaneous equations, and c ' ∈ Z satisfies c ' ≡ c (modM), then since to i ∈ arbitrarily 1 ..., r}, m _i| M, old friend c ' ≡ c ≡ c _i(mod m _i). that is c ' satisfies simultaneous equations.

For example x=233 satisfies following simultaneous equations:

$\left\{\begin{array}{c}x\≡2\left(\mathrm{mod}3\right)\\ x\≡1\left(\mathrm{mod}4\right)\\ x\≡3\left(\mathrm{mod}5\right)\end{array}\right.---\left(2\right)$

So, according to above-mentioned theory,, satisfy c ≡ 233 ≡ 53 (mod60) to integer c arbitrarily, can satisfy this group simultaneous equations.That is the integer that only satisfies c ≡ 53 (mod 60) just satisfies these simultaneous equations.

2, data transaction (Delta-Sigma) system is back to numerical value modular converter 5, and the back is the conversion of RNS-bit data stream to the numerical value conversion:

RNS being reduced to the back in design of bit data stream, should consider the bandwidth of the bit data stream of input.Both should be consistent.According to Chinese remainder theorem, based on mould M, for one group of given RNS data R of system ₁, R ₂, R ₃, modular converter when being reduced to bit data stream and implementation method are all very simple.Output with the unique solution x control bit data flow of formula (3) Simultaneous Equations.That is, continue x " 1 " (being high level) of output under the Synchronization Control of clock, if do not reach the appointment figure place this moment, then alternately output " 1 " and " 0 " after this is to keep the balance of data, until reaching the appointment figure place.

$\left\{\begin{array}{c}x\≡R_1\left(\mathrm{mod}(2^n-1)\right)\\ x\≡R_2\left(\mathrm{mod}{2}^n\right)\\ x\≡R_3\left(\mathrm{mod}(2^n+1)\right)\end{array}\right.---\left(3\right)$

The back mainly comprises as shown in Figure 2 to numerical value modular converter 5 schematic diagrams: triple channel subtract counter: to mould (2 ⁿ+ 1) counter of modulo operation is to mould 2 ⁿThe counter of modulo operation is to mould (2 ⁿ-1) counter of modulo operation, full zero comparator and a multidiameter option switch.In the upper edge of synchronised clock, three counters are carried out synchronously respectively and are subtracted 1 operation, and when any one counter reduces to 0 and other counters when not counting 0, then this counter reloads the mould value of this passage in the upper edge of next clock, as, (2 ⁿ+ 1) passage adds patrix value (2 ⁿ+ 1), and continue to participate in subtracting 1 operation, the rest may be inferred, experiencing n clock up to all three counters, carried out subtracting for n time 1 operate after, its result is 0.All subtract counter shut-down operations.The n value of this moment is the unique solution x of above-mentioned simultaneous equations.In this process according to counter status carry-out bit data flow: do not count simultaneously before 0 at all counters, bit data stream continues output " 1 ", data bit be spaced apart a clock cycle; When the count value of all counters is 0 simultaneously, bit data stream is output " 1 " and " 0 " alternately, the balance that to be system keep data with high level and the low level of a clock cycle of a clock cycle, specify figure place until output, next group RNS data of system update realize that RNS is to this data flow translation function.

Claims (2)

1, the back of a kind of data conversion system is characterized in that to the numerical value modular converter, comprises triple channel subtract counter, full zero comparator and gate, and the triple channel subtract counter comprises mould (2 ⁿ+ 1) counter of modulo operation, to mould 2 ⁿThe counter of modulo operation and to mould (2 ⁿ-1) counter of modulo operation, remainder number system data input triple channel subtract counter carries out complementation, outputs to full zero comparator then, and gate is according to the state of full zero comparator, carry-out bit data flow.

2, the back of a kind of data conversion system comprises the back to the numerical value modular converter of data conversion system to numerical value conversion implementation method, and implementation method may further comprise the steps:

1) based on (2 ⁿ-1) 2 ⁿ(2 ⁿ+ 1) module, one group of given remainder number system data R ₁, R ₂, R ₃, with R ₁, R ₂, R ₃Import respectively the triple channel subtract counter to mould (2 ⁿ-1) counter of modulo operation, to mould 2 ⁿThe counter of modulo operation and to mould (2 ⁿ+ 1) counter of modulo operation, upper edge at synchronised clock, after described three counters are carried out synchronously respectively and are subtracted 1 operation, sending into full zero comparator compares, as this moment three-channel count value be not zero entirely, gate carry-out bit data flow " 1 " is carried out synchronously once more at three counters of next clock and to be subtracted 1 operation;

2) reduce to zero and other counters when not counting 0 when any one counter, then this counter reloads the mould value of this passage in the upper edge of next clock, and continue to participate in subtracting 1 and operate, relatively experiencing n clock again up to all three counters, after having carried out subtracting for n time 1 operation, its result is zero, and gate replaces carry-out bit data flow " 1 " and " 0 ", i.e. system's balance of keeping data with high level and the low level of a clock cycle of a clock cycle;

3) alternately output to the appointment figure place, upgrade next group remainder number system data, get back to step 1) and realize that remainder number system is to the bit data stream conversion.

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