CN101547005A - Oscillation adjusting circuit and oscillation adjusting method - Google Patents
Oscillation adjusting circuit and oscillation adjusting method Download PDFInfo
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- CN101547005A CN101547005A CN200810087012A CN200810087012A CN101547005A CN 101547005 A CN101547005 A CN 101547005A CN 200810087012 A CN200810087012 A CN 200810087012A CN 200810087012 A CN200810087012 A CN 200810087012A CN 101547005 A CN101547005 A CN 101547005A
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Abstract
The invention relates to an oscillation adjusting circuit, which comprises a first circuit. The first circuit receives an input data stream with a given time interval, generates an output signal with a first cycle, determines a first error signal between the given time intervals and the testing periods of the given time intervals, determines a reference error signal according to the period of preset times of the first cycle, and adjusts the first cycle according to the first error signal and the reference error signal, wherein the give time interval is related to the period between the first appearance of a prepositioned pattern and the second appearance of the prepositioned pattern in the input data stream.
Description
Technical field
The present invention relates to a kind of vibration and adjust circuit and method, particularly relate to a kind of vibration that is used for transfer of data and adjust circuit and method.
Background technology
Vibration is adjusted in the system of transfer of data of circuit can effectively apply to have bit rate (Bit rate) or clock synchronization (Clocksynchronization), for example on universal serial (USB) interface, micro-control unit (MCU) or the communication system, utilize the correctness and stability when guaranteeing transmission of data packets of data frequency Synchronization Control accurately.Full speed (Full speed) with USB 1.1 editions is example, under the situation of not using external quartz (Crystal) oscillator, utilize vibration to adjust the internal circuit loop mechanism Auto-Sensing of circuit and the frequency of oscillation of proofreading and correct receiving terminal assembly (Device), make the reference data stream of the internal frequency of receiving terminal and host side synchronous.
The benefit of utilizing vibration to adjust circuit is: (1) can not use height accurately under the condition of external module (as quartz (controlled) oscillator), allows system is the same can stably transmit data; That (2) can save integrated circuit (IC) goes out pin (Pin) number, and the configuration plane on system's plank also can save the placement space of outer member (as quartz (controlled) oscillator), therefore can effectively reduce cost.
Aspect circuit design, the structure that circuit adopts phase-locked loop (PLL) and/or delay-locked loop (DLL) is adjusted in traditional vibration, data transmission standard with USB is an example, and the shortcoming of this structure is as follows: phase-locked loop that (1) is traditional and delay-locked loop need long and continuous input reference frequency reaches locking; (2) it needs tediously long locking time; (3) it needs frequency locking circuit structure accurately, otherwise easily causes the error on the frequency.Based on above reason, phase-locked loop and delay-locked loop very are not applicable on the transmission system of USB.
Disclose a vibration in the bulletin file of U.S. Pat 6670852 and adjusted circuit, it comprises one first circuit and a second circuit.First circuit is subjected to configuration to react control signal, vibrates in the output signal of a first frequency and produce.Second circuit is disposed receives the correction signal of vibrating in second frequency, and when first pattern, react a count value, when second pattern, react a storage values, produce control signal, wherein in first pattern, count value is reacted the difference between first frequency and the second frequency and is adjusted.
Disclose a vibration in the bulletin file of U.S. Pat 7093151 and adjusted circuit, it comprises one first circuit.This first circuit is subjected to configuration to receive input traffic, generation has the output of first frequency, reaction the recording the period of known interval and adjust first frequency, wherein the period between the appearance second time with the pre-determined bit pattern be associated with a pre-determined bit pattern in the input traffic appears for the first time in known interval.The internal frequency that this patent needs huge locking list (Lock-up table) to remember, adjust and proofread and correct first circuit.
Do not use external quartz (controlled) oscillator and locking list in order to make vibration adjust circuit,, need more effective vibration to adjust circuit to dwindle chip area, save the element cost and to provide good selectivity on the communication transmission field widely.
So,,, and, " circuit and method are adjusted in vibration " of the present invention proposed in line with the spirit of working with perseverance through concentrated research in view of above demand.
Summary of the invention
The objective of the invention is to propose a kind of vibration and adjust circuit and method, the cycle of oscillation of the output signal that error signal that utilization is determined and reference error signal are adjusted this circuit is to dwindle chip area, save the element cost and to provide good selectivity on the communication transmission field widely.
For reaching above-mentioned purpose, the present invention at first proposes a kind of vibration and adjusts circuit, and it comprises one first circuit.This first circuit receives the input traffic with known interval, generation has the output signal of period 1, first error signal between the tested period of decision known interval and known interval, period decision reference error signal according to the prearranged multiple of period 1, and adjust the period 1 according to first error signal and reference error signal, wherein the period between the appearance second time with this pre-determined bit pattern be associated with a pre-determined bit pattern in the input traffic appears for the first time in known interval.
Secondly the present invention also proposes a kind of vibration method of adjustment, it has the output signal of period 1 in order to generation, and comprise the following steps: to provide the input traffic with known interval, wherein the period between the appearance second time with this pre-determined bit pattern be associated with a pre-determined bit pattern in the input traffic appears for the first time in known interval; First error signal between the tested period of decision known interval and known interval; According to the period of the prearranged multiple of period 1, the decision reference error signal; And, according to first error signal and reference error signal, adjust the period 1.
The present invention also proposes a kind of vibration at last and adjusts circuit, and it comprises an oscillator, a sequential comparator and an Error processing circuit.This oscillator produces has the output signal of period 1.Timing comparator receives input traffic and the output signal with known interval, error signal between the tested period of generation known interval and known interval, and the period according to the prearranged multiple of period 1 produces reference error signal, and wherein the period between the appearance second time with this pre-determined bit pattern be associated with a pre-determined bit pattern in the input traffic appears for the first time in known interval.Error is adjusted circuit according to error signal and reference error period that it received, produces the control signal of adjusting the period 1.
Description of drawings
Fig. 1 is the schematic diagram that circuit is adjusted in the embodiment of the invention 1 described vibration;
Fig. 2 is the work schedule schematic diagram that circuit is adjusted in the embodiment of the invention 1 described vibration;
Fig. 3 is the schematic diagram that circuit is adjusted in the embodiment of the invention 2 described vibrations;
Fig. 4 is the schematic diagram that circuit is adjusted in the embodiment of the invention 3 described vibrations;
Fig. 5 is the signal schematic representation that circuit is adjusted in the embodiment of the invention 3 described vibrations;
Fig. 6 is the configuration schematic diagram of the embodiment of the invention 3 described ring counters;
Fig. 7 is the embodiment of the invention 3 described frequency error rates and the schematic diagram that concerns of adjusting number;
Fig. 8 is the schematic diagram of the embodiment of the invention 3 described another error comparators and another ring counter; And
Fig. 9 is the schematic diagram that circuit is adjusted in the embodiment of the invention 4 described vibrations.
Label declaration
91,92,93,94: circuit is adjusted in vibration
11,21,41: timing comparator
12: error is adjusted circuit
13,23,43: oscillator
211: the edge detection device
212,312: error comparator
2121,3121: counter
2122,3122: comparator
2123,223: latch unit
22: approach buffer continuously and adjust circuit
221,321: ring counter
222: adder and substracter circuit
24,26: divider
25: control unit
42: the Error processing circuit
CLK1, CLK2, OSC, OSC1: output signal
DATA1, DATA2, DATA4: input traffic
SERR1, SERR2, SERR4: error signal
SREF1, SREF2, SREF4: reference error signal
SM1, SM2, SM3: compare result signal
CA1, CA2, CA4: control signal
T1, TFRAME: known interval
T2: compare the period
T3: adjust the period
TS, CS, DS: signal
TOSC, TOSC1: cycle
f
OSC: frequency
FD1, FD2: frequency divider
OSCDIV: frequency elimination signal
TOSCDIV: tested period
SPD2: segment signal during error
T
ERROR: the error period
SFS2: fast slow signal
FS: speed relation value
TAP1, TAP2, TAP3, TAP4: reference error period
PRT1: prearranged multiple
MIN, XIN, XIN0, XIN1, XIN2: judgment value
PRT2, PRT3, PRT4: count value
ADJ1, ADJ2: adjust signal
MRK: beacon signal
QB, MD, ACODE: quantized value
Embodiment
Below in conjunction with accompanying drawing,, describe the present invention in detail by specific embodiments of the invention.
See also Fig. 1, the schematic diagram of circuit is adjusted in its vibration that is provided for the embodiment of the invention 1.As shown in Figure 1, vibration is adjusted circuit 91 and is comprised an oscillator 13, a sequential comparator 11 and error adjustment circuit 12, and wherein receiver (Receiver) (not shown) that circuit 91 can be positioned at receiving terminal is adjusted in vibration.Oscillator 13 produces the output signal CLK1 with period 1, and wherein the period 1 is the inverse of the first frequency of output signal CLK1.
Timing comparator 11 receives input traffic DATA1 and the output signal CLK1 with known interval, error signal SERR1 between the tested period of decision known interval and known interval, period decision reference error signal SREF1 according to the prearranged multiple of period 1, and comparison error signal SERR1 and reference error signal SREF1, to produce compare result signal SM1, wherein input traffic DATA1 can be from transceiver (Transceiver) (not shown) of transmission end, the first time that known interval is associated with a pre-determined bit pattern among the input traffic DATA1 occurs the period between the appearance second time with the pre-determined bit pattern.
Error is adjusted circuit 12 and is received compare result signal SM1, and according to compare result signal SM1, produces control signal CA1, and wherein control signal CA1 comprises the quantized value of conversion from compare result signal SM1.Control signal CA1 offers oscillator 13, and oscillator 13 is adjusted the period 1 of output signal CLK1 according to control signal CA1.Adjust the circulation adjustment of circuit 91 through vibration, the first frequency of output signal CLK1 is with convergence and be locked in the second frequency of input traffic DATA1, and wherein second frequency is the inverse of known interval.Full speed (Fullspeed) with universal serial (USB) 1.1 editions is example, utilizes vibration to adjust circuit 91 and will keep error rate between first frequency and the second frequency (host data rate) in 0.25%.
See also Fig. 2, the schematic diagram of the work schedule of circuit is adjusted in its vibration that is provided for the embodiment of the invention 1.Fig. 2 shows the input traffic DATA1 that transceiver sends and the periodic duty sequential of receiver, its be used in input traffic DATA1 and receiver output signal CLK1 synchronously on, and can use in the lock bit rate or use on the mode of locking frequency (Clock).Input traffic DATA1 comprises at least one known interval T
1, known interval T
1Defined by several recurrent events, particularly known interval T
1Defined by adjacent recurrent event.Those recurrent events comprise several news frame starting point (SOF) packages of a universal serial.The periodic duty sequential comprises that one compares period T
2With an adjustment period T
3When recurrent event appearred in input traffic DATA1, just start-up period sex work sequential was to find the frequency error of input traffic DATA1 and output signal CLK1; Then carry out the frequency adjustment immediately, the first frequency of correcting output signal CLK1 makes input traffic DATA1 and output signal CLK1 synchronous.
See also Fig. 3, the schematic diagram of circuit is adjusted in its vibration that is provided for the embodiment of the invention 2.As shown in Figure 3, vibration adjustment circuit 92 comprises that a sequential comparator 21, approaches buffer continuously and adjusts circuit (Successive approximation register (SAR) tuning circuit) 22, one oscillator 23, a divider 24, a control unit 25 and a divider 26.Control unit 25 is coupled in timing comparator 21, approach buffer continuously adjusts circuit 22 and divider 24, and control timing comparator 21, approaches the running that buffer is adjusted circuit 22 and divider 24 continuously; Have a signal TS between control unit 25 and the timing comparator 21, control unit 25 and approach buffer continuously and adjust between the circuit 22 and have a signal CS has a signal DS between control unit 25 and the divider 24.
Timing comparator 21 receives has known interval T
FRAMEInput traffic DATA2 and frequency elimination signal OSCDIV, when detecting input traffic DATA2, control unit 25 and timing comparator 21 have one-period during the sexual behavior part, control unit 25 starts divider 24, the frequency of output signal OSC is amplified (frequency error also amplifies) thereupon, and obtain among the frequency elimination signal OSCDIV corresponding to known interval T
FRAMETested period T
OSCDIV, wherein during circuit design, need to calculate known interval T
FRAMEWith period T
OSCMultiple relation, with the frequency divider FD1 of decision divider 24.Timing comparator 21 decision known interval T
FRAMEWith tested period T
OSCDIVBetween error signal SERR2, according to period T
OSCThe period decision reference error signal SREF2 of prearranged multiple, and comparison error signal SERR2 and reference error signal SREF2 are with generation compare result signal SM2.
Approach buffer continuously and adjust circuit 22 reception compare result signal SM2, and according to compare result signal SM2 and one or two search computings, produce a control signal CA2, wherein control signal CA2 comprises the quantized value of conversion from compare result signal SM2.Because present embodiment adopts and approaches buffer adjustment circuit 22 continuously, make compare result signal SM2 only must comprise whether to need the data of adjusting frequency and heightening or turning down, therefore do not need to use huge locking list (Lock-up table) to remember, and know definite error magnitude, need not remove the numerical value of required adjustment of videoing according to huge locking list yet, and then lower the design complexities and the chip area of composed component.When each recurrent event occurs, approach buffer adjustment circuit 22 continuously and can produce control signal CA2 according to compare result signal SM2.Oscillator 23 receives control signal CA2, and adjusts the frequency f of output signal OSC according to control signal CA2
OSC, so, known interval T
FRAMEWith tested period T
OSCDIVBetween error will reduce and convergence zero half and halfly.
Divider 26 is provided with a frequency divider FD2, receives output signal OSC, and according to output signal OSC and frequency divider FD2, produces an output signal CLK2.By selecting frequency divider FD2, as known interval T
FRAMEWith tested period T
OSCDIVBetween error convergence zero time, can make the frequency of the frequency of output signal CLK2, and make two signal Synchronization near input traffic DATA2.
See also Fig. 4, the schematic diagram of circuit is adjusted in its vibration that is provided for the embodiment of the invention 3.The detail section that circuit 93 has shown the vibration adjustment circuit 92 of Fig. 3, the omission that wherein repeats narration are adjusted in the vibration of Fig. 4.As shown in Figure 4, timing comparator 21 comprises an edge detector 211 and an error comparator 212.
Edge detection device 211 is coupled in control unit 25 and 25 controls of controlled unit, edge detection device 211 receives input traffic DATA2 and frequency elimination signal OSCDIV, the edge of a pulse of detecting input traffic DATA2 and the edge of a pulse of frequency elimination signal OSCDIV, first start time point of decision known interval and first termination time point and second start time point and second termination time point of tested period, to produce error signal SERR2, wherein error signal SERR2 comprises having error period T
ERRORError the time segment signal SPD2 and fast slow signal SFS2 with speed relation value FS.
Edge detection device 211 utilizes the edge of a pulse of detecting input traffic DATA2 to detect the pre-determined bit pattern of input traffic DATA2, with decision known interval T
FRAMEFirst start time point and first termination time point, be example with the full speed (Full speed) of USB1.1 version, edge detection device 211 detecting news frame starting point (SOF) packages.
Error comparator 212 is coupled in control unit 25 and 25 controls of controlled unit, and error comparator 212 is provided with prearranged multiple PRT1, receives output signal OSC and error signal SERR2, by the triggering of error signal SERR2, and the period T of count output signal OSC
OSCPrearranged multiple PRT1 produce and have reference error period T
AP1Reference error signal SREF2, and according to error signal SERR2 and reference error signal SREF2, produce compare result signal SM2.
Error comparator 212 comprises a counter 2121, a comparator 2122 and a latch unit 2123.Counter 2121 is provided with prearranged multiple PRT1, receives error signal SERR2 and output signal OSC, and according to prearranged multiple PRT1, output signal OSC and error period T
ERRORStart time point, produce reference error signal SREF2.Segment signal SPD2 and reference error signal SREF2 when comparator 2122 receives error, and relative error period T
ERRORWith reference error period T
AP1, wherein as error period T
ERRORGreater than reference error period T
AP1The time, approach buffer continuously and adjust circuit 22 adjustment oscillators 23, make error period T
ERRORLess than reference error period T
AP1Latch unit 2123 receives fast slow signal SFS2, and breech lock speed relation value FS, to produce the judgment value MIN among the compare result signal SM2.
Approach buffer adjustment circuit 22 continuously and comprise a ring counter 221, an adder and substracter circuit 222 and a latch unit 223.Ring counter receives compare result signal SM2, and according to compare result signal SM2, produces one and adjust signal ADJ1.Adder and substracter circuit 222 receives control signal CA2 and adjusts signal ADJ1, and adjusts control signal CA2 according to adjusting signal ADJ1, adjusts signal ADJ2 to produce one.The adjustment signal ADJ2 that latch unit 223 breech locks are received is to produce control signal CA2.
Now, with one be actually used in the USB1.1 version at full speed the example of specification illustrate that the vibration of Fig. 4 adjusts the running of circuit 93.See also Fig. 5, the signal schematic representation of circuit is adjusted in its vibration that is provided for the embodiment of the invention 3.The signal of Fig. 5 comprises having known interval T
FRAMEBeacon signal MRK, frequency elimination signal OSCDIV, error the time segment signal SPD2 and reference error signal SREF2.When the USB receiver is connected to usb host, promptly receive input traffic DATA2 from usb host; According to the full speed specification of USB1.1 version, can know that input traffic DATA2 has the T of known interval accurately that indicates recurrent event
FRAME, it is 1ms ± 500ns, wherein ± 500ns is the error amount that known interval TFRAME may occur, promptly error rate is ± 0.05%.
In beacon signal MRK, indicate known interval T by an impulse duration
FRAMEWhen edge detection device 211 and control unit 25 detected recurrent event, control unit 25 can be removed the output signal OSC that it received frequently by notice divider 24, and wherein the frequency divider FD1 of divider 24 is set to 12000.Here, the frequency f of output signal OSC
OSCBe designed to 12MHz ± 5%, the possible error amount that wherein ± 5% is oscillator 23 when initial vibration, this error amount through behind the frequency elimination of divider 24 by average and amplify 12000 times, therefore produce and have tested period T
OSCDIV(T
OSCDIV=T
OSC* 12000) frequency elimination signal OSCDIV, wherein T
OSCBe the cycle of output signal OSC, and tested period T
OSCDIVAlso indicate by an impulse duration.
Edge detection device 211 receives input traffic DATA2 and frequency elimination signal OSCDIV, and under the control of control unit 25, generation has known interval T
FRAMEBeacon signal MRK, decision known interval T
FRAMEFalling edge (termination time point) and tested period T
OSCDIVFalling edge (termination time point) between error period T
ERROR(T
ERROR=| T
OSCDIV-T
FRAME|), and decision known interval T
FRAMEWith tested period T
OSCDIVBetween speed relation value FS.Present embodiment omits the detecting of rising edge, because as known interval T
FRAMERising edge (start time point) when occurring, the rising edge (start time point) of frequency elimination signal OSCDIV occurs immediately, so the worst error of two rising edges is 1 period T
OSC, that is error rate has only 1/12000=0.0083%, its on specification ± 0.25%, be negligible, so the initial point that opens of rising edge is used as unanimity, and only do the judgement of falling edge.
Then, error period T
ERROROffer error comparator 212 with speed relation value FS and make comparisons, wherein the counter 2121 in the error comparator 212 is provided with the prearranged multiple PRT1 of expression counts, and its value is 24; At this moment, error comparator 212 can be because known interval T
FRAMEFalling edge or tested period T
OSCDIVFalling edge and flip-flop number 2121 makes counter 2121 begin to count and produce the reference error period T of about 2 μ s
REFA2(T
REFA2=T
OSC* 24), reference error period T wherein
REFA2It is an error criterion value.
Error period T
ERRORWith reference error period T
REFA2Offer error comparator 212 interior comparators 2122 and do the comparison of period size, to produce the judgment value XIN among the compare result signal SM2; As error period T
ERRORGreater than reference error period T
REFA2The time, judgment value XIN is made as 0, the frequency f of its expression output signal OSC
OSCNeed to adjust; As error period T
ERRORLess than reference error period T
REFA2The time, judgment value XIN is made as 1, the frequency f of its expression output signal OSC
OSCDo not need to adjust.The mathematical expression of decision judgment value XIN is expressed as follows:
W＝T
ERROR-T
REFA2＝|T
OSC×12000-T
FRAME|-T
OSC×24；
Wherein, work as W〉0, XIN=0 then; As W ≦ 0, then XIN=1.
Selected value that it should be noted that the prearranged multiple PRT1 of counter 2121 is 24, and determines that the factor of its value is as follows: because the precision of the full speed specification requirement frequency of USB1.1 version is ± 0.25%, consider the known interval T of usb host end
FRAMEThe rate of change be about ± 0.05%, so the frequency f of the output signal OSC of circuit 93 is adjusted in vibration
OSCBe designed to be locked in ± 0.20% in.The period T of output signal OSC
OSCFor 83.33ns (1/12MHz), with period T
OSCCount the period that promptly is similar to 2 μ s for 24 times, the period of the period of 2 μ s than last 1ms then is 0.2%.In addition, if will be to take from the reference error period T of output signal OSC
REFA2(2 μ s) will have a doubtful point as the error criterion value, and the related reference error period T that makes because output signal OSC is not accurately, but is arranged ± 5% variable error
REFA2(2 μ s) also have ± 5% variable error.And this doubtful point is not a problem, has 5% the margin of error because suppose present output signal OSC, and known to preceding, divider 24 can amplify 12000 times with the error of output signal OSC, thus this moment, error period T
ERRORThe margin of error (5% * 12000) can be much larger than reference error period T
REFA2The margin of error (5% * 24); After adjusting oscillator 23 one after another through back coupling then, the period T of output signal OSC
OSCThe margin of error can slowly reduce, also can make reference error period T
REFA2Be contracted to the period of 2 μ s.
Speed relation value FS offers the latch unit 2123 in the error comparator 212, and error comparator 212 utilizes latch unit 2123 to preserve speed relation value FS and produces judgment value MIN among the compare result signal SM2; When judgment value MIN equals 0, the frequency f of expression output signal OSC
OSCToo slowly, need raising frequency; Otherwise, when judgment value MIN equals 1, the frequency f of expression output signal OSC
OSCNeed frequency reducing too soon.Judgment value XIN among the compare result signal SM2 and MIN offer and approach buffer continuously and adjust circuit 22 and remove working frequency f
OSCCorrection control, and the relation of judgment value XIN and MIN and frequency state is as shown in table 1 below:
| XIN | | Frequency state | |
| 0 | 0 | |
|
| 0 | 1 | Frequency reducing | |
| 1 | 0 | |
|
| 1 | 1 | Untuned |
Table 1
Because using, present embodiment approaches the control that buffer adjustment circuit 22 comes working frequency to proofread and correct continuously, so its needs are known the frequency f of output signal OSC
OSCBe too soon, too slow or suitably (in ± 0.2% the error), and just be enough to express above message by two judgment value XIN and the MIN that error comparator 212 is provided.Approach buffer adjustment circuit 22 continuously and be subdivided into ring counter (Ring counter) 221, adder and substracter circuit 222 and latch unit 223, its main order ground is that judgment value XIN and MIN are converted to the control signal CA2 that oscillator 13 can be discerned, and in order to make frequency f
OSCCorrection obtain enough accuracy, the quantized value ACODE of control signal CA2 needs enough figure places.
One set point of the pre-change frequency error rate of ring counter 221 definition, and the configuration schematic diagram of ring counter 221 is as shown in Figure 6.When the ring counter 221 of Fig. 6 receives judgment value XIN is 0 information, then starts to change, and sees through and sets, and ring counter 221 can change the quantized value QB that adjusts signal ADJ1 at every turn, so frequency f
OSCError rate will reduce step by step, for example 1.6% → 0.8% → 0.4% → 0.2% → 0.1% so that known interval T
FRAMEWith tested period T
OSCDIVSynchronously; Therebetween, if the frequency error rate reduce to ± 0.2% in, then judgment value XIN will become 1, and quantized value QB can skip to 0, with stop frequency f
OSCAdjustment.In addition, ring counter 221 receives judgment value MIN, and judgment value MIN breech lock is output as the quantized value MD that adjusts signal ADJ1.
Adder and substracter circuit 222 receives control signal CA2 and adjusts signal ADJ1, and change the quantized value ACODE of a preceding state according to quantized value QB, how much determining of the change amount of quantized value ACODE by quantized value QB, quantized value ACODE will increase or reduce then and determined by quantized value MD, so, adder and substracter circuit 222 will determine the change result's of quantized value ACODE quantized value QS, and produce the adjustment signal ADJ2 with quantized value QS.Latch unit 223 receives adjusts signal ADJ2, and breech lock quantized value S, has the control signal CA2 of quantized value ACODE with generation.Oscillator 13 receives control signal CA2, and adjusts the frequency f of output signal OSC according to quantized value ACODE
OSCAdjust the simple in structure and clear of circuit 22 because approach buffer continuously, so chip area can dwindle.
Divider 26 is provided with slowly device (Buffer) (not shown) of a frequency divider FD2 and, receives output signal OSC, and inciting somebody to action accurately via frequency elimination, synchronous frequency signal offers USB device or micro-control unit (MCU) use.Control unit 25 in order to control with coordinate timing comparator 21, approach action between buffer adjustment circuit 22 and the divider 24 continuously, this action comprises that vibration adjusts extracting opportunity that frequency elimination control, the vibration of the startup opportunity of circuit 93, divider 24 adjust in the circuit 93 signal between each element and reply control, and guarantees the correctness of data when circulation.
Therefore, the circuit technology that utilizes vibration to adjust circuit 93 just can be corrected to the frequency of oscillation of receiver inside the Frequency Synchronization with the USB transmission end, and Fig. 7 has shown the operation situation of this process.In Fig. 7, number is adjusted in the X-axis representative, and Y-axis is represented frequency error rate (%), and wherein frequency error rate (%) is the frequency of output signal CLK2 and the percentage error of transmission end synchronizing frequency.One-period occurs during the sexual behavior part at each input traffic DATA2, just adjust the frequency of oscillation of oscillator 13, the frequency f of the OSC of correcting output signal step by step
OSC, it does not need higher frequency to count, and does not also need huge locking list, therefore, the power consumption on the cpable of lowering power and judge on error, the frequency after synchronously can not float, system can revise at any time, and stability is higher.Under the identical situation, this invention structure also can be used in the locking synchronously of frequency, and as top example, the designer sets up relativeness, the error of detecting frequency signal and the frequency size of automatic guiding output frequency make system more accurate in data transmission procedure.
In Fig. 7, if because volume production, when making the initial frequency of oscillation of oscillator 23 can't be modified to lower frequency error rate, if just the initial frequency error rate be 4%, 5% or more than, then may need the adjustment of tens times or twenties times the frequency error rate can be dropped in 0.2%; Or frequency adjusts and is locked at 0.2% o'clock, because external factor makes the unexpected drastic change of frequency error rate to higher, do not think again to adjust too slowly, at this moment, can make following change to the error comparator among Fig. 4 212 and the structure of ring counter 221.
See also Fig. 8, the schematic diagram of its another error comparator 312 that is provided for the embodiment of the invention 3 and another ring counter 321.As shown in Figure 8, error comparator 312 comprises a counter 3121, a comparator 3122.Counter 3121 is provided with three count value PRT2, PRT3 and PRT4, segment signal SPD2 and output signal OSC when receiving error, and according to these count values PRT2, PRT3, PRT4, output signal OSC and error period T
ERRORStart time point, produce and to have three reference error period T
AP2, T
AP3, T
AP4Reference error signal SREF3.Comparator 3122 is in order to relative error period T
ERRORWith those reference error periods T
AP2, T
AP3, T
AP4, to produce compare result signal SM3.
With the data instance of reality, those count values PRT2, PRT3, PRT4 are given as 360,120 and 24 respectively, then reference error period T
AP2Can be 30 μ s (T
REFB1=T
OSC* 360), its expression 3% (sign point of 30 μ/lm); Reference error period T
AP3Can be 10 μ s (T
REFB2=T
OSC* 120), its expression 1% (sign point of 10 μ/lm); Reference error period T
AP4Can be 2 μ s (T
REFB2=T
OSC* 24), its expression 0.2% (sign point of 2 μ/lm).Therefore, if error period T
ERRORGreater than reference error period T
AP2, represent that then present frequency error rate surpasses 3% (XIN2=0); If error period T
ERRORGreater than reference error period T
REFB2, represent that then present frequency error rate surpasses 1% (XIN1=0), so can be in the hope of three judgment value XIN2, the XIN1 of the compare result signal SM3 of following table 2, the truth table of XIN0:
| XIN2 | XIN1 | XIN0 | The |
| 0 | 0 | 0 | >3％ |
| 0 | 0 | 1 | |
| 0 | 1 | 0 | |
| 0 | 1 | 1 | |
| 1 | 0 | 0 | 1～3％ |
| 1 | 0 | 1 | |
| 1 | 1 | 0 | 0.2～1％ |
| 1 | 1 | 1 | <0.2％ |
Table 2
Obtained the truth table of table 2, promptly can know the scope of present frequency error rate, therefore, error comparator 412 is given ring counter 321 with the compare result signal SM3 that generation has judgment value XIN2, XIN1, XIN0.At this moment, ring counter 321 also will be made suitably in the mode of similar Fig. 6 and change, suppose XIN2 XIN1 XIN0=000, represent that present frequency error rate surpasses 3%, can set adjustment (adjustment as 2%) by a relatively large margin this moment for, if XIN2 XIN1 XIN0=100, represent that present frequency error rate is between 1～3%, can do in amplitude adjustment (adjustment) as 0.5% or 1%, by that analogy, the designer can set up the size of pre-change frequency error rate on their own, and satisfying to need to adjust problem of a specified duration, to improve system effectiveness.
See also Fig. 9, the schematic diagram of circuit is adjusted in its vibration that is provided for the embodiment of the invention 4.As shown in Figure 9, vibration adjustment circuit 94 comprises an oscillator 43, a sequential comparator 41 and an Error processing circuit 42.Oscillator 43 produces has period T
OSC1Output signal OSC1.Timing comparator 41 receives input traffic DATA4 and the output signal OSC1 with known interval, the error signal SERR4 between the tested period of generation known interval and known interval, and according to period T
OSC1Period of prearranged multiple produce reference error signal SREF4, wherein the period between the appearance second time with the pre-determined bit pattern be associated with a pre-determined bit pattern among the input traffic DATA4 appears for the first time in known interval.Error processing circuit 42 receives error signal SREF4 and reference error signal SERR4, and according to error signal SREF4 and reference error signal SERR4, produces adjustment cycle T
OSC1Control signal CA4.
Herein, see also Fig. 9 vibration method of adjustment provided by the present invention is described, it has period T in order to generation
OSC1Output signal OSC1, this method comprises the following steps: to provide the DATA4 of the input traffic with known interval, and wherein the period between the appearance second time with this pre-determined bit pattern be associated with a pre-determined bit pattern among the input traffic DATA4 appears for the first time in known interval; Error signal SERR4 between the tested period of decision known interval and known interval; According to period T
OSC1Period of prearranged multiple, decision reference error signal SREF4; And, according to error signal SERR4 and reference error signal SREF4, adjustment cycle T
OSC1
In sum, vibration adjustment circuit provided by the invention and method can reach the effect that goal of the invention sets really.But the above only is the preferred embodiment of this case, and the equivalence that the technical staff in all capable territories does according to spirit of the present invention is modified or changed, and all is encompassed in the application protection range of the present invention.
Claims (14)
1. circuit is adjusted in a vibration, it is characterized in that, comprises:
One first circuit, reception has the input traffic of known interval, generation has first output signal of period 1, determine first error signal between tested period of this known interval and this known interval, period decision reference error signal according to the prearranged multiple of this period 1, and adjust this period 1 according to this first error signal and this reference error signal, wherein the period between the appearance second time with this pre-determined bit pattern be associated with the pre-determined bit pattern in this input traffic appears for the first time in this known interval.
2. circuit is adjusted in vibration as claimed in claim 1, it is characterized in that, wherein:
Described input traffic more comprises at least one known interval;
In described input traffic, this known interval is defined by several recurrent events; And
Recurrent event such as described more comprises several news frame starting point packages of a universal serial.
3. circuit is adjusted in vibration as claimed in claim 1, it is characterized in that the inverse of described period 1 is a first frequency, and this first frequency be adjusted to the host data rate 0.25% within.
4. circuit is adjusted in vibration as claimed in claim 1, it is characterized in that described first circuit more comprises:
One control unit;
One error comparator, be coupled in described control unit and controlled by this control unit, this error comparator is provided with prearranged multiple, receive first output signal and first error signal, triggering by described first error signal, count the prearranged multiple of the period 1 of first output signal, produce reference error signal, and produce a compare result signal according to this first error signal and this reference error signal with reference error period;
One approaches buffer continuously adjusts circuit, is coupled in described control unit and controlled by this control unit, and this approaches buffer continuously and adjusts circuit according to the compare result signal that it received, and produces a control signal;
One oscillator according to the control signal that it received, produces first output signal;
One first divider, be coupled in described control unit and controlled by this control unit, this first divider is provided with a first frequency divisor, receives first output signal, and the appearance first time, first output signal and first frequency divisor according to this pre-determined bit pattern produce a frequency elimination signal;
One second divider, it is provided with a second frequency divisor, receives first output signal, and according to this first output signal and second frequency divisor, produces one second output signal; And
One edge detector, be coupled in described control unit and controlled by this control unit, this edge detection device receives input traffic and frequency elimination signal, detect the edge of a pulse of this input traffic and the edge of a pulse of this frequency elimination signal, first start time point of decision known interval and first termination time point and second start time point and second termination time point of this tested period, to produce first error signal, wherein this first error signal comprises one first an error period and a speed relation value.
5. circuit is adjusted in vibration as claimed in claim 4, it is characterized in that described error comparator more comprises:
One counter, it is provided with prearranged multiple, receives first error signal and first output signal, and according to one the 3rd start time point of this prearranged multiple, first output signal and the first error period, produces reference error signal; And
One first comparator in order to compare the reference error period and the first error period, wherein during the period, approaches buffer continuously and adjusts circuit adjustment oscillator greater than reference error when this first error period, makes this first error period less than this reference error period.
6. circuit is adjusted in vibration as claimed in claim 4, it is characterized in that, the described buffer adjustment circuit that approaches continuously more comprises:
One ring counter, it receives compare result signal, and according to this compare result signal, produces one first and adjust signal;
One adder and substracter circuit, it receives control signal and first and adjusts signal, and adjusts control signal according to this first adjustment signal, adjusts signal to produce one second; And
One latch unit, the second adjustment signal that its breech lock received is to produce control signal.
7. circuit is adjusted in vibration as claimed in claim 4, it is characterized in that, wherein:
The pre-determined bit pattern of described edge detection device detecting input traffic, and this edge detection device detecting one news frame starting point package;
Described first frequency divisor is determined by period 1 and known interval; And/or
The described first error period is the period between first termination time point and second termination time point.
8. circuit is adjusted in vibration as claimed in claim 1, it is characterized in that, wherein:
Described first error signal more comprises one first an error period and a speed relation value;
Described first circuit more according to the period of start time point and several prearranged multiples of period 1 of this first error period, determines several reference error period, and wherein these a little reference error periods are corresponding to these a little prearranged multiples; And
Described first circuit is the reference error periods such as the first error period and those more relatively, adjust the amplitude of period 1 with decision, wherein said first circuit more comprises a counter, and this counter is provided with this a little prearranged multiples, and receive first error signal and first output signal, and, produce the reference error period according to these a little prearranged multiples, first output signal and the 3rd start time point of the first error period.
9. a vibration method of adjustment has first output signal of period 1 in order to generation, it is characterized in that,
Comprise the following steps:
Input traffic with known interval is provided, the first time that wherein said known interval is associated with pre-determined bit pattern in the input traffic occurs the period between the appearance second time with this pre-determined bit pattern;
Determine first error signal between tested period of described known interval and this known interval;
According to the period of the prearranged multiple of described period 1, the decision reference error signal; And
According to described first error signal and reference error signal, adjust this period 1.
10. vibration method of adjustment as claimed in claim 9 is characterized in that, more comprises the following steps:
By the triggering of described first error signal, count the period 1 prearranged multiple of first output signal, produce reference error signal with reference error period;
According to described first error signal and reference error period, produce a compare result signal;
According to described compare result signal and one two search computings, produce a control signal;
According to described control signal, vibration produces first output signal;
The appearance first time, first output signal and first frequency divisor according to described pre-determined bit pattern produce a frequency elimination signal;
According to described first output signal and second frequency divisor, produce second output signal; And
Utilize the edge of a pulse of the described input traffic of detecting and the edge of a pulse of frequency elimination signal, first start time point of decision known interval and first termination time point and second start time point and second termination time point of this tested period, to produce first error signal, wherein this first error signal comprises one first an error period and a speed relation value.
11. vibration method of adjustment as claimed in claim 10 is characterized in that, described known interval is the period between a pair of news frame starting point package.
12. vibration method of adjustment as claimed in claim 10 is characterized in that, wherein:
Described first frequency divisor is determined by period 1 and known interval; And
The described first error period is the period between first termination time point and second termination time point.
13. vibration method of adjustment as claimed in claim 9 is characterized in that, described first error signal more comprises one first an error period and a speed relation value, and this method more comprises the following steps:
Period according to start time point and several prearranged multiples of period 1 of the described first error period determines several reference error period, and wherein those reference error periods are corresponding to those prearranged multiples; And
Utilize the more described first error period and those reference error periods, the amplitude of period 1 is adjusted in decision.
14. circuit is adjusted in a vibration, it is characterized in that, comprises:
One oscillator, generation has the output signal of period 1;
One sequential comparator, reception has the input traffic and the output signal of known interval, first error signal between the tested period of generation known interval and this known interval, and the period according to the prearranged multiple of this period 1 produces reference error signal, and wherein the period between the appearance second time with this pre-determined bit pattern be associated with a pre-determined bit pattern in this input traffic appears for the first time in this known interval; And
One Error processing circuit according to first error signal and the reference error signal that it received, produces the control signal of adjusting the period 1.
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| CN200810087012A CN101547005A (en) | 2008-03-28 | 2008-03-28 | Oscillation adjusting circuit and oscillation adjusting method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103138754A (en) * | 2011-12-05 | 2013-06-05 | 擎泰科技股份有限公司 | Clock generator and a method of generating a clock signal |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103138754A (en) * | 2011-12-05 | 2013-06-05 | 擎泰科技股份有限公司 | Clock generator and a method of generating a clock signal |
| CN103138754B (en) * | 2011-12-05 | 2016-07-20 | 立而鼎科技（深圳）有限公司 | Frequency generator and the method producing frequency signal |
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