CN101546712B

CN101546712B - Method for packaging semiconductor with cavity

Info

Publication number: CN101546712B
Application number: CN200810088589XA
Authority: CN
Inventors: 叶崇茂
Original assignee: Lingsheng Precision Industries Co Ltd
Current assignee: Lingsheng Precision Industries Co Ltd; Lingsen Precision Industries Ltd
Priority date: 2008-03-28
Filing date: 2008-03-28
Publication date: 2010-09-08
Anticipated expiration: 2028-03-28
Also published as: CN101546712A

Abstract

The invention relates to a method for packaging a semiconductor with a cavity, which comprises the following steps of: a, providing a substrate of which the front side has a chip accommodating area; b, forming a barrier layer above the front side; c, coating a UV adhesive layer on the upper surface of the barrier layer; d, removing an area, corresponding to the chip accommodating area, in the UV adhesive layer; e, further removing an area, corresponding to the chip accommodating area, in the barrier layer; f, arranging a chip on the chip accommodating area in an open accommodating chamber and molding an wire on the chip to electrically connect the chip and the substrate; and g, arranging a cover layer on the UV adhesive layer and heating the UV adhesive layer to fix the cover layer on the barrier layer. The design of the invention can reduce glue overflow generated during the packaging of the semiconductor considerably; and the method can be implemented by the prior art without increasing equipment purchase cost.

Description

Method for packaging semiconductor with chamber

Technical field

The present invention is relevant with semi-conductive encapsulation, is meant a kind of modification method of semiconductor packages step especially.

Background technology

Known package assembling with chamber, for example: the mems chip encapsulation or the method for packing of CMOS chip are earlier chip to be sticked on the chip rest area of a substrate mostly, around putting the district, erects this chip the barrier layer (dam) of an enclosure wall shape, this barrier layer bottom surface is engaged in this substrate rest area periphery and chip is surrounded in the centre, electrically connect chip and substrate then, coat viscose in this barrier layer upper surface at last, again with a capping, as glass ... etc., fit in the barrier layer top said chip is packaged in the confined space.

Yet these are known to have in the mems chip packaging technology of chamber, because this viscose be a glue, the rerum natura instability, so be difficult for evenly coating the barrier layer top of this enclosure wall shape, after barrier layer was coated viscose and covered capping, idol had the facts of excessive glue pollution chip again; Moreover, when this capping sticks in this barrier layer, producing the phenomenon of slip because of not solidified viscose easily, and therefore lower its sealing effectiveness, all this kind is all it still must improve part.

As mentioned above, known method for packaging semiconductor with chamber truly has the defective on its project organization, improves waiting.

Summary of the invention

The object of the present invention is to provide a kind of method for packaging semiconductor with chamber, it can reduce the chip damage that the glue that overflows is caused.

To achieve these goals, according to the method for packaging semiconductor with chamber provided by the present invention, include the following step: (a) substrate forms a chip and puts the district on this substrate front side; (b) form a barrier (dam) layer in this top, front, this barrier layer is that a square block and this barrier layer lower surface are put the district across this chip; (c) this barrier layer upper surface is coated with a UV glue-line; (d) this UV glue-line is carried out exposure imaging, and remove the zone of putting the district in this UV glue-line corresponding to this chip; (e) further will put the zone removal in district in this barrier layer corresponding to this chip, make this UV glue-line be formed at this barrier layer top, and enclose an open room; (f) this chip that a chip is arranged in this opening room is put in the district, and stamps lead in substrate and chip chamber, makes this chip and this substrate do electrically connect by this lead; (g) covering layer is arranged on this UV glue-line, and these covering series of strata are sealed this opening room, heat this UV glue-line with this covering layer of set on this barrier layer.

Say further that again the method for packaging semiconductor with chamber provided by the invention includes the following step:

(a) substrate has a front, forms a chip on this front and puts the district;

(b) form a barrier (dam) layer in this top, front, and this barrier layer lower surface is put the district across this chip;

(c) this barrier layer upper surface is coated with a UV glue-line, and treats its curing;

(d) this UV glue-line is carried out exposure imaging, and remove this UV glue-line is put the district corresponding to this chip zone;

(e) remove in the zone of further this barrier layer being put the district corresponding to this chip, makes this UV glue-line be formed at this barrier layer top, and enclose an open room;

(f) this chip that a chip is placed in this opening room is put in the district, and stamps lead in substrate and chip chamber;

(g) on this UV glue-line a covering layer is set, this covering layer is sealed this opening room, heat this UV glue-line with this covering layer of set on this barrier layer.

Described method for packaging semiconductor with chamber, wherein: the zone that this barrier layer is put the district corresponding to this chip in step e is to remove with lapping mode.

Described method for packaging semiconductor with chamber, wherein: this UV glue-line is B rank epoxy (B-stage epoxy).

Thus, the present invention is by the above-mentioned steps flow process, and the excessive glue phenomenon that is produced in the time of can significantly reducing semiconductor packages can also be saved the cost in the manufacturing process.

Description of drawings

Fig. 1 is the action flow chart of a preferred embodiment of the present invention;

Fig. 2 (A) is the present invention's one preferable implementation step schematic diagram;

Fig. 2 (B) is the present invention's one preferable implementation step schematic diagram;

Fig. 2 (C) is the present invention's one preferable implementation step schematic diagram;

Fig. 2 (D) is the present invention's one preferable implementation step schematic diagram;

Fig. 2 (E) is the present invention's one preferable implementation step schematic diagram;

Fig. 2 (F) is the present invention's one preferable implementation step schematic diagram; And

Fig. 2 (G) is the present invention's one preferable implementation step schematic diagram.

Primary clustering symbol description in the accompanying drawing:

Substrate 11

Positive 12

Chip is put district 13

Barrier layer 14

Lower surface 15

UV glue-line 16

Upper surface 17

Open room 18

Chip 19

Lead 21

Covering layer 22

Embodiment

In order to describe steps flow chart characteristics of the present invention place in detail, lift the explanation of a following preferred embodiment and conjunction with figs. as after, wherein:

Fig. 2 (A) is the present invention's one preferable implementation step schematic diagram, and it has shown that chip is put the aspect that the district is provided with on the substrate;

Fig. 2 (B) is the present invention's one preferable implementation step schematic diagram, the aspect when it has shown substrate and barrier layer storehouse;

Fig. 2 (C) is the present invention's one preferable implementation step schematic diagram, and it has shown in the aspect of barrier layer top coating UV glue-line;

Fig. 2 (D) is the present invention's one preferable implementation step schematic diagram, and it has shown removes the UV glue-line is put the zone in district corresponding to this chip aspect;

Fig. 2 (E) is the present invention's one preferable implementation step schematic diagram, and it has shown removes the aspect of putting the zone in district in the barrier layer corresponding to this chip;

Fig. 2 (F) is the present invention's one preferable implementation step schematic diagram, and it has shown that a chip is placed in this chip puts the aspect of distinguishing; And

Fig. 2 (G) is the present invention's one preferable implementation step schematic diagram, and it has shown covering layer is fitted in aspect on this UV glue-line.

See also Fig. 1 and Fig. 2 (A) to Fig. 2 (G), a kind of stack type semiconductor encapsulation method for making for a preferred embodiment of the present invention provided wherein comprises following each step:

Step (a): a substrate 11, have a front 12, a chip is set on this front 12 puts district 13;

Step (b): form a barrier (dam) layer 14 in these 12 tops, front of this substrate 11, this barrier layer 14 is that a square block and this barrier layer 14 are to put district 13 across this chip, makes this chip put district 13 and is covered by the lower surface 15 of barrier layer 14 fully;

Step (c): the upper surface 17 in this barrier layer 14 is coated with the UV glue-line 16 of a suitable thickness, and this UV glue-line 16 is covered with in this upper surface 17, and treats its curing;

Step (d): remove this UV glue-line 16 is put district 13 corresponding to this chip zone; Earlier the part that UV glue-line 16 desires are kept covers shielding, then utilizes the part that does not cover shielding on this UV glue-line 16 of mode etching of exposure imaging, wait remove in this UV glue-line 16 put the zone in district 13 corresponding to this chip after, again this shielding is picked up;

Step (e): because the zone that this UV glue-line 16 is put district 13 corresponding to this chip is removed, therefore manifest this barrier layer 14 that is positioned at these UV glue-line 16 belows, then the zone removal in district 13 will be put again in this barrier layer 14 corresponding to this chip, the mode of removing can be with grinding, mode such as etching or boring is finished, all distinguish 13 zone because of this UV glue-line 16 part of being removed and the part that this barrier layer 14 is removed again corresponding to this chip storing, so this UV glue-line 16 can be enclosed an open room 18 with barrier layer 14, is that this chip is put district 13 and be somebody's turn to do the bottom of opening room 18;

Step (f): this chip that a chip 19 is placed in this opening room 18 is put in the district 13, and stamped lead 21, make 11 of this chip 19 and this substrates produce electrically connect in substrate 11 and 19 of chips;

Step (g): one covering layer 22 is set in these opening room 18 tops, wherein, be provided with a chip 19 in this opening room 18, this covering layer 22 can be encapsulated in this chip 19 in this opening room 18, this opening room 18 is because this UV glue-line 16 and this barrier layer 14 surround forms, and this UV glue-line 16 is positioned at this barrier layer 14 tops; Therefore this covering layer 22 can be fitted with this UV glue-line 16, waits and heats this UV glue-line 16 again after covering covering layer 22, makes this UV glue-line 16 softening to be attached on this covering layer 22, promptly finishes one and has the semiconductor packages of chamber.

Wherein, this UV glue-line 16 can be B rank epoxy joint glue, and this covering layer 22 can be a glassy layer.

As from the foregoing, the present invention is sticked together glue-line 16 with UV and is preset cemented on barrier layer 14 earlier in manufacture process, its attainable effect be: the excessive glue phenomenon that is produced in the time of can significantly reducing semiconductor packages, and simplify the steps flow chart of encapsulation, make the process of encapsulation more smooth and easy, encapsulation flow process of the present invention does not in addition need to add extra technology, does not therefore have misgivings that increase cost and the operation of finishing encapsulation that can be more easy on making.

Claims

1. method for packaging semiconductor with chamber includes the following step:

(a) substrate has a front, forms a chip on this front and puts the district;

(b) form a barrier layer in this top, front, and this barrier layer lower surface is put the district across this chip;

2. according to the described method for packaging semiconductor with chamber of claim 1, wherein: the zone that this barrier layer is put the district corresponding to this chip in step (e) is to remove with lapping mode.

3. according to the described method for packaging semiconductor with chamber of claim 1, wherein: this UV glue-line is Jie's B epoxy.