CN101546271B - Register allocation method for super block in dynamic binary translation system. - Google Patents
Register allocation method for super block in dynamic binary translation system. Download PDFInfo
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- CN101546271B CN101546271B CN2009100504407A CN200910050440A CN101546271B CN 101546271 B CN101546271 B CN 101546271B CN 2009100504407 A CN2009100504407 A CN 2009100504407A CN 200910050440 A CN200910050440 A CN 200910050440A CN 101546271 B CN101546271 B CN 101546271B
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Abstract
The invention relates to a register allocation method for a super block in a dynamic binary translation system. The method is a simplified graph coloring register allocation method according to the characteristic of the super block of the binary translation system. An interference graph is constructed by activity information of variables in the super block; and then a register allocation problem is converted into an interference graph simplification problem to make an object code of the super block use an object platform register maximally and has the characteristic of high object code execution efficiency. During the allocation, the variables in a basic block are allocated with registers according to the different demands in the field of dynamic binary translation; and the allocation comprises common allocation, mandatory specified register allocation, and mandatory non-specific register allocation. The register allocation method has the characteristic of retargetability and the characteristics of good allocation effect and low allocation expense for the super block. The register allocation method is suitable for a plurality of object platforms, particularly for a multi-source multi-objective binary translation platform.
Description
Technical field
The present invention relates to the register allocation method of superblock in a kind of dynamic binary translation system, possess redirected characteristic, can be applicable to the plurality of target platform, be particularly useful for the binary translation platform of multi-source multi-target.
Background technology
Binary translation is the method the most widely of using in the virtual execution technique; Be the adaptive a kind of effective means of platform of transplanting possibility and raising software to be provided for leaving over code; It is under the situation of the source code that does not need executable program; Can run on other target machine platforms dynamically with the conversion of the process of the binary program on the source machine platform.For dynamic binary translator self, execution performance is a very important measurement index.So-called execution performance is meant that the efficient of under former framework, moving with source program is reference, and its loss in efficiency degree under the running environment that dynamic binary translator provides is low more, and the execution performance of translater is good more.
Register is in the superiors in the Computer Storage architecture, be the fastest storage medium of access speed, and because the restriction of die size; Usually the register number is few; The x86 processor of Intel has only 8 general-purpose registers, and the register number of some RISC architecture is more slightly, but also has only the register about tens; Certainly the inside also comprises a lot of specified registers, can by translater use just still less.In order to improve the execution performance of the code after translater is translated, a kind of technology need be adopted in the binary translation field, and its makes the code block after the translation can utilize this scarce resource of register as far as possible efficiently.But for the binary translation field, consider the real-time of dynamic execution, the distribution method expense can not be too high.Therefore the technician must be between register that uses target platform more efficiently and assignment overhead seeking balance.The binary translation field has the technology of structure superblock usually, promptly carries out temperature to some than higher fundamental block altogether, encodes as a piece, forms a superblock.So-called superblock is meant to have an inlet, the code block of one or more outlets.For the distribution of the register in the superblock, also higher because the temperature of its execution is higher to the quality requirements of object code, therefore need to adopt a kind of good register allocation method.
At present, can use following method to accomplish its registers task in the binary translation field:
1, simple register allocation method, this allocation algorithm through to the variable in the superblock number according to target the machine registers number carry out modulo operation one time, the numeral that draws promptly is the register number that is assigned with.If this register is taken by its dependent variable of same instruction, then attempt the register of next numbering.If this register is not taken by its dependent variable in same the instruction, then exchange to internal memory to this content of registers, distribute this register to give current variable then.If this register is idle, directly distribute this register to give current variable.This method is simply effective, and expense is little, is applicable to the promptness characteristic in binary translation field, but does not utilize the information of superblock internal variable, makes allocation result efficient inadequately, and the register service efficiency is not high.
2, graph coloring register allocation method, this method leaves superblock some variablees commonly used in the global register in.Global variable is meant and in this fundamental block, is used that maximum variable of number of times (use-frequency), leaves these variablees in some register in, in the life cycle of whole superblock, they is not done replacement.This method need get ahead and consult whole superblock before distribution, collects the frequency of utilization information of all variablees in the superblock.Distribute some fixing registers to give the highest variable of these frequency of usages then, remaining variables uses simple register allocation method to distribute.This method has been utilized the information of superblock internal variable, but uses fully inadequately, only at incipient stage some variablees that utilized the information fixed allocation collected, the assigning process of follow-up variable has then been abandoned these information fully.
3, based on the register allocation method of next-use information; This method is carried out its registers according to the next-use information of superblock internal variable; So-called next-use information is meant the position that this variable is used next time, and this method is simply effective, is applicable to its registers in the fundamental block.For the superblock of being made up of some fundamental blocks, abundant inadequately to the use of variable information, the allocation result of register is efficient inadequately.
4, figure dyeing distribution method, this method has consequence in static compiler field, and it is a kind of heuristic distribution method of simplifying thinking based on figure.It comprises following several steps:
(1) collection of variable activated information
(2) structure of interference figure
(3) figure simplifies and its registers
In static compiler, the collection process of interfere information can just can reach stable through iteration repeatedly usually, and promptly activated information all no longer changes at each node.Figure simplify run in the process can adopt usually under the situation that figure can not simplify again combination, freezing, select to overflow and actually various advanced means such as overflow and improve and scheme the process of simplifying.This method complexity is too high, and assignment overhead is too big.
Can find out that from four kinds of above-mentioned register allocation methods every kind of method all has its intrinsic relative merits, four collect and utilize the abundance of information to be and increase progressively trend, and simultaneously, assignment overhead and implementation complexity be increase thereupon also.For preceding two kinds of register allocation methods, realize simpler, but utilize the information of superblock internal variable very limited, can not reach effective effect.The third has reached compromise preferably for a fundamental block on allocation result and allocative efficiency.Last a kind of method has made full use of the information of collecting; For static compiler will be the best way; In the binary translation field; In a superblock, also be not enough to remedy for reaching the assignment overhead that this effect is paid according to the raising of the resulting register service efficiency of this kind distribution method.
Therefore need a kind of novel register allocation method that is applicable to superblock in the binary translation of invention, can effectively utilize the information of superblock internal variable, produce good allocation result, again too many assignment overhead can not be arranged.
Summary of the invention
The objective of the invention is to deficiency to prior art; The register allocation method of superblock in a kind of dynamic binary translation system is provided; Satisfy the specific demand of its registers of superblock in the dynamic binary translator field; Such as the susceptibility of binary translation system, in assignment overhead and allocation result, reach compromise to assignment overhead.
Be to realize above-mentioned purpose, a kind of register allocation method of the present invention's design is figure that a kind of characteristic according to the binary translation system superblock the has been simplified register allocation method that dyes.Because distribute to as if superblock, will be on assignment overhead between the register allocation method that dyes based on the register allocation method of next-use and traditional figure.It utilizes the activated information structure interference figure of superblock internal variable; Be converted into its registers problem problem of simplifying of interference figure then; Make the object code of superblock can use the target platform register to greatest extent, have object code and carry out the high characteristic of efficient.
The active position of the inventive method:
Dynamic binary translator can use the profile technology to obtain the execution hot path in order to optimize performance usually, and the structure superblock, in the process of superblock structure, need call this method and accomplish sharing out the work of target platform register.
The concrete steps that the present invention carries out its registers are following:
1) target platform of initialization register divider; The register number that comprises target platform; The instruction of data mobile apparatus between the register of target platform, the data mobile apparatus of internal memory to the data mobile apparatus instruction of register and register to internal memory instructs;
2) initialization register inner skeleton data structure comprises the data structure data of initialization target platform buffer status, and all target platform buffer status are made as the free time, and the variable that is mated is made as sky, and the place instruction is made as sky; All superblock variable positions of initialization are internal memory; Empty and be used for depositing the formation that tabulation is disturbed in the superblock instruction; Initialization is used for depositing the interference tabulation of variable interfere information in the individual instructions for empty; Initialization register predistribution table as a result is empty;
3) travel through to head from each superblock afterbody, check the variable of every instruction successively, therefrom find the variable of DEF type earlier; Check to disturb in the tabulation whether this variable is arranged,, then remove this variable from disturbing in the tabulation if having; Find the variable of USE type again; Check to disturb in the tabulation whether this variable is arranged,, then insert this variable if do not have; After having traveled through all variablees of this instruction; Disturbing tabulation to be inserted into the formation head; And this basis of disturbing tabulation to tabulate as the interference that produces next bar instruction; Till article one instruction of superblock, obtain the formation that the superblock instruction disturbs tabulation to form, accomplish the collection of interfere information;
4) the initialization interference figure is not for existing interference edge; The formation that the instruction of traversal superblock disturbs tabulation to form from the head of the queue to the tail of the queue, the tabulation of the interference in the processing queue successively, all two variablees, all corresponding this interference edge of location records in interference figure to variable in same tabulation; Interference tabulation up to the formation afterbody is processed, and the generative process of interference figure finishes;
5) check the interference edge of each variable through interference figure, if it is the interference edge number is less than target platform register number, then stacked this variable; And the interference edge relevant with this variable in the deletion interference figure, if be no less than target platform register number, then check next variable; If the interference edge of surplus variable all is no less than target platform register number in the interference figure; Then select one of them variable as sacrificing variable, in interference figure, delete, and the relevant with it interference edge of deletion; And then check next variable, till all variablees of interference figure were stacked, interference figure simplification process finished;
6) eject variable successively from stack top, find one not distribute to the register that has the interference relationships variable with it, distribute to this variable, outcome record in predistribution as a result in the table.Till the stack sky, register predistribution finishes;
7) according to difference translation needs the variable in the superblock is carried out the distribution of register, be divided into normal allocation, the distribution of mandatory requirement particular register, the nonspecific its registers of mandatory requirement;
8) for normal allocation, check the state of register successively, be to be assigned with if buffer status is arranged, and be assigned with to as if this variable, then continue to keep this distribution, otherwise check predistribution table as a result; If there is its registers to give this variable, and this buffer status is to be assigned with, then checks interference figure; If there are not interference relationships in variable that is assigned to and current variable, then directly distribute this register, if this variable subsequent instructions is used; Be loaded into this register to the value of the corresponding internal memory of variable; If there is interference relationships, preserve value in this register to the corresponding internal memory of the variable that is assigned to, distribute this register then; If this variable subsequent instructions is used, be loaded into this register to the value of variable; If this register is protected state, then check all registers, if there is the register of idle condition; Then distribute it,, be loaded into this register to the value in the corresponding internal memory of variable if this variable subsequent instructions is used; If there is not idle register; Then search a register that has been assigned with, preserve the internal memory of the corresponding variable of register that the value in this register that has been assigned with has been assigned with to this, the register that distributes this to be assigned with then; If this variable subsequent instructions is used, be loaded into this register to the value in the corresponding internal memory of variable; If do not have its registers to give it in the predistribution result; Then find the register of a non-protected state, preferentially select idle register to distribute to this variable, if what find is idle register; And this variable subsequent instructions is used; Be loaded into this register to the value in the corresponding internal memory of this variable,, at first be kept at the internal memory of the corresponding variable of this register that has been assigned with for this value of the register that distributes if what find is the register that has been assigned with; If this variable subsequent instructions is used, be loaded into this register to the value in the corresponding internal memory of this variable;
9) distribute for the mandatory requirement particular register,, then continue to keep this distribution if the variable that the mandatory requirement register has been assigned with is this variable just; If the variable that the mandatory requirement register is assigned with is not this variable; And there are interference relationships in the variable that is assigned with and this variable; Then be saved in internal memory to the value of mandatory requirement particular register, accomplish data protection and handle, distribute to this variable to this mandatory requirement particular register dependent variable; If this variable subsequent instructions be used and this variable in internal memory; The Data Loading of the corresponding internal memory of this variable to the mandatory requirement particular register, if this variable subsequent instructions be used and this variable in register, the Data Loading of the register of this variable correspondence to the mandatory requirement particular register; If the variable that the mandatory requirement register is assigned with is not this variable; And there are not interference relationships in the variable that is assigned with and this variable; Then distribute to this variable to this mandatory requirement particular register; If this variable subsequent instructions be used and this variable in internal memory; The Data Loading of the corresponding internal memory of this variable to the mandatory requirement particular register, if this variable subsequent instructions be used and this variable in register, the Data Loading of the register of this variable correspondence to the mandatory requirement particular register;
10) for the nonspecific its registers of mandatory requirement; Preserve state to a temporary variable of the nonspecific register of mandatory requirement earlier; If the nonspecific register of mandatory requirement has been distributed to this variable, then preserve the nonspecific register of mandatory requirement to the corresponding internal memory of this variable, the state of change temporary variable is idle; The state of the nonspecific register of change mandatory requirement is shielded; Then this variable is carried out normal allocation, changes back the value of temporary variable the nonspecific register of shielded mandatory requirement, and with the result of normal allocation as allocation result; If the nonspecific register of mandatory requirement is not distributed to this variable; The state of the nonspecific register of change mandatory requirement is shielded; Then this variable is carried out normal allocation; Change back the value of temporary variable with the nonspecific register of shielded mandatory requirement, and with the result of normal allocation as allocation result.
Register allocation method of the present invention has substantive progressive and significant advantage:
1. the present invention can carry out the relevant register distribution according to different target platforms, has retargetable property, only needs very little change, just can be applicable to the plurality of target platform.With existing register allocation method ratio, the support of binary translation system there is particular processing, the characteristic of multi-source multi-target is especially arranged, only need the register number of two call back functions of change and target platform, just can use facility very.
2. the present invention has good support to the various application scenarioss that its registers in the binary translation system needs.Provide abundant interface to satisfy the various allocation requirements of binary translation to register.
3. assignment overhead is little, and allocation result is good.Based on the figure that the simplifies its registers strategy that dyes, have superblock of traversal and just can accomplish the interfere information collection process, level process such as a characteristic such as completion interference figure simplification process has been cancelled combination, and is freezing.Be applicable to the distribution of register in the superblock granularity of dynamic binary translation system field.Dyeing between the register allocation method based on next-use information register distribution method and classical figure, the characteristics of combining super piece have found expense and result's better balance point.
Embodiment
For understanding technical scheme of the present invention better, further describe below in conjunction with accompanying drawing and through concrete embodiment.Following examples do not constitute qualification of the present invention.
CrossBit is a dynamic binary translation system, and it can be for carrying out the source program in multiple different architecture, and the method through translation and optimization provides the execution environment under the isomery framework.In order to realize multi-source multi-target, CrossBit has used the intermediate code layer, can reduce the translation path like this.Only need translate into the intermediate code piece to front end binary image program (front end), and then become corresponding target platform code (rear end) to the intermediate code block translation, just can form a kind of binary translator.If target platform changes, only need to change a rear end.At present, CrossBit supports SimpleScalar, MIPS, X86, SPARC front end, X86 and SPARC rear end.CrossBit adopts VINST as the metainstruction collection; It is the self-designed cover metainstruction collection of CrossBit project team; Be a kind of virtual machine instruction set of simplifying of low level, have infinite a plurality of 32 virtual registers, Load-Store style architecture, single inclined to one side location addressing mode.Register allocation method face to as if the intermediate code piece formed of these metainstructions.The execution framework of CrossBit is, at first loads the source binary image, finds out the entry address of source image; In TCache, search the target code block to entering the mouth afterwards, so-called TCache is a region of memory, is used for depositing translated target code block; If search successfully, then switch contexts is carried out this target code block; If search failure, then start the front end demoder of CrossBit, in the source image fundamental block that should the entry address being decoded into metainstruction; And being packaged into intermediate code piece (VBlock), the back-end code device that calls CrossBit then converts the metainstruction piece to target code block (TBlock).Be submitted in the TCache then, and then search TCache, TCache will occur and hit, at this moment carry out contextual switching again, carry out the execution of target code block.After target code block is finished, will turn back to the context of CrossBit, carry out the operation of next samsara.So back and forth, be finished up to whole procedure.In the process of carrying out; CrossBit can be provided with a counter in each TBlock; Every execution once will add one, when the number of times of this fundamental block execution surpasses the threshold values of setting, will be set at the object that need do superblock to this TBlock; When execution environment switches to CrossBit, will carry out the superblock structure to the corresponding VBlock of this TBlock.And then the super VBlock that constructs done coding, in the process of coding, with calling the register allocation method that the present invention proposes.
The present invention mainly comprises following plurality of processes, the simplifying of the structure of the initialization before the initialization of the register allocator of specific objective platform, its registers, the collection of interfere information, interference figure, interference figure, predistribution and concrete its registers process.Be without loss of generality, the embodiment of the invention relies on the execution framework of CrossBit and the generation technique of superblock.
1) target platform of initialization register divider
The target platform of initialization register divider comprises the register number of target platform, the data mobile apparatus instruction between the register of target platform, and the data mobile apparatus of internal memory to the data mobile apparatus instruction of register and register to internal memory instructs.
Present embodiment uses constructed fuction RegAllocator (XTUInt8 num_regs; CBOfSpillIncb_spill_in; CBOfSpillOut cb_spill_out, CBOfRegToReg cb_regtoreg) create the register allocator of target platform, the number of register transmits through parameter num_regs; Cb_spill_in, cb_spill_out, cb_regtoreg are function pointers; Can accomplish internal memory respectively on the definite object platform to register, register is to internal memory, and register is to the function of functions such as register.
2) initialization before its registers
Initialization register inner skeleton data structure comprises the data structure data of initialization target platform buffer status, and all target platform buffer status are made as the free time, and the variable that is mated is made as sky, and the place instruction is made as sky; All superblock variable positions of initialization are internal memory; Empty and be used for depositing the formation that tabulation is disturbed in the superblock instruction; Initialization is used for depositing the interference tabulation of variable interfere information in the individual instructions for empty; Initialization register predistribution table as a result is empty.
In the present embodiment, use ra_reg_table [reg_num] to preserve the state of target platform register, reg_num is the register number of target platform; Structure RegUsage comprises status (free; Allocated reserved), mapped_to and inst information, representes the state of register respectively; The virtual register numbering of being mated, the numbering of instruction of living in; Use boolra_vreg_spilled [MAX_VREG_NUM] to preserve the location of virtual register in the metainstruction, wherein MAX_VREG_NUM representes the number of the virtual register that comprises at most in the VBlock, and rule of thumb value is set usually; Use RegLists reg_lists to deposit the formation of disturbing tabulation, be used for preserving the interfere information of collecting, typedef std::queue < RegList>RegLists wherein, typedefstd::set < XTRegNum>RegList; Use XTInt32 reg4vars [MAX_VREG_NUM] save register predistribution result.
The initialization of i, ra_reg_table [reg_num]
The status territory of this array the inside all elements of initialization is free, and the inst territory is made as 0, and the mapped_to territory is made as-1.The expression buffer status is idle, and the variable that is mated is for empty, and the place instruction is for empty, and all registers can be assigned with.
The initialization of ii, ra_vreg_spilled [MAX_VREG_NUM]
All elements in this array of initialization is false.Show that all virtual registers are all in internal memory.If this value is true, show that then this virtual register is in register.
The initialization of iii, RegLists reg_lists
Empty the data of the inside.
The initialization of iv, reg4vars [MAX_VREG_NUM]
The predistribution result of each virtual register of initialization is-1, is expressed as sky.
3) interfere information is collected
Travel through to head from each superblock afterbody, check the variable of every instruction successively, therefrom find the variable of DEF type earlier; Check to disturb in the tabulation whether this variable is arranged,, then remove this variable from disturbing in the tabulation if having; Find the variable of USE type again; Check to disturb in the tabulation whether this variable is arranged,, then insert this variable if do not have; After having traveled through all variablees of this instruction; Disturbing tabulation to be inserted into the formation head; And this basis of disturbing tabulation to tabulate as the interference that produces next bar instruction; Till article one instruction of superblock, obtain the formation that the superblock instruction disturbs tabulation to form, accomplish the collection of interfere information.
Present embodiment has used collectGraphInfo (VBlock*vb) function to accomplish this task, and wherein vb is the pointer of VBlock, points to the address of VBlock, and the VBlock here is super VBlock.What deposit in the VBlock is the VInst instruction of a rule; The collection process of interfere information is for scan all VInst instructions to the end from tail; Take out the parameter of the virtual register type (VReg) of every instruction; According to the numbering of its virtual register with and type (Operand::VREG_DEF or Operand::VREG_USE), put tabulation into.Certain parameter type such as an instruction seq (seq is the position of this instruction in VBlock) is VREG_DEF, checks then whether the current list comprises this numbering, if exist, then in tabulation, removes this numbering, otherwise continues to check next parameter.If certain parameter type is VREG_USE, check then whether the current list comprises this numbering, if comprise then continue next parameter, otherwise, then put this parameter into tabulation.This process was till all parameters of this instruction were all done processing.Put the tabulation that obtains into the reg_lists head, and be the basis, carry out the scanning of next bar instruction with this tabulation.This process is till this super dummy block will head.
4) disturb map generalization
The initialization interference figure is not for existing interference edge; The formation that the instruction of traversal superblock disturbs tabulation to form from the head of the queue to the tail of the queue, the tabulation of the interference in the processing queue successively, all two variablees, all corresponding this interference edge of location records in interference figure to variable in same tabulation; Interference tabulation up to the formation afterbody is processed, and the generative process of interference figure finishes.
Present embodiment is represented interference figure with two-dimensional array, and the initialization interference figure does not exist interference edge to be to be initialized as 0 to this two-dimensional array all elements each other, accomplishes the initial work of interference figure.Travel through reg_lists then from the beginning to the end, take out each tabulation successively, successively each tabulation is processed; All virtual registers in same tabulation; Then there is interference relationships each other in it, and then interference edge of record in interference figure writes down interference edge in the present embodiment and then is presented as; One dimension subscript and two-dimentional subscript are represented the numbering of two virtual registers respectively, are changed to 1 at these two pairing element values of subscript of array.Till the reg_lists afterbody, accomplish and disturb map generalization.
5) interference figure simplifies
Through the interference edge that interference figure is checked each variable,, then stacked this variable if the interference edge number is less than target platform register number; And the interference edge relevant with this variable in the deletion interference figure, if be no less than target platform register number, then check next variable; If the interference edge of surplus variable all is no less than target platform register number in the interference figure; Then select one of them variable as sacrificing variable, in interference figure, delete, and the relevant with it interference edge of deletion; And then check next variable, till all variablees of interference figure were stacked, interference figure simplification process finished.
Present embodiment shows as that two-dimensional array according to the expression interference figure; The line number group element of each virtual register reference numeral of inspection correspondence successively; Statistical content is 1 number; If do not surpass the register number, then stacked this virtual register numbering, and the columns group element zero clearing to numbering.When running into interference figure and can not continue to simplify, select one of them virtual register, with the columns group element zero clearing of this virtual register reference numeral, continue the simplification work of interference figure.Up to interference figure simplify finish till, obtain the virtual register stack that can dye.
6) register predistribution
Eject variable successively from virtual register stack stack top, find one not distribute to the register that has the interference relationships variable with it, distribute to this variable, outcome record in predistribution as a result in the table.Till the stack sky, register predistribution finishes.
In the present embodiment; Be specially the virtual register stack is played stack operation; Check the allocation result of the interfering nodes of this virtual register; Interference figure through visit backup finds all interfering nodes, through the register that uses an interim array representation to be used up by all interfering nodes of current virtual register, finds out the register of a free time in this interim array and gives the stack top virtual register; Keep a record at reg4vars, promptly be changed to this register being numbered down the target element content with this virtual register.Continue to play stack operation, empty, accomplish the predistribution work of register up to stack.
7) distribution of register
According to difference translation needs the variable in the superblock is carried out the distribution of register, be divided into normal allocation, the distribution of mandatory requirement particular register, the nonspecific its registers of mandatory requirement.When variable does not have the specified register requirement, promptly on the target platform any one register can, this situation will be used normal allocation.When variable has the requirement of register, such as being the situation of x86 when target platform, certain variable must be used the ESP register, will use the distribution of mandatory requirement particular register in this case.When variable need be except certain particular register other registers, will use the nonspecific its registers of mandatory requirement in this case.
8) normal allocation
For normal allocation, check the state of register successively, be to be assigned with if buffer status is arranged, and be assigned with to as if this variable, then continue to keep this distribution; Otherwise check predistribution table as a result, if there is its registers to give this variable, and this buffer status is to be assigned with; Then check interference figure,, then directly distribute this register if there are not interference relationships in variable that is assigned to and current variable; If this variable subsequent instructions is used, be loaded into this register to the value of the corresponding internal memory of variable, if there is interference relationships; Preserve value in this register to the corresponding internal memory of the variable that is assigned to; Distribute this register then,, be loaded into this register to the value of variable if this variable subsequent instructions is used; If this register is protected state, then check all registers, if there is the register of idle condition; Then distribute it,, be loaded into this register to the value in the corresponding internal memory of variable if this variable subsequent instructions is used; If there is not idle register; Then search a register that has been assigned with, preserve the internal memory of the corresponding variable of register that the value in this register that has been assigned with has been assigned with to this, the register that distributes this to be assigned with then; If this variable subsequent instructions is used, be loaded into this register to the value in the corresponding internal memory of variable; If do not have its registers to give it in the predistribution result; Then find the register of a non-protected state, preferentially select idle register to distribute to this variable, if what find is idle register; And this variable subsequent instructions is used; Be loaded into this register to the value in the corresponding internal memory of this variable,, at first be kept at the internal memory of the corresponding variable of this register that has been assigned with for this value of the register that distributes if what find is the register that has been assigned with; If this variable subsequent instructions is used, be loaded into this register to the value in the corresponding internal memory of this variable.
Present embodiment uses regAlloc (XTRegNum vreg, RegAccessMode mode) to accomplish normal allocation.Parameter vreg is the virtual register that needs register, and mode representes the access type (DEF or USE) of this virtual register.Mainly contain following steps:
1. order is checked the state of each register; If allocated and with its coupling be vreg, then check vreg whether in register (through checking the spilled sign), if not in register; Need be spill in, and revise the spilled sign.Upgrade the inst value of register.Returning this register uses to vreg.Assigning process finishes.Return.If travel through all buffer status, do not meet this condition, get into step 2.;
2. check reg4vars [vreg],, then check the state of each register that is numbered reg4vars [vreg] if be not less than 0; If 4. free as allocation result, gets into step with this register; If reserved or the instruction of place, place are present instruction, then need redistribute and get into step 3., if allocated; Check interference figure, if virtual register that this register is assigned with and vreg mutual interference mutually, then this content of registers spill out to internal memory; Otherwise do not need spill out to internal memory, then with this register as allocation result.Assigning process finishes, and gets into step 4.;
3. check each buffer status, if free, then with this register as allocation result; If other virtual registers or the state distributed to bar instruction are reserved, then continue to check next register, only till find a suitable register; If distributed to other virtual registers of non-present instruction; Check interference figure, if virtual register that this register is assigned with and vreg mutual interference mutually, then this content of registers spill out to internal memory; Otherwise do not need spill out to internal memory, and with this register as allocation result.Get into step 4.;
If 4. mode is USE, to the register that is assigned to, and the location of upgrading vreg is in register vreg content spill in.The state of that register that renewal is assigned to is the status area update allocated promptly, and the mapped_to area update is vreg, and the inst area update is present instruction.Return allocation result.
9) the mandatory requirement particular register is distributed
Distribute for the mandatory requirement particular register,, then continue to keep this distribution if the variable that the mandatory requirement register has been assigned with is this variable just; If the variable that the mandatory requirement register is assigned with is not this variable; And there are interference relationships in the variable that is assigned with and this variable; Then be saved in internal memory to the value of mandatory requirement particular register, accomplish data protection and handle, distribute to this variable to this mandatory requirement particular register dependent variable; If this variable subsequent instructions be used and this variable in internal memory; The Data Loading of the corresponding internal memory of this variable to the mandatory requirement particular register, if this variable subsequent instructions be used and this variable in register, the Data Loading of the register of this variable correspondence to the mandatory requirement particular register; If the variable that the mandatory requirement register is assigned with is not this variable; And there are not interference relationships in the variable that is assigned with and this variable; Then distribute to this variable to this mandatory requirement particular register; If this variable subsequent instructions be used and this variable in internal memory; The Data Loading of the corresponding internal memory of this variable to the mandatory requirement particular register, if this variable subsequent instructions be used and this variable in register, the Data Loading of the register of this variable correspondence to the mandatory requirement particular register.
Present embodiment uses regAllocForce, and (XTRegNum vreg, XTRegNum expect RegAccessMode) accomplish certain particular register of mandatory requirement and give virtual register.Mainly contain following steps:
1. check the state of register expect,, return error code, finish if deadlock takes place reserved.Otherwise get into 2.;
If 2. the state of expect is allocated, then check whether vreg of its map object, if; Then upgrade ra_reg_table [expect] .inst, check the spilled sign then, if overflowed with present instruction position vinst_seq; And be the USE type, also need be in the expect register the content spill in of vreg, and revise the spilled sign; Return expect then, finish.If not being vreg, its map object do not get into step 3.;
3. check ra_reg_table [expect] .inst,, finish if error code is returned in present instruction; Otherwise, check interference figure, if expect register match objects and vreg have interference relationships, this expect register of spill out then; If there is not interference relationships, do not need spill out operation, search vreg allocation result in the past then, if be assigned with register; Revise the state of original register, change free into such as status, mapped_to changes-1 into, and upgrades the state of expect register; Such as the mapped_to value is vreg, and inst is updated to present instruction, and status changes allocated into.And be loaded into the value of this register in the expect register, return allocation result, finish.If be not assigned with register, if DEF, what is not done, if mode is USE, then spill in virtual register vreg is to expect.Upgrading the state of expect register, is vreg such as the mapped_to value, and inst is updated to present instruction, and status changes allocated into.Return allocation result expect, finish.
10) the nonspecific its registers of mandatory requirement
For the nonspecific its registers of mandatory requirement; Preserve state to a temporary variable of the nonspecific register of mandatory requirement earlier; If the nonspecific register of mandatory requirement has been distributed to this variable, then preserve the nonspecific register of mandatory requirement to the corresponding internal memory of this variable, the state of change temporary variable is idle; The state of the nonspecific register of change mandatory requirement is shielded; Then this variable is carried out normal allocation, changes back the value of temporary variable the nonspecific register of shielded mandatory requirement, and with the result of normal allocation as allocation result; If the nonspecific register of mandatory requirement is not distributed to this variable; The state of the nonspecific register of change mandatory requirement is shielded; Then this variable is carried out normal allocation; Change back the value of temporary variable with the nonspecific register of shielded mandatory requirement, and with the result of normal allocation as allocation result.
Present embodiment uses regAllocForceExcept (XTRegNum vreg, XTRegNum except, RegAccessMode mode) to accomplish the function that distribution other any registers except except are given vreg.Mainly contain following steps:
1. the state of save register except is to temp.Check whether vreg of register except corresponding virtual register, if then spill out register except content is to internal memory, revising the temp state is free, gets into step then 2.;
2. revising the except state is reserved, and concrete operations are ra_reg_table [except]=reserved in this example.The purpose that is revised as the reserved state is to stop to call the regAlloc function vreg is carried out the branch timing, obtains the result of except.(vreg mode) distributes call function regAlloc then.Use the temp value to recover the state of except at last.Return allocation result.Finish.
Present embodiment has also used regAllocReserve (XTRegNum treg) to accomplish the protection work of register.Be mainly used in and avoid certain register to be used.Key step is following:
If 1. the treg state is allocated, check its inst value, if equal present instruction, then make mistakes, otherwise use regSpillOut (treg) operation to accomplish the work that register value is preserved, and modification mapped_to is-1.Get into step 2..If right and wrong allocated state, then what is not done.Get into step 2..
2. the state of revising treg is reserved, returns.Finish.
Present embodiment uses regAllocRelease (XTRegNum treg) to accomplish the work that register discharges, and this part register that main recovery no longer is used of working uses in order to other registers.Also initiatively tackle of the reserved operation of regAllocReserve function to register.
Concrete operations are free for the state of revising treg.
Present embodiment uses regSpillOut (XTRegNum physical_reg) to accomplish the data transfer work of register to internal memory.Specifically be embodied as the vreg that finds physical_reg corresponding; The call back function (* ra_cb_spill_out) (physical_reg, (XTMemAddr) ra_spill_pool+vreg) that calls corresponding platform is then accomplished content the moving to the corresponding memory pool position of vreg of physical_reg.Finish.The function ra_cb_spill_out register that to be bar set according to target platform is to the data mobile apparatus code instruction of internal memory.
Overflow into for register, adopt the operation of regSpillIn, i.e. the mirror image operation of regSpillOut.The operation of regSpillIn is the mirror image operation of regSpillOut.
Claims (1)
1. the register allocation method of superblock in the dynamic binary translation system is characterized in that comprising the steps:
1) target platform of initialization register divider; The register number that comprises target platform; The instruction of data mobile apparatus between the register of target platform, the data mobile apparatus of internal memory to the data mobile apparatus instruction of register and register to internal memory instructs;
2) initialization register inner skeleton data structure comprises the data structure data of initialization target platform buffer status, and all target platform buffer status are made as the free time, and the variable that is mated is made as sky, and the place instruction is made as sky; All superblock variable positions of initialization are internal memory; Empty and be used for depositing the formation that tabulation is disturbed in the superblock instruction; Initialization is used for depositing the interference tabulation of variable interfere information in the individual instructions for empty; Initialization register predistribution table as a result is empty;
3) travel through to head from each superblock afterbody, check the variable of every instruction successively, therefrom find the variable of define styles earlier; Check to disturb in the tabulation whether this variable is arranged,, then remove this variable from disturbing in the tabulation if having; Find the variable of type of service again; Check to disturb in the tabulation whether this variable is arranged,, then insert this variable if do not have; After having traveled through all variablees of this instruction; Disturbing tabulation to be inserted into the formation head; And this basis of disturbing tabulation to tabulate as the interference that produces next bar instruction; Till article one instruction of superblock, obtain the formation that the superblock instruction disturbs tabulation to form, accomplish the collection of interfere information;
4) the initialization interference figure is not for existing interference edge; The formation that the instruction of traversal superblock disturbs tabulation to form from the head of the queue to the tail of the queue, the tabulation of the interference in the processing queue successively, all two variablees, all corresponding this interference edge of location records in interference figure to variable in same tabulation; Interference tabulation up to the formation afterbody is processed, and the generative process of interference figure finishes;
5) check the interference edge of each variable through interference figure, if it is the interference edge number is less than target platform register number, then stacked this variable; And the interference edge relevant with this variable in the deletion interference figure, if be no less than target platform register number, then check next variable; If the interference edge of surplus variable all is no less than target platform register number in the interference figure; Then select one of them variable as sacrificing variable, in interference figure, delete, and the relevant with it interference edge of deletion; And then check next variable, till all variablees of interference figure were stacked, interference figure simplification process finished;
6) eject variable successively from stack top, find one not distribute to the register that has the interference relationships variable with it, distribute to this variable, outcome record in predistribution as a result in the table; Till the stack sky, register predistribution finishes;
7) according to difference translation needs the variable in the superblock is carried out the distribution of register, be divided into normal allocation, the distribution of mandatory requirement particular register, the nonspecific its registers of mandatory requirement;
8) for normal allocation, check the state of register successively, be to be assigned with if buffer status is arranged, and be assigned with to as if this variable, then continue to keep this distribution, otherwise check predistribution table as a result; If there is its registers to give this variable, and this buffer status is to be assigned with, then checks interference figure; If there are not interference relationships in variable that is assigned to and current variable, then directly distribute this register, if this variable subsequent instructions is used; Be loaded into this register to the value of the corresponding internal memory of variable; If there is interference relationships, preserve value in this register to the corresponding internal memory of the variable that is assigned to, distribute this register then; If this variable subsequent instructions is used, be loaded into this register to the value of variable; If this register is protected state, then check all registers, if there is the register of idle condition; Then distribute it,, be loaded into this register to the value in the corresponding internal memory of variable if this variable subsequent instructions is used; If there is not idle register; Then search a register that has been assigned with, preserve the internal memory of the corresponding variable of register that the value in this register that has been assigned with has been assigned with to this, the register that distributes this to be assigned with then; If this variable subsequent instructions is used, be loaded into this register to the value in the corresponding internal memory of variable; If do not have its registers to give it in the predistribution result; Then find the register of a non-protected state, preferentially select idle register to distribute to this variable, if what find is idle register; And this variable subsequent instructions is used; Be loaded into this register to the value in the corresponding internal memory of this variable,, at first be kept at the internal memory of the corresponding variable of this register that has been assigned with for this value of the register that distributes if what find is the register that has been assigned with; If this variable subsequent instructions is used, be loaded into this register to the value in the corresponding internal memory of this variable;
9) distribute for the mandatory requirement particular register,, then continue to keep this distribution if the variable that the mandatory requirement register has been assigned with is this variable just; If the variable that the mandatory requirement register is assigned with is not this variable; And there are interference relationships in the variable that is assigned with and this variable; Then be saved in internal memory to the value of mandatory requirement particular register, accomplish data protection and handle, distribute to this variable to this mandatory requirement particular register dependent variable; If this variable subsequent instructions be used and this variable in internal memory; The Data Loading of the corresponding internal memory of this variable to the mandatory requirement particular register, if this variable subsequent instructions be used and this variable in register, the Data Loading of the register of this variable correspondence to the mandatory requirement particular register; If the variable that the mandatory requirement register is assigned with is not this variable; And there are not interference relationships in the variable that is assigned with and this variable; Then distribute to this variable to this mandatory requirement particular register; If this variable subsequent instructions be used and this variable in internal memory; The Data Loading of the corresponding internal memory of this variable to the mandatory requirement particular register, if this variable subsequent instructions be used and this variable in register, the Data Loading of the register of this variable correspondence to the mandatory requirement particular register;
10) for the nonspecific its registers of mandatory requirement; Preserve state to a temporary variable of the nonspecific register of mandatory requirement earlier; If the nonspecific register of mandatory requirement has been distributed to this variable, then preserve the nonspecific register of mandatory requirement to the corresponding internal memory of this variable, the state of change temporary variable is idle; The state of the nonspecific register of change mandatory requirement is shielded; Then this variable is carried out normal allocation, changes back the value of temporary variable the nonspecific register of shielded mandatory requirement, and with the result of normal allocation as allocation result; If the nonspecific register of mandatory requirement is not distributed to this variable; The state of the nonspecific register of change mandatory requirement is shielded; Then this variable is carried out normal allocation; Change back the value of temporary variable with the nonspecific register of shielded mandatory requirement, and with the result of normal allocation as allocation result.
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| CN1746850A (en) * | 2004-09-07 | 2006-03-15 | 中国科学院计算技术研究所 | In the binary translation to the disposal route of floating-point operation among the X86 |
| CN1755631A (en) * | 2004-09-30 | 2006-04-05 | 中国科学院计算技术研究所 | Library function call disposal route in the binary translation |
| CN101387969A (en) * | 2008-10-16 | 2009-03-18 | 上海交通大学 | Dynamic binary translation method for cooperation design of software and hardware |
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| CN1746850A (en) * | 2004-09-07 | 2006-03-15 | 中国科学院计算技术研究所 | In the binary translation to the disposal route of floating-point operation among the X86 |
| CN1755631A (en) * | 2004-09-30 | 2006-04-05 | 中国科学院计算技术研究所 | Library function call disposal route in the binary translation |
| CN101387969A (en) * | 2008-10-16 | 2009-03-18 | 上海交通大学 | Dynamic binary translation method for cooperation design of software and hardware |
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