CN101541489A

CN101541489A - Memory elements and cross point switches and arrays of same using nonvolatile nanotube blocks

Info

Publication number: CN101541489A
Application number: CN200780035300.1A
Authority: CN
Inventors: C·L·伯廷; X·M·H·黄; T·鲁克斯; R·斯瓦拉贾
Original assignee: Nantero Inc
Current assignee: Nantero Inc
Priority date: 2006-08-08
Filing date: 2007-08-08
Publication date: 2009-09-23
Anticipated expiration: 2027-08-08
Also published as: CN101542631A; CN101558449A; CN101542631B; CN101558449B; CN101541489B

Abstract

Under one aspect, a covered nanotube switch includes: (a) a nanotube element including an unaligned plurality of nanotubes, the nanotube element having a top surface, a bottom surface, and side surfaces; (b) first and second terminals in contact with the nanotube element, wherein the first terminal is disposed on and substantially covers the entire top surface of the nanotube element, and wherein the second terminal contacts at least a portion of the bottom surface of the nanotube element; and (c) control circuitry capable of applying electrical stimulus to the first and second terminals. The nanotube element can switch between a plurality of electronic states in response to a corresponding plurality of electrical stimuli applied by the control circuitry to the first and second terminals.; For each different electronic state, the nanotube element provides an electrical pathway of different resistance between the first and second terminals.

Description

Use memory element and the cross point switches and the array thereof of Nonvolatile nanotube piece

MULTIPLE-BLADE

Interests under the united states patent law § 119 (e) of the claimed following application of the application, its full content is incorporated herein by reference:

The U.S. Provisional Patent Application No.60/918 that on March 16th, 2007 submitted to, 388, be entitled as " memory storage element and cross point switches and the array thereof that use nonvolatile nanotube blocks " (" MemoryElements and Cross Point Switches and Arrays of Same Using NonvolatileNanotube Blocks ");

The U.S. Provisional Patent Application No.60/855 that on October 27th, 2006 submitted to, 109, be entitled as " nonvolatile nanotube blocks " (" Nonvolatile Nanotube Blocks ");

The U.S. Provisional Patent Application No.60/840 that on August 28th, 2006 submitted to, 586, be entitled as " Nonvolatile nanotube diodes " (" Nonvolatile Nanotube Diode ");

The U.S. Provisional Patent Application No.60/836 that on August 8th, 2006 submitted to, 437, be entitled as " Nonvolatile nanotube diodes " (" Nonvolatile Nanotube Diode ");

The U.S. Provisional Patent Application No.60/836 that on August 8th, 2006 submitted to, 343, be entitled as " the scalable Nonvolatile nanotube switch of replacing assembly as electrical fuse " (" Scalable NonvolatileNanotube Switches as Electronic Fuse Replacement Elements ");

The application is the continuation application of following application, and requires the priority under the united states patent law § 120, and its full content is incorporated herein by reference:

The U.S. Patent application No.11/280 that on November 15th, 2005 submitted to, 786, be entitled as " two-terminal nanotube device and system and manufacture method thereof " (" Two-Terminal Nanotube Devices AndSystems And Methods Of Making Same ");

The U.S. Patent application No.11/274 that on November 15th, 2005 submitted to, 967, be entitled as " use and have the memory array of the nanotube that can adapt journey resistance " (" Memory Arrays Using NanotubeArticles With Reprogrammable Resistance "); And

The U.S. Patent application No.11/280 that on November 15th, 2005 submitted to, 599, be entitled as " the non-volatile shadow door bolt that uses nanotube switch " (" Non-Volatile Shadow Latch Using ANanotube Switch ").

The application is relevant to the following application of submitting to simultaneously, and its full content is incorporated herein by reference:

U.S. Patent application No. (to be arranged) is entitled as " Nonvolatile resistive memories of tool scalable two-terminal nanotube switches " (" Nonvolatile Resistive Memories Having ScalableTwo-Terminal Nanotube Switches ");

U.S. Patent application No. (to be arranged) is entitled as " latch circuit and the function circuit of replacing the scalable Nonvolatile nanotube switch of tool of element as electrical fuse " (" Latch Circuits andOperation Circuits Having Scalable Nonvolatile Nanotube Switches asElectronic Fuse Replacement Elements ");

U.S. Patent application No. (to be arranged) is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " (" Nonvolatile Nanotube Diodes andNonvolatile Nanotube Blocks and Systems Using Same and Methods ofMaking Same ");

U.S. Patent application No. (to be arranged) is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " (" Nonvolatile Nanotube Diodes andNonvolatile Nanotube Blocks and Systems Using Same and Methods ofMaking Same "); And

U.S. Patent application No. (to be arranged) is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " (" Nonvolatile Nanotube Diodes andNonvolatile Nanotube Blocks and Systems Using Same and Methods ofMaking Same ").

Background

Technical field

The application relates generally to the switching device of nanotube element and the field of memory storage element.

The discussion of prior art

Digital Logical Circuits is portable electronic equipment, the electronic amusement device that is used for personal computer, for example personal organizers and calculator, and the control circuit of electrical equipment, telephone switching system, automobile, aircraft and other manufacture.Digital Logical Circuits comprises it can being independent or in conjunction with the logic and the memory function of (integrated) on the identical chips.The amount that continues to increase logic and memory is essential.

The key character of Logic Circuit Design is short-term listing, of short duration errorless design cycle, and revises logic function in the site environment more preferably to meet the ability of application demand.Cross point switch matrix helps to meet these demands.Yet, need to improve cross point switch matrix density and need to improve integrated easiness.

Exist ever-increasing demand for enabling than the independence of large memories function or the more and more intensive memory of embedding, its scope extremely surpasses the memory of 1GB from hundreds of KB.The density that these big more memory requirements are more and more higher, more substantial peddling, the cost that every bit is lower, more Gao Su operation, and expend lower power.These demands of challenge semicon industry use improved technology characteristics to dwindle geometry apace.The memory density that increases needs littler unit (cell), and it comprises littler selection transistor and littler storage node.Via using littler unit size to reduce the power consumption of every bit.

Bipolar or integrated circuit that the FET switch element is constructed is volatibility normally.When electric power was bestowed this device, they only kept its internal logic states.Internal state is just lost when electric power removes, unless some Nonvolatile memory circuits add to keep logic state, such as EEPROM (Electrically Erasable Read Only Memory) in device inside or outside.Even used nonvolatile memory to keep logic state, additional circuitry also must be transferred to memory with digital logic states before losing electric power, and recovered the state of each logic circuit when device recovers electric power.Avoid all the other solutions of information dropout in the volatibility digital circuit, for example battery backup also can increase cost and complexity that numeral designs.

Proposed to use the device of nanoscale lines, SWCN for example, tie (with reference to WO 01/03208 as the cross bar switch of memory cell to form knot, device, array and manufacture method thereof (" Nanoscopic Wire-Based Devices; Arrays, and Methods of TheirManufacture ") based on nanoscale lines; And the Science that delivers on July 7th, 2000 of people such as Thomas Rueckes, vol.289, " the nonvolatile RAM that is used for molecular computing " of pp.94-97 based on CNT) (" Carbon Nanotube-Based Nonvolatile Random Access Memory forMolecular Computing ").Below these devices be called nanometer pipeline cross bar switch memory (NTWCM).Under these suggestions, the indivedual single wall nano pipelines that are suspended on other line limit memory cell.The signal of telecommunication is written into one or two lines, so that it attracts in fact each other or repels.Each physical state (promptly attracting mutually or the repulsion line) is corresponding to an electric state.Repelling line mutually is open circuit knot.Attracting line mutually is the closed condition of a formation rectifying junction.When electric power when knot removes, line is just kept its physics (and thereby electric) state, forms non-volatile memory cells thus.

The U.S. Patent No. 6 that is entitled as " electromechanical memory array and the manufacture method thereof of using the nanotube ribbon element " (" Electromechanical Memory Array Using Nanotube Ribbons and Method forMaking Same "), 919,592 disclose the electromechanical circuits such as memory cell, and wherein circuit comprises the structure that has conductive trace and support to extend from substrate surface.Nanotube ribbon element that can dynamo-electric distortion or switch mat are crossed over the support of conductive trace and are hung.Each ribbon element comprises one or more nanotubes.Ribbon element is typically by optionally removing material from the stratiform of nanotube or tangled structure and forming.

For example, as U.S. Patent No. 6,919, in 592 disclosed ground, and nanostructured can be patterned into ribbon element, and this ribbon element can be used as the assembly of creating non-volatile dynamo-electric memory cell.But this ribbon element deflection is in response to the dynamo-electric deflection of the electro photoluminescence of control trace and/or this ribbon element.The deflection physical state of this ribbon element can be used to represent corresponding information state.This deflection physical state has non-volatile attribute, still keeps its physics (and so information) state although the electric power of expression memory cell removes this ribbon element.As be entitled as the U.S. Patent No. 6 of " dynamo-electric three trace junction devices " (" Electromechanical Three-TraceJunction Devices "), 911,682 is disclosed, three trace frameworks can be used for dynamo-electric memory cell, and wherein two traces in these traces are the electrode of the deflection of control ribbon element.

The use that has proposed to be used for the dynamo-electric bistable device that digital information stores is (with reference to the U.S. Patent No. 4 that is entitled as " nonvolatile memory device that comprises the micromechanics memory element " (" Non-volatile Memory DeviceIncluding a Micro-Mechanical Storage Element "), 979,149).

Based on the establishment of the bistable state nano-electromechanical switch of CNT (comprising individual layer) and metal electrode and operate in to have in the patent application early of commonly-assigned us and describe in detail with the application by its structure, the patent documentation of following combination for example.

Summary of the invention

The invention provides the non-volatile memory device and cross point switches and the array thereof that use the Nonvolatile nanotube element.

Down, clad nano pipe switch comprises: (a) comprise the nanotube element of unjustified a plurality of nanotubes, this nanotube element has end face, bottom surface and a plurality of side on the one hand; (b) first and second conducting terminals that contact with this nanotube element, wherein this first conducting terminal places and covers in fact the whole top of this nanotube element, and wherein this second conducting terminal contacts the part of the bottom surface of this nanotube element at least; And (c) control circuit and this first and second conducting terminal electric connection also can apply electro photoluminescence to it, wherein this nanotube element can be applied between a plurality of electronic states of corresponding a plurality of electric stimulations of this first and second conducting terminal in response to this control circuit and switch, and wherein for each different electronic state of a plurality of electronic states, this nanotube element provides the power path that has corresponding different resistance between this first and second conducting terminal.

One or more embodiment comprise one or more following features.This first conducting terminal also is placed in and covers in fact at least one side in individual many sides of this nanotube element.This first conducting terminal also is placed in and covers in fact these a plurality of sides.One insulator layer contacts with the bottom surface of this nanotube element, and this insulator layer and this second conducting terminal cover the whole bottom surface of this nanotube element in fact together.Contacting one of at least of one insulator layer and one of the bottom surface of this nanotube element and side of this nanotube element.This insulator layer comprise SiO2, SiN and Al2O3 one of them.One passivation layer covers this first conducting terminal at least, and this passivation layer makes this first and second conducting terminal and this nanotube element to environmental sealing in fact.This passivation layer comprises SiO ₂, SiN, Al ₂O ₃, polyimides, phosphosilicate glass oxide, polyethylene fluoride, polypropylene carbonate and polybutene carbonate one of them.This second conducting terminal contacts the whole bottom surface of this nanotube element in fact.This first and second conducting terminal comprises the conductive material that independently is selected from by the following group that constitutes separately, comprises Ru, Ti, Cr, Al, Al (Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu, TiPd, PbIn, TiW, RuN, RuO, TiN, TaN, CoSi _xAnd TiSi _x

Down, clad nano pipe switch comprises: (a) comprise the nanotube element of unjustified a plurality of nanotubes, this nanotube element has end face and bottom surface on the other hand; (b) first and second conducting terminal that contacts and be spaced apart from each other with this nanotube element; (c) first insulator layer that contacts with the end face of this nanotube element; (d) second insulator layer that contacts with the bottom surface of this nanotube element, wherein this first and second conducting terminal with this first and second insulator layer in fact around this nanotube element; And (e) control circuit and this first and second conducting terminal electric connection also can apply electro photoluminescence to it, wherein this nanotube element can switch between a plurality of electronic states to corresponding a plurality of electro photoluminescence that this first and second conducting terminal applies in response to this control circuit, and wherein for each different electronic state of a plurality of electronic states, this nanotube element provides the power path that has corresponding different resistance between this first and second conducting terminal.

One or more embodiment comprise one or more following features.The end face of this first insulator layer of at least a portion and this nanotube element is separated a gap.A gap is separated in the bottom surface of this second insulator layer of at least a portion and this nanotube element.This first and second conducting terminal contacts the bottom surface of this nanotube element, and wherein this first insulator layer contacts with the whole top of this nanotube element.This first and second conducting terminal contacts the end face of this nanotube element.This first conducting terminal contacts the bottom surface of this nanotube element, and this second conducting terminal contacts the end face of this nanotube element.This first and second insulator layer comprises the insulating materials that independently is selected from by the following group that constitutes separately, comprises SiO ₂, SiN and Al ₂O ₃This first and second conducting terminal comprises the conductive material that independently is selected from by the following group that constitutes separately, comprises Ru, Ti, Cr, Al, Al (Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu, TiPd, PbIn, TiW, RuN, RuO, TiN, TaN, CoSi _xAnd TiSi _x

Under aspect another, clad nano pipe switch comprises: (a) comprise the nanotube element of unjustified a plurality of nanotubes, this nanotube element has end face and bottom surface; (b) first and second conducting terminal that contacts and be spaced apart from each other with this nanotube element; (c) first insulator layer places on the end face of this nanotube element and spaced away; (d) second insulator layer places under the bottom surface of this nanotube element and spaced away, wherein this first and second conducting terminal with this first and second insulator layer in fact around this nanotube element; And (e) control circuit and this first and second conducting terminal electric connection also can apply electro photoluminescence to it, wherein this nanotube element can switch between a plurality of electronic states to corresponding a plurality of electric stimulations that this first and second conducting terminal applies in response to this control circuit, and wherein for each different electronic state of a plurality of electronic states, this nanotube element provides the power path with corresponding different resistance between this first and second conducting terminal.

One or more embodiment comprise one or more following features.This first and second insulator layer comprises the insulating materials that independently is selected from by the following group that constitutes separately, comprises SiO ₂, SiN and Al ₂O ₃This first and second conducting terminal comprises the conductive material that independently is selected from by the following group that constitutes separately, comprises Ru, Ti, Cr, Al, Al (Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu, TiPd, PbIn, TiW, RuN, RuO, TiN, TaN, CoSix and TiSix.

The accompanying drawing summary

In the accompanying drawings:

Figure 1A-1C is the sub-Nonvolatile nanotube switch of both-end (NVNT switch) of each end tool bottom contact position, and the perspective view of the embodiment of tool combination top/side and bottom contact position and the sub-nonvolatile nanotube blocks switch of the both-end of another tool top and bottom contact position (NV NT block switch).

Fig. 2 A illustrates the embodiment that is in level orientation in fact, has the NV NT switch of two bottom contact terminals that are positioned at graphical nanotube channel assembly opposite end separately.

Fig. 2 B illustrates the SEM view of the exemplary Nonvolatile nanotube switch of the Nonvolatile nanotube switch embodiment that is similar to shown in Fig. 2 A.

Fig. 2 C illustrates the result of the loop-around data of the exemplary Nonvolatile nanotube switch that is similar to Fig. 2 B.

Fig. 3 illustrates and is in the embodiment of NV NT switch that level orientation, tool are positioned at two bottom contact terminals of graphical nanotube channel assembly opposite end separately in fact, and wherein the switch channel length is less than the interval between the contact terminal.

Fig. 4 A illustrates the embodiment with the sub-NV NT of the both-end block switch that mixes vertical and level orientation, it has to the bottom contact terminal of nonvolatile nanotube blocks (NV NT block), and to the combination top and the side contact terminal that extend horizontally to the NV NT block of the second bottom contact terminal in fact.

Fig. 4 B illustrates the result of the loop-around data of the exemplary nonvolatile nanotube blocks switch that is similar to Fig. 4 B.

Fig. 5 A illustrates the embodiment of the sub-NV NT of a pair of both-end block switch with vertical orientations, and it has to the bottom contact terminal and the top contact terminal of nonvolatile nanotube blocks (NV NT block).

Fig. 5 B illustrates the result of the loop-around data of the exemplary nonvolatile nanotube blocks switch that is similar to Fig. 5 A.

Fig. 6 A illustrates the NV NT switch embodiment of Fig. 2 A that has added a passivation layer.

Fig. 6 B illustrates the NV NT switch embodiment of Fig. 2 A that has added two passivation layers.

Fig. 6 C illustrates the NV NT switch embodiment that has added a passivation layer and added Fig. 2 A of an interstitial area on graphical nanotube assembly.

Fig. 6 D illustrates the NV NT switch embodiment that has added a passivation layer and added Fig. 2 A of interstitial area under reaching on the graphical nanotube assembly.

Fig. 7 A illustrates the NV NT switch embodiment of the Fig. 3 that has added a passivation layer.

Fig. 7 B illustrates the NV NT switch embodiment that has added a passivation layer and added Fig. 3 of an interstitial area on the channel length part of graphical nanotube assembly.

Fig. 8 A illustrates the NV NT block switch embodiment of Fig. 4 A that has added a passivation layer.

Fig. 8 B illustrates and has added the NV NT block switch embodiment that a passivation layer and the adjacent side face in the nonvolatile nanotube blocks district have added Fig. 4 A of an interstitial area.

Fig. 8 C illustrates the embodiment of the sub-NV NT of a pair of both-end block switch with vertical orientations, it has to the bottom contact terminal and the top contact terminal of nonvolatile nanotube blocks (NV NT block), and wherein this top contact terminal is extended all sides with the contact nonvolatile nanotube blocks.

Fig. 8 D is the conclusion of the embodiment of NV NT switch described in Fig. 2 A-8C and NV NT block switch, and it can be used as the Nonvolatile nanotube memory node in the memory array cell.

The embodiment of the schematically illustrated memory element of Fig. 9 A, it can use Nonvolatile nanotube switch or the nonvolatile nanotube blocks switch Nonvolatile nanotube memory node as the memory element unit.

Fig. 9 B illustrates the layout of the embodiment of 16 bit memory arrays, and it comprises that NMOS FET selects transistor and cmos buffer device and control circuit.

Figure 10 A shows the top SEM figure corresponding to 16 bit memory array area of the example assembled of Fig. 9 B layout, and shows the Nonvolatile nanotube memory node that uses the nonvolatile nanotube blocks switch to form.

Figure 10 B shows the inclination angle SEM figure of one of exemplary nonvolatile nanotube blocks switch shown in Figure 10 A.

Figure 11 A shows and to write 0 and write the test result of 1 storage operation to what the exemplary 16 bit memory arrays shown in Fig. 9 A-10B were carried out.

What Figure 11 B showed each bit (unit) position in the exemplary 16 bit memory arrays shown in Fig. 9 A-10B writes 0 and write the schmoo figure of 1 operating voltage.

What Figure 11 C showed each bit (unit) position in the exemplary 16 bit memory arrays shown in Fig. 9 A-10B writes 0 and write another schmoo figure of 1 operating voltage.

Figure 12 A illustrates to have as the Nonvolatile nanotube memory node and is formed at the vertical view of the embodiment of four memory array cells on the end face of cellular zone.

Figure 12 B illustrates the sectional view of the memory array cell embodiment shown in Figure 12 A.

Figure 13 A illustrates as the Nonvolatile nanotube memory node and is formed on the end face of cellular zone, has the vertical view of embodiment of four memory array cells of top/side and bottom contact terminal type nonvolatile nanotube blocks switch.

Figure 13 B illustrates the sectional view of the memory array cell embodiment shown in Figure 13 A.

Figure 14 A illustrates as the Nonvolatile nanotube memory node and is formed on the end face of cellular zone, has the vertical view of embodiment of four memory array cells of top and bottom contact terminal type nonvolatile nanotube blocks switch.

Figure 14 B illustrates the sectional view of the memory array cell embodiment shown in Figure 14 A.

Figure 15 illustrates as the Nonvolatile nanotube memory node and is formed on the end face of cellular zone, has the sectional view of embodiment of the memory array cell of top and bottom contact terminal type sealing nonvolatile nanotube blocks switch.

Figure 16 A illustrates as the Nonvolatile nanotube memory node and includes the vertical view of embodiment of four memory array cells of and cellular zone under bit line adjacent with corresponding selection transistor in.

Figure 16 B illustrates the sectional view of the memory array cell embodiment shown in Figure 16 A.

Figure 17 A illustrates as the Nonvolatile nanotube memory node and includes the vertical view of the embodiment of and four memory array cells cellular zone, that have top/side and bottom contact terminal type nonvolatile nanotube blocks switch under bit line adjacent with corresponding selection transistor in.

Figure 17 B illustrates the sectional view of the memory array cell embodiment shown in Figure 17 A.

Figure 18 A illustrates as the Nonvolatile nanotube storage node and includes the vertical view of the embodiment of and four memory array cells cellular zone, that have top and bottom contact terminal type nonvolatile nanotube blocks switch under bit line adjacent with corresponding selection transistor in.

Figure 18 B illustrates the sectional view of the memory array cell embodiment shown in Figure 18 A.

Figure 19 illustrates as the Nonvolatile nanotube memory node and includes the sectional view of the embodiment of memory array cell and cellular zone under bit line adjacent with corresponding selection transistor, that have top and bottom contact terminal type sealing nonvolatile nanotube blocks switch in.

Figure 20 A illustrates as the Nonvolatile nanotube memory node and includes the sectional view of the embodiment of and memory array cell cellular zone, that have top and bottom contact terminal type nonvolatile nanotube blocks switch bit line contact and corresponding selection transistor drain between adjacent with corresponding selection transistor in.

Figure 20 B show according to some embodiment because of becoming in the comparison in the estimation unit zone of the type of selected Nonvolatile nanotube memory node and employed integrating device.

Figure 21 illustrates that use is in level orientation and the tool first central area contact terminal in fact and around the sectional view of the embodiment of the formed cross point switches of Nonvolatile nanotube switch of second " picture frame " contact terminal of this first contact.

Figure 22 A-22C illustrates plane and two respective cross-section figure of the embodiment that uses first kind top and the formed cross point switches of bottom contact terminal nonvolatile nanotube blocks switch.

Figure 22 D shows that the circuit of the non-volatile electric programming that various ON (conducting) and the OFF (ending) corresponding to the nonvolatile nanotube blocks switch shown in Figure 22 A-22C makes up is by the embodiment that connects.

Figure 23 A-23C illustrates plane and two respective cross-section figure of the embodiment that uses the second class top and the formed cross point switches of bottom contact terminal nonvolatile nanotube blocks switch.

Specifically describe

Each embodiment of the present invention provides memory element and cross point switches and the array thereof that uses nonvolatile nanotube blocks.This memory cell and cross point switches comprise two-terminal nanotube switches, and it comprises the nanotube element such as nanotube blocks with the sub-electric connection of both-end.These switches can repeat to switch between first and second state in response to the electro photoluminescence at this both-end place, and thereby can the storing memory state or provide Reprogrammable to be electrically connected.Compare the relatively nanotube films of thin (for example 0.5-10nm), the memory and the cross point switches array of relative higher density made in the use of nanotube " block ".

Some embodiment provide the 3-D cellular construction of 2-D cellular construction and enhancing, and it allows to comprise the intensive nonvolatile memory array of the sub-Nonvolatile nanotube memory node of both-end.This node comprises 2-D nanotube switch that is called Nonvolatile nanotube switch (NV NT switch) and/or the 3-D nanotube switch that is called nonvolatile nanotube blocks switch (NV NT block switch).This node also comprises the corresponding selection transistor such as NMOS FET (NFET), and logical one and 0 state that it can write a plurality of cycles read stored logic state and keep logic state and need not to apply electric power to memory node.The scalable one-tenth large memories of some embodiment array structure, and/or make compatible with cmos circuit.As some embodiment during with the combination of NMOS FET and CNT, it should be noted the duality principle in the based semiconductor device, PMOS FET can replace NMOS FET, also correspondingly changes together with the polarity of providing voltage.Should also be noted that the operation of both-end NV NT switch and NV NT block switch is irrelevant with the sense of current of this nanotube of flowing through, and irrelevant with the polarity of the voltage of each end points (terminal) that is applied to this nanotube.What should further note is that alternative NMOS or PFETFET select transistor to use the CMOS selector that comprises NFET and PFET device.

Can use 3-D NV NT block switch as the Nonvolatile nanotube memory node in the memory cell, and as the non-volatile cross point switches in the cross point switch matrix application.In certain embodiments, as in the U.S. Patent application No. (to be arranged) that is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " (" Nonvolatile Nanotube Diodes andNonvolatile Nanotube Blocks and Systems Using Same and Methods ofMaking Same ") that submits to simultaneously with the application in greater detail, can be as small as F * F at each side NV NT block switch, wherein F is the minimum technology node size.

It should be noted that the nonvolatile memory array based on nanotube also can be configured to be in the NAND and the NOR array of PLA, FPGA and PLD configuration, and also can use in the cross point switch matrix non-volatile cross point switches layout line route based on nanotube.Field programmable logic can use the combination based on the nonvolatile memory array of nanotube and cross point switch matrix repeatedly to reconfigure, to form logic function independent and that embed.

The NV NT switch of 2 dimension (2-D) horizontal alignments and 3 dimension (3-D) NV NT block switch

The example of the sub-2-D Nonvolatile nanotube of both-end switch (NV NT switch) and the sub-3-D nonvolatile nanotube blocks of both-end switch (NV NT block switch) is described in respective drawings, and concludes in Fig. 8 D, and it will be further elucidated hereinbelow.For ease of integrated, NV NT switch or NV NT block switch can be formed on the end face of memory array or near, or as described below, for high density (little overlay area) can form near the unit selecting transistor.

For ease of integrated, memory cell can be used has end face or near NV NT switch or the Nonvolatile nanotube memory node of NV NT block switch of formation (manufacturing) on the memory cell of distribution in fact in advance, wherein selects transistor (typically being NFET) to be connected to array word line (WL) and bit line (BL).One binding post selects transistorized source electrode to interconnect to the first terminal of NV NT switch or NV NT block switch NFET, and second terminal is connected to the reference array line that is also referred to as auxiliary word lines (WWL) simultaneously.

Because almost required all growth, deposition and the etching step of semiconductor structure all nanotube deposition and graphical before finish, to be convenient to nanotube switch integrated so be positioned at the end face of memory array or near NV NT switch or NV NT block switch.Because memory array can be pre-formed in the stage that nanotube switch only need form routinely to finish manufacturing, so the integrated nanometer pipe switch structure allows quick sample to prepare when the manufacturing cycle will stop.Yet, in certain embodiments, memory cell region is in the minimum dimension of can be in fact on the area using particular technology node F to make greater than (50 to 100% or more than), for example in each embodiment, bit line (BL) is placed in contiguous NFET selector, but not place on the selector, be connected with the binding post of enabling between the respective switch terminal of NFET on selecting transistorized source electrode and placing integrated morphology neutrality line array.

Being positioned at the end face of memory array or near NV NT switch or NV NT block switch can be passivated, and sealably encloses in the encapsulation, under typical situation test and assessment to the tolerance of the harsh and unforgiving environments of for example high temperature and high radiation.The example of unpassivated switch following Fig. 2 A, 3 and 4A shown in.

Be positioned at the end face of memory array or near NV NT switch or NV NT block switch and can be passive state, and use conventional packaging system encapsulation.The tolerance to the harsh and unforgiving environments of for example high temperature and high radiation can be tested and assess to this packaged chip through passivation under typical situation.Through the example of passivation switch shown in following Fig. 5 A, 6A-6D, 7A-7B, the 8A-8C.

Through the NV of passivation NT switch or NV NT block switch also can be integrated in NFET select near the transistor, under the bit line, to realize intensive memory cell.For example the NV NT block switch of band top shown in Fig. 5 A and bottom contact for example can be integrated into that density is 6-8F ²Memory cell, wherein F is the minimum technology node.As described in more detail below, memory cell size (overlay area) assessment is described in Figure 20 B based on the nanotube switch of concluding among Fig. 8 D.

2-D NV NT switch and 3D NV NT block switch structure

Figure 1A-1C illustrates has the thin Nonvolatile nanotube element (NV NT element) of different contact positions and the perspective view that is called the volatibility nanotube element of being altogether unjustifiable of nonvolatile nanotube blocks (NV NT block).Shown in Figure 1A-1C, NV NT element and contact be combined to form 2 dimension (2-D) NV NT switches, and NV NT block and contact be combined to form 3 dimension (3-D) NV NT block switch.As described below, for making advantage and more intensive memory cell and cross point switches array, can use 3-D NV NT block switch to substitute NV NT switch as Nonvolatile nanotube memory node in the memory array cell (NV NT memory node) and cross point switches.NV NT switch shown in Figure 1A-1C and NV NT block switch are the exemplary subset of possible switch configuration, its some embodiment description in the U.S. Patent application No. (to be arranged) that is entitled as " using Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system and manufacture method " (" Nonvolatile NanotubeDiodes and Nonvolatile Nanotube Blocks and Systems Using Same andMethods of Making Same ") that for example submits to simultaneously with the application.

NV NT switch 1000A among Figure 1A shown in the perspective view shows to have relatively the Nonvolatile nanotube element 1005 of thin (below for example about 0.5nm to 10nm) and the NV NT switch of bottom contact position 1010 and 1015.As further described below and U.S. Patent application No.11/280, described in 786, the position on contact position explanation terminal (not shown) contact nanometer tube elements 1005 surfaces.

NV NT block switch 1000B among Figure 1B shown in the perspective view shows and has NV NT block 1020 the NV NT block switch of (for example typically be 10nm or greater than arbitrary specific dimensions), and this NV NT block 1020 has bottom contact position 1030 and comprises top contact position 1025-2 and the top of side contact position 1025-1/side contact position 1025.The edge of bottom contact position 1030 and side contact position 1025-1 is separated by overlap distance LOL.Describe among the U.S. Patent application No. (to be arranged) as described below and that being entitled as of submitting to simultaneously " use Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system and manufacture method " with the application, contact position illustrates that the terminal (not shown) contacts the position on NV NT block 1020 surfaces.

NV NT block switch 1000C among Fig. 1 C shown in the perspective view shows and has NV NT block 1035 the NV NT block switch of (for example typically be 10nm or greater than arbitrary specific dimensions), and this NV NT block 1035 has bottom contact position 1040 and top contact position 1045.As described below and submit and be entitled as description among the U.S. Patent application No. (to be arranged) of " using Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system and manufacture method " simultaneously to the application, contact position illustrates the position that the terminal (not shown) contacts NV NT block 1035 surfaces.With respect to other embodiment of 3-D NVNT block switch and 2-D NV NT switch, 3-D NV NT block switch 1000C occupies less relatively zone (having less relatively overlay area).

Be listed in the NV NT switch 1000A shown in Fig. 2 A down corresponding to NV NT switch 2000, wherein nanotube element 1005A is corresponding to nanotube element 2035, contact position 1010 is corresponding to the position of contact terminal 2010, and contact position 1015 is corresponding to the position of contact terminal 2015.

As U.S. Patent application No.11/280, in 786 more detailed description ground, and Fig. 2 A illustrates the NV NT switch 2000 that comprises graphical nanotube element 2035 on the insulator 2030, and it is positioned at the surface of combined insulation body and wiring layer 2020, and it is supported by substrate 2025.Graphical nanotube element 2035 is the nanostructureds on the plane, and overlaps with 2015 with terminal (conducting element) 2010 and contact.Contact terminal 2010 and 2015 deposition before graphical nanotube blocks 2035 forms also directly is patterned on the combined insulation body and wiring layer 2020 that is positioned on the substrate 2025.Nonvolatile nanotube switch channel length L _SW-CHIt is the spacing between contact terminal 2010 and 2015.Substrate 2025 can be insulator, semiconductor or organic rigid or a flexible substrate for example pottery or glass.Substrate 2025 also can be organically, and can be flexible or rigidity.Insulator 2020 and 2030 can be SiO ₂, SiN, Al ₂O ₃, or other insulating material.Terminal 2010 and 2015 can use all kinds of contacts and interconnection base metal to form, for example Ru, Ti, Cr, Al, Al (Cu), Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and metal alloy, for example TiAu, TiCu, TiPd, PbIn and TiW, the conductor that other is suitable, or conductive nitride, oxide or silicide, for example RuN, RuO, TiN, TaN, CoSi _xAnd TiSi _x

As U.S. Patent application No.11/280, describe in detail more in 786, Fig. 2 B illustrate Nonvolatile nanotube switch 2000 before the passivation ' SEM figure, and corresponding to the Nonvolatile nanotube switch 2000 in Fig. 2 A sectional view.Nonvolatile nanotube switch 2000 ' comprise nanostructured elements 2035 ', correspond respectively to the contact terminal 2010 of contact terminal 2010 and 2015 ' and 2015 ', and corresponding to the insulator 2020 of insulator and wiring layer 2020 '.As U.S. Patent application No.11/280, describe in detail more in 786, although can use other suitable channel length, such as switch 2000 ' exemplary volatibility nanotube switch made the channel length L that scope is 250nm to 22nm _{Raceway groove}, reduce the Nonvolatile nanotube switch size thus and reduce program voltage.

As U.S. Patent application No.11/280, describe in detail more in 786, the laboratory tests of single Nonvolatile nanotube switch illustrate the Nonvolatile nanotube switch of switch 2000 shown in Fig. 2 A sectional view, and corresponding to the switch of NV NT shown in Fig. 2 B 2000 ' the SEM micrograph, circulating between ON and OFF resistance states shown in Figure 20 50 among Fig. 2 C exceedes 5,000 ten thousand times.Conducting (ON) state resistance typically is in 10k ohm to 50k ohm, typically exceeds 1G ohm by (OFF) state resistance simultaneously, conducting with end resistance value between (ON and OFF) on off state differential greater than five orders of magnitude arranged.As U.S. Patent application No.11/280, described in 786, the test than the single Nonvolatile nanotube switch of short channel length with 50nm has for example caused lower writing 0 and write 1 voltage level, such as the 4-5 volt but not 8 to 10 volts.

Fig. 3 illustrates NV NT switch 3000, it is the variant of the NV NT switch 2000 shown in Fig. 2 A, comprise the graphical nanotube element 3045 that supports and be in contact with it with 3015 by contact terminal 3010, extend 3040, reach insulator 3035 with terminal 3010 physics and the electric contact terminal that contacts.Insulator 3042 is finished this complanation structure, but does not contact with graphical nanotube element 3045 usually.NV NT switch 3000 has probably the overall dimensions identical with NV NT switch 2000, its difference be insulator 3030 and 3035 and the contact terminal 3040 that extends use known preferable manufacture method to be added into basic NV NT switch 2000 structures, be reduced to the shorter L shown in Fig. 3 with channel length with NV NT switch 3000 _SW-CHAs U.S. Patent application No.11/280, described in 786, because L _SW-CHLength can be in for example 5 to 50nm length range, so shorter L _SW-CHChannel length can reduce the operating voltage of NV NT switch 3000, and simultaneously contact terminal 3010 and 3015 for example can separate 150 to 250nm.The prior art USP 4,256 incorporated herein by reference as full content, described in 514, L _SW-CHLength partly determines according to the thickness of insulator 3035, and this insulator 3035 is to use known preferable sidewall spacer method to be deposited on the upper area that is exposed of contact terminal 3010 and 3015.The end face 3030 of insulator 3030 ' and the coplane end face of contact terminal 3010 and 3015 between, the contact terminal 3010 and 3015 the upper area that is exposed can be in for example 10 to 500nm scope.The end face 3030 of insulator 3030 ' can by with insulator 3030 optionally directional etch become the preferable industry method of desired depth under the end face of coplanar contacts terminal 3010 and 3015 to form.Insulator 3030 and contact terminal 3010,3030 contact with insulator and wiring layer 3020 on the substrate 3025.

Insulator 3035 uses known preferable industry method to be deposited as corresponding to required switch channel length L _SW-CHThickness, such as 5 to 50nm, and then use preferred approach graphical.

Then, the prior art USP 4,944 incorporated herein by reference as full content, described in 836, use preferred approach to deposit a conductor layer, and the preferred approach of for example chemically mechanical polishing (CMP) is applied to combined insulation body and conductor layer.This moment in this is handled, L _SW-CHBe restricted to as shown in Figure 3, also limit contact terminal 3015 and extend 3040 contact terminals that contact 3010 with contact terminal.

Then, insulator 3042 uses the preferred approach of deposition and complanation and forms.Then, as described in the patent application of being included in, use the graphical nanotube element 3045 of preferred approach.

Substrate 3025 can be insulator, semiconductor or organic rigid or a flexible substrate for example pottery or glass.Substrate 3025 also can be organically, and can be flexible or

rigidity.Insulator

3020,3030,3035 and 3042 can be SiO ₂, SiN, Al ₂O ₃, or other insulating

material.Contact terminal

3010,3015 and contact terminal extend 3040 and can use all kinds of contacts and interconnection base metal to form, for example Ru, Ti, Cr, Al, Al (Cu), Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and metal alloy, for example TiAu, TiCu, TiPd, PbIn and TiW, the conductor that other is suitable, or conductive nitride, oxide or silicide, for example RuN, RuO, TiN, TaN, CoSi _xAnd TiSi _x

NV NT switch

2000 and 3000 is illustrated as not having the insulating protective layer of covering.If NV NT switch is formed on the top layer of semiconductor chip, chip operation just need not insulate so.Yet chip is installed in the sealed package usually, to guarantee protecting and exempt from environmental pollution and moisture attack in the mechanical handling process.If NV NT switch is incorporated near the Semiconductor substrate place, or does not give sealing, so as further described, can use dielectric protection layer NV NT switch with reference to Fig. 5 A, 6A-6D, 7A, 7B and 8A-8C.

As among the U.S. Provisional Patent Application No. (to be arranged) that is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " that submits to simultaneously with the application in greater detail, Fig. 4 A illustrates the NV NT block switch 4000 corresponding to the NV of 3-D shown in Figure 1B NT block switch 1000B.Switch 4000 occupies probably the zone identical with NV NT switch 2000 and 3000.NV NT block switch 4000 also is characterized by NV NT overlapping block length L _OL, it is determined according to the interval between the edge of bottom contact terminal 4015 and NV NT block 4035.NV NT block switch 4000 comprises that the side/top contact 4040 that is formed by contact, side 4040A and end face contact 4040B reaches the combination of the bottom contact 4042 that is formed by contact terminal 4015.Bottom contact 4042 is corresponding to the bottom contact position 1030 of the NV NT block switch 1000B shown in the perspective view of Figure 1B; Side/end face contact 4040 is corresponding to top/side contact position 1025; End face contact 4040B is corresponding to end face contact position 1025-2; Contact, side 4040A is corresponding to lateral location 1025-1; And NV NT block 4035 is corresponding to NV NT block 1020.Effective overlap length L _OLBe the distance between the edge of bottom contact 4042 and the side that the is discussed in further detail below/end face contact 4040.Contact terminal 4010 connects side/end face contact 4040 by conductor 4045.Can use preferable manufacture method to deposit simultaneously and patterned conductor 4045 and face contact 4040, form conductor/contact 4045/4040 interconnection mechanism of combination thus.Conductor/contact 4045/4040 that combination can be used in NV NT block side is as mask, the preferred approach of the expose portion by this nanotube blocks structure of directional etch and partly limiting.NV NT block 4035 sides 4043 (and both sides in addition of can't see among Fig. 4 A) are exposed.The method of etching of nano tubular construction layer is described in the patent documentation of being included in.

Before graphical nanotube blocks 4035 formed,

contact terminal

4010 and 4015 depositions also directly were patterned on the combined insulation body and wiring layer 2020 that is positioned on the substrate 4025.Substrate 4025 can be insulator, semiconductor or organic rigid or a flexible substrate for example pottery or glass.Substrate 4025 also can be organically, and can be flexible or

rigidity.Insulator

2020 and 4030 can be SiO ₂, SiN, Al ₂O ₃, or other insulating

material.Terminal

4010 and 4015 can use all kinds of contacts and interconnection base metal and forming, for example Ru, Ti, Cr, Al, Al (Cu), Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn, and metal alloy, for example TiAu, TiCu, TiPd, PbIn and TiW, the conductor that other is suitable, or conductive nitride, oxide or silicide, for example RuN, RuO, TiN, TaN, CoSi _xAnd TiSi _x

Being relevant to the Figure 45 00 shown in Fig. 4 B corresponding to the laboratory ON/OFF switch testing result of the exemplary nonvolatile nanotube blocks switch of NV NT block switch 4000 is described, wherein write 0 corresponding to wiping and produce high resistance OFF state, and write 1 corresponding to program and produce low resistance ON state.Test status and result describe in the patent documentation of being included in more detail.Figure 45 00 illustrates the result of electric test, wherein apply one 6 volts write 0 potential pulse, 6 volts write 1 potential pulse and measure the ON resistance in each ON/OFF cycle in 100 cycles.ON resistance value 4555 is in 120k ohm usually to 1M ohm scope, and OFF resistance value 4560 is generally more than 100M ohm, and maximum is more than 1G ohm.Under these two kinds of situations, ON resistance value 4565 expressions that surpass 1G ohm can't switch to the ON state.

As what further describe among the U.S. Patent application No. (to be arranged) that is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " that submits to simultaneously with the application, Fig. 5 A illustrates the control of 3-D diode to two of memory array identical memory cell, i.e. unit 1 and unit 2.Unit 1 (identical with unit 2) comprises steering diode 5010, and the one terminal contacts with NV NT block switch 5005 on the bottom contact terminal 5020, and another diode 5010 terminals contact with array routing conductor 5015.NV NT block switch 5005 top contact 5040 contact with array routing conductor 5050.NV NT block switch 5005 comprises the top contact 5040 that contacts with NV NT block 5030, and the bottom contact 5020 that contacts with NV NT block 5030.NV NT block switch 5005 is embedded in the dielectric 5060.Because being limited of the preferable manufacture method that further describes in the patent documentation that top and bottom contact and NV NT block 5030 sides can be passed through to be included in from align with grooves, and can be used for forming the minimum NV NT storage node size of F * F, so NV NT block switch 5005 quite intensive (occupying less relatively overlay area).Though NV NT block switch 5005 is illustrated as selecting with diode 5010 (control to) device to combine, but as below for example be relevant to and further describe among Figure 18 A-18C, NV NT block switch 5005 can with the combination of NFET selector to form the memory array of relative comparatively dense.

The NV NT block switch 1000C that further illustrates in the perspective view of above Fig. 1 C illustrates the NV NT block 1035 corresponding to the NV NT block 5030 shown in Fig. 5 A.Bottom contact position 1040 is corresponding to bottom contact 5020, and top contact position 1045 is corresponding to top contact 5040.

The lateral dimension of NV NT block switch 5010 can be the same with minimum dimension F * F little.The lateral dimension of NV NT block 5030 can be greater than minimum dimension F; The lateral dimension of NV NT block 5030 need not equate.The minimum dimension F that vertical (thickness) size that also note that other NV NT block switch described in NV NT block switch 5010 and the literary composition also is not limited to technology node usually and is provided.On the contrary, vertically (thickness) size is relevant with the thickness of nano tube structure, as among the U.S. Patent application No. (to be arranged) that is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " that submits to simultaneously with the application in greater detail, it may be selected to be for example enough thick and forbids electric contact the between the contact 5020 and 5040 basically.The example of contact and conductor material comprises base metal, for example Al, Au, W, Ta, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloy, for example TiAu, TiCu, TiPd, PbIn and TiW, the conductor that other is fit to, or the conductive nitride of TiN for example, oxide or silicide, for example RuN, RuO, TiN, TaN, CoSi _xAnd TiSi _xInsulator can be SiO ₂, SiN, Al ₂O ₃, or other insulating material.

Being relevant to the Figure 50 70 shown in Fig. 5 B corresponding to the laboratory ON/OFF switch testing result of the nonvolatile nanotube blocks switch of NV NT block switch 5000 is described, wherein write 0 corresponding to wiping and produce high resistance OFF state, and write 1 corresponding to program and produce low resistance ON state.Test status and result describe in the patent documentation of being included in more detail.Figure 50 70 illustrates the result of electric test, its apply one 6 volts write 0 potential pulse, 6 volts write 1 potential pulse and measure the ON resistance in each ON/OFF cycle in 100 cycles.ON resistance value 5075 is in 120k ohm usually to 1M ohm scope, and OFF resistance value 5080 is generally more than 100M ohm, and maximum is more than 1G ohm.

Be applied to the insulator of 2-D NV NT switch and 3D NV NT block switch structure

Some embodiment of NV NT switch and NV NT block switch can form on the end face of chip, and do not use insulator and be packaged in the environment of sealing.During when nanotube element deposition and graphically in the end face of coplanar contacts terminal and insulator, more than be relevant to the nonisulated NV NT switch that Fig. 2 A and 3 for example further illustrates and form.The example of insulation NV NT switch and NV NT block switch further specifies hereinafter.

Chip for NV NT switch with the non-hermetic environments of being packaged in can add one or more insulator layers to NV NT construction of switch.And for the memory cell of for example comparatively dense, NV NT switch can be combined near the unit selecting transistor of NFET for example, and it is near silicon substrate and under bit line array lines for example.Thereby a plurality of insulating barriers can be used for being combined on the NV NT switch in some memory array organizations.Insulator can with the nanotube element alternately to change the electric attribute of NV NT switch, for example required voltage threshold and the current value of switch.Some insulators can promote electrical characteristic by reducing threshold voltage and electric current.The example of NV NT switch insulation body method further illustrates at the following Fig. 5 of being relevant to A, 6A-6D, 7A, 7B and 8A-8C.Under some situations, add one or more insulating barriers and can comprise the one or more additional mask layer of use.

As shown in Figure 1B and 1C and Fig. 4 A and 5A, some embodiment of NV NT block switch can make the top contact to conductor, make insulator not contact with the end face of NV NT block structure.Yet insulator can contact with some sidewall surfaces of the NV NT block switch structure shown in Fig. 4 A and the 5A.NV NT block switch is operated with various contact configurations, the for example top and bottom shown in Fig. 4 A-4B and the 5A-5B and top/side and bottom contact, and other contact configurations, for example only end points, end points and contact, side, and further illustrative other contact option in the patent documentation of being included in.

Be relevant to Fig. 8 C and further illustrative as following, some embodiment of NV NT block switch can have on five faces to six faces the only contact of conductor (naked body), and the sub-fraction of only remaining bottom NVNT block areas coats or the NV NT block switch of sealing (covering) and contacting with insulator under it by forming.Because the sensitiveness of nanotube electrical characteristic is reduced to that integrated circuit is handled and structure in general various insulator, NV NT block switch can be more easily integrated on each assembled layers compared to NV NT switch and other (sealing) for the NV NT block switch of this coating or sealing.In other words, the NV NT block switch that coats or seal can be compatible with the insulator of the broad range that is used for the integrated circuit manufacturing.Yet, in certain embodiments, as shown in Figure 5A, coat or the NV NT block switch of sealing can more not intensive (having big overlay area) compared to the NV NT block switch 5000 with top and bottom contact.

Fig. 6 A illustrates by insulator 6010 being added into the insulation NV NT switch 6000 that the NV NT switch 2000 shown in Fig. 2 A forms.Graphical nanotube element 2035 can contact with its lower insulator 2030, and covers insulator 6010.As what further describe in following and the patent documentation included in, preferable passivation layer can be used as the

insulator

6010 and 2030 in the NV NT switch 6000.

Passivation layer can have some or all Column Properties down.The first, this passivation layer can form effective moisture barrier, avoids nanotube to be exposed to water in fact.The second, this passivating film can not disturb, and preferably promotes the switching mechanism of storage arrangement.The 3rd, this passivating film can with other insulator that is relevant to the preferred process flow process that is used to form integrated morphology, conductor and semiconductor compatibility.

Passivation layer can be formed by arbitrary suitable material known in the CMOS industry, includes but not limited to: SiO ₂, SiN, Al ₂O ₃, polyimides, and other insulating materials, for example CVD (chemical vapor deposition), ALD (ald) oxide of PSG (phosphosilicate glass) oxide, LTO (complanation low temperature oxide) oxide, sputter oxide or nitride, flow fill oxide, oxide and nitride.Also can use PVDF (polyethylene fluoride) insulating materials.Also can use the combination of these insulators or other suitable insulator.

Also can use deposition and graphically be dissolved in the NMP of industry Nei Kede for example or the preferred approach of the sacrifice polymer poly propylene carbonate (PPC) of one or more organic solvents of cyclohexane forms insulator 6010 and 2030.For example can (Empower Materials Inc.) can find description to the attribute of polypropylene carbonate in the reference technique data of Huo Deing from En Baowa Materials Co., Ltd.Also can use for example Unity ^TMOther sacrifice property polymer of sacrifice property polymer and polybutene carbonate sacrifice property polymer.Relevant Unity ^TMThe information of polymer can obtain from supplier BFGoodrich, Cleveland, Ohio place.The use of sacrifice property polymer further describes in the patent documentation of being included in.As what further describe in the patent documentation of being included in, these materials also can be used for combining with other material, promptly have for example SiO ₂The PPC or the Unity of insulator ^TMPolymer.

Fig. 6 B illustrate by the insulator 6025 that will contact, the insulator 6030 that contacts with insulator 6025, contact terminal 2010 with

graphical nanotube element

2035 and 2015 and SI semi-insulation body 2030 be added into the insulation NV NT switch 6020 that the NV NT switch 2000 shown in Fig. 2 A forms.Insulator 6025 can be by applying above-mentioned for example PPC and Unity the preferred approach of sacrifice polymer form.Insulator 6030 can be by applying for example SiO ₂Insulator preferred approach and form.

Fig. 6 C illustrates the insulation NV NT switch 6040 corresponding to NV NT switch 6020.Yet when forming NV NT switch 6040, the insulator 6025 that is used for NV NT switch 6020 can use via the sacrifice polymer of for example above-mentioned PPC of insulating barrier evaporation or Unity and form.Fig. 6 C illustrates NV NT switch 6040 after sacrifice property polymer insulator 6025 is via insulating barrier 6050 (for example SiO2) evaporation, as in the patent documentation of being included in greater detail, on graphical nanotube element 2035, form interstitial area 6045.

Fig. 6 D illustrates insulation NV NT switch 6060, and it is corresponding to NV NT switch 6040.Yet, embed under the graphical nanotube element 2035 the sacrifice insulator (not shown) in the insulator 6070 by insulator 6050 evaporations, on graphical nanotube element 2035, producing interstitial area 6065, and under nanotube element 2035, produce interstitial area 6065 '.The feature of strengthening the property with NV NT switch of the graphical nanotube element that contains interstitial area further describes in the patent documentation of being included in.

Fig. 7 A illustrates by insulator 7010 being added into having from aliging the raceway groove length L that the NV NT switch 3000 shown in Fig. 3 forms _SW-CHInsulation NV NT switch 7000.Graphical nanotube element 3045

contacts contact terminal

3010 and 3015, contact terminal extension 3040 and the insulator 3035 under it.Graphical nanotube element 3045 also contacts the insulator 7010 on it.Passivation layer further describes above-mentioned and following reaching in the patent documentation of being included in.

Fig. 7 B illustrates insulation NV NT switch 7050, and it is corresponding to NV NT switch 7000.Yet sacrifice property insulator is by for example SiO ₂Insulator 7065 evaporations, to be positioned at L _SW-CHThe top of the graphical nanotube 3045 of the part on the district reaches at this L _SW-CHThe both sides of channel region extend to the top of graphical nanotube element 3045 and form gap 7060.The example of interstitial area is relevant to Fig. 6 A-6D and describes in more detail last addressing in the patent documentation of being included in.

Fig. 8 A illustrates insulation NV NT block switch 8000, and it is similar to the nonisulated NV NT block switch 4000 that further illustrates among above-mentioned Fig. 4 A.Can use insulation NV NT block switch 8000 in the memory cell, but not the NV NT switch shown in Fig. 6 A-6D and 7A and the 7B.NV NT block switch 8000 shown in Fig. 8 A forms by deposition insulator 8010 on the surface of NV NT block switch 4000, make insulator 8010 contact, comprise the be exposed side and the insulator 4030 of the side 4043 of 4040 districts, contact, for example NV NT block 4035 with conductor 4045.Because contact 4040B covered by conductor 4045, thus insulator 8010 contact with the end face of NV NT block 4035, and owing to contact 4040A is covered by conductor 4045, thus insulator 8010 also not with the contacts side surfaces of NV NT block 4035.Insulator 8010 materials can be to be similar to insulator 6010 materials that the above-mentioned Fig. 6 of being relevant to A further describes.

Before forming insulator 8030, the NV NT block switch 8020 shown in Fig. 8 B forms by comprising the sacrifice polyidal field that is similar to sacrificial region that the above-mentioned Fig. 6 of being relevant to A-6D and 7A-7B further describe.This sacrifice polyidal field can keep the insulator structure shown in further as above Fig. 6 B, and insulator evaporation that maybe can be by for example insulator 8030 is to form for example interstitial area shown in Fig. 6 C and 6D.Interstitial area 8040 avoids insulator 8030 to contact with the exposed side 4043 of NV NT block 4035.Other NV NT block 4035 sides (can't see in Fig. 8 B) can comprise interstitial area, and it avoids the contacts side surfaces between NV NT block 4035 and the insulator 8030.Interstitial area and preferable manufacture method further describe in the above-mentioned Fig. 6 of being relevant to C, 6D and 7B and the patent documentation included in.

NV NT block switch has been shown as with various geometry and contact configurations electric operation (switching between ON and OFF state), the for example top and bottom shown in Fig. 4 A and the 5A and top/side and bottom contact, and other contact configurations, for example only end points, end points and contact, side and other operating of contacts are for example described in the U.S. Patent application No. (to be arranged) that is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " that submits to simultaneously with the application.For flexibility and easiness, be desirable with the next integrated NV NT block switch of mode that strengthens conductor contact point at the side/top/bottom surface (face) of NV NT block areas and reduce non-conductor (insulator) contact with the integrated NV NT block switch type configuration of the semiconductor process flow of the almost arbitrary layer (or other type) that is exposed to different materials and technology.Further describe as the following Fig. 8 of being relevant to C, the contact that only has conductor (naked body) on five faces in six NV NT block surfaces (face) of the feasible NV NT block switch that coats or seal of (for example sealing) NV NT block arrangement that coats or seal by conductor contact point, the sub-fraction on NV NT block surface, only remaining bottom contacts with the insulator under it, and is called overlap length L _OL

Fig. 8 C illustrates the sectional view of sealing (covering) NV NT block switch 8050, and it comprises the bottom contact terminal 8065 that contacts with insulator and wiring layer 8055, and this bottom contact terminal 8065 contacts with substrate 8060 again.The end face of bottom contact terminal 8065 and insulator 8070 coplanes.Bottom contact terminal 8065 contacts NV NT block 8075 on bottom contact 8067.NV NT block 8075 extends overlap distance L in all each sides under the surface of bottom contact 8067 _OL, and contact with the end face of insulator 8070.L _OLIt can be 5 to 100nm the order of magnitude for example.Further describe L as the above Fig. 3 of being relevant to _OLCan be as prior art USP 4,256, the known preferable sidewall spacer method of the use described in 514, in conjunction with as prior art USP 4, the preferred approach of for example chemically mechanical polishing (CMP) technology described in 944,836 is determined from alignment techniques by mask alignment or mat.

Conductor uses forming top/side contact terminal 8080 at end face and all side surrounding NV NT blocks 8075.The top section 8080A of top/side contact terminal 8080 forms top contact 8083 with the end face of NV NT block 8075.Preferable manufacture method can be when forming the sidewall surfaces of NV NT block 8075, and the top section 8080A that uses top/side contact terminal 8080 is as mask layer.Sidewall conductor region 8080B-1,8080B-2 and other sidewall region of top/side contact terminal 8080 be can't see in Fig. 8 C, can be by the conformal conductor layer of deposition, then as prior art USP4,256, the preferred approach of directional etch shown in 514 forms, to form sidewall conductor 8080B-1 and 8080B-2.Preferable directional etch method is removed the remainder of the face upper conductor material of insulator 8070.Sidewall conductor region 8080B-1 and 8080B-2 are formed up to the sidewall contact 8082-1 and the 8082-2 of the side of NV NT block 8075.

Preferred methods deposition insulator 8085.Then, preferred approach through hole 8087 is etched to the top section 8080A of top/side contact terminal 8080.Then, the preferred approach deposition is filled up the conductor layer of through hole 8087.Then, the preferred approach of for example CMP described in the patent documentation of being included in makes the surface planeization of the conductor 8090 of the end face 8080A that forms contact top/side contact terminal 8080.

In certain embodiments, the big twice overlap length of the comparable minimum dimension F of the size L of sealing NV NT block switch 8050 _OL(2L _OL) amount and the thickness of twice sidewall conductor 8080B-1 and 8080B-2.As example, if L _OLBe 5 to 50nm and sidewall conductor region 8080B-1 and 8080B-2 for for example 5 to 50nm, so in certain embodiments, the minimum dimension of sealing NV NT block switch 8050 sizes is that cross section F+20nm is to cross section F+200nm.

The example of contact and conductor material comprises base metal, for example Al, Au, W, Ta, Cu, Mo, Pd, Ni, Ru, Ti, Cr, Ag, In, Ir, Pb, Sn, and metal alloy, for example TiAu, TiCu, TiPd, PbIn and TiW, other suitable conductor or conductive nitride, TiN for example, oxide or silicide, for example RuN, RuO, TiN, TaN, CoSi _xAnd TiSi _xInsulator can be SiO ₂, SiN, Al ₂O ₃Or other insulating material.

For example be relevant to as following that Figure 19 further describes, sealing NV NT block switch 8050 can be in conjunction with the selection transistor of for example NFET to produce memory cell.

Be relevant to 2-D NV NT switch that Fig. 2 A-8C further describes and some embodiment of 3-DNV NT block switch more than Fig. 8 D concludes, it can be as following further described, as the Nonvolatile nanotube memory node in the memory array.The Nonvolatile nanotube memory node that is numbered 1-13 among Fig. 8 D is corresponding to 2-D and/or 3-D construction of switch, and comprises Short Description, switch number and corresponding figure number and integrated layer restriction (if any).Some embodiment of nonisulated switch can be restricted to only top placement, and some embodiment of insulated switch can place arbitrary integrated layer simultaneously, because insulation protection switch in subsequent processing steps.

Use memory cell and the array thereof of 3-D nonvolatile nanotube blocks switch as memory element

Some embodiment of NV NT switch and NV NT block switch can select transistor integrated to form non-volatile memory cells and array thereof with NFET.For asking integrated easiness, this nanotube switch can place on the end face that partly forms the unit that comprises the NFET selecting arrangement that connects word line (WL) and bit line (BL) or near it.

Further describe design, manufacturing and test sample 16 bit memory arrays as the following Fig. 9 of being relevant to A, 9B, 10A, 10B and 11A-11C.Be electrically connected corresponding NFET at the top layer of CMOS chip with a terminal and select transistorized source electrode and the nonisulated NV NT block switch 4000 shown in the shop drawings 4A, so that as described below finishing has the non-volatile 16 bit memory arrays of cmos buffer device circuit.

Below being relevant to Figure 12 A, 12B, 13A, 13B, 14A, 14B and 15 further describes and addresses the NV NT switch of concluding among Fig. 8 D and the various memory array cells of NV NT block switch in the use.These memory cell are used by the NV NT memory node that places memory cell surface or near word line and wiring in advance and the NV NT switch on the bit line layer and NV NT block switch to form.

Below being relevant to Figure 16 A, 16B, 17A, 17B, 18A, 18B and 19 further describes and addresses the NV NT switch of concluding among Fig. 8 D and the various memory array cells of NV NT block switch in the use.These memory cell use by in the unit of contiguous NFET selector the NV NT memory node that forms of integrated NV NT switch and NV NT block switch, the one terminal connects the transistorized source electrode of NFET and also is positioned under the bit line layer, with the raising cell density.

Figure 20 A illustrates the NV NT block switch memory node that is connected between bit line BL and the NFET transistor drain.This Integrated Solution is accomplished according to the density of NV NT block switch and the electric current bi-directional nature of NV NT block switch.

Figure 20 B illustrates the unit area (overlay area) of the various NV NT memory nodes that form with NV NT switch or NV NT block switch.The unit area is with the numeral of the least square of size F * F.Be opposite in advance on the routing cell district surface and go up or near NV NT memory node, the unit area depends on from alignment or the neat binding post of non-oneself whether be used to make NFET to select a termination contact of transistorized source electrode and NV NT switch or NV NT block switch.In certain embodiments, be positioned under the bit line, have top and bottom contact (being called node #10) and in cellular zone integrated NV NT block switch have 6-8F ²The estimation unit zone of scope.Use the 16 bit memory arrays of NV NT block switch as the Nonvolatile nanotube memory node

Shown in Fig. 9 A, nonvolatile memory array sketch 9000 comprise 16 nonvolatile storage unit C00, C10 ..., C33.Memory array is not limited to 16 unit, but can have for example millions of or billions of unit.Each memory cell shown in the memory array sketch 9000, for example be expressed as unit C00, comprise and select transistor T 00, it can be shown NFET, maybe can be that the PFET (not shown) maybe can be the CMOS switching device (not shown) that comprises NFET and PFET device, or the switching device (not shown) of other type.Each unit such as unit C00, also comprises Nonvolatile nanotube memory node NT00.Nonvolatile nanotube memory node NT00 (NV NT memory node) can use for example above-mentioned reach NV NT switchtype and the NV NT block switch type concluded among Fig. 8 D to form.

For example the transistorized source S C00 of the non-volatile memory cells of unit C00 by connecting NFET T00 for example forms to for example the first terminal of the NV NT memory node of the NV NT memory node NT00 shown in Fig. 9 A.The example of NV NT memory node is shown among Fig. 8 D.

Memory array sketch 9000 selects transistorized respective gates to form by connecting word line WL0, WL1, WL2 and WL3 NFET to the respective memory unit; Corresponding second terminal that connects auxiliary word lines WWL0, WWL1, WWL2 and WWL3 NV NT memory node to the respective memory unit; And as Fig. 9 A and 9B shown in, connect bit line BL0, BL1, BL2 and BL3 corresponding NFET to the corresponding non-volatile memory cells and select transistorized respective drain to spread.For example, word line WL0 is connected to the grid of NFET T00 by contact GC00; Auxiliary word lines WWL0 is connected to second terminal of Nonvolatile nanotube memory node NT00 by contact NC00; And bit line BL0 is connected to the drain electrode of T00 by contact DC00.

Memory array Column Layout 9002 shown in the plane of Fig. 9 B is to use the layout (design) corresponding to the exemplary 16 bit memory arrays of memory array sketch 9000 of 250nm CMOS design rule.Emphasize selected design work station arrangement level.

The unit C00 of the memory array Column Layout 9002 shown in Fig. 9 B and C10 form in same FET district 9005, and share common drain diffusion.Word line WL0 osculating element C00 on contact 9007 selects the transistorized grid of NFET, and it is corresponding to the contact GC00 between the grid of word line WL0 and NFET T00 in the memory array sketch 9000 shown in Fig. 9 A.Drain contact 9010 is shared by mirror image unit C00 shown in Fig. 9 B and C 10, and contact contacts the conductor segment 9015 of bit line BL0 again via contact 9020.Contact 9010 shown in Fig. 9 B is corresponding to the drain contact DC00 of NFETT00 shown in Fig. 9 A and the DC10 of NFET T01.The source electrode that connects NFET T00 to first contact of the NT00 of Nonvolatile nanotube memory node shown in Fig. 9 A by contact SC00.Further illustrate as the following Figure 13 of being relevant to B, NV NT block switch 4000 shown in Fig. 4 A (NV NT memory node numbering 9 among Fig. 8 D) places unit C00 to select on the source electrode of NFET, and has NV NT block 4035 bottom contact 4015 of extension with osculating element C00NFET source diffusion.Top/contact, side 4040 to the combination of NV NT block 4035 is connected to (part) shown in Fig. 4 A conductor 4045, and corresponding to the conductor segment among Fig. 9 B 9030.Conductor segment 9030 also is connected to the second word line WWL0 by contact 9035, and it is corresponding to the contact NC00 among Fig. 9 A.All C10NFET selectors and NV NT block switch are to be relevant to the described corresponding manner interconnection of unit C00.Aforesaid, all other unit are corresponding to the mirror image of unit C00 or unit C00.

SEM Figure 100 00 shown in Figure 10 A shows the plane of the memory cell that just part is made before the NV NT block switch corresponding to the block switch of NV NT shown in Fig. 4 A 4000 forms, and it is formed on the lower floor's unit selecting transistor and array routing corresponding to memory array Column Layout 9200.Use preferred approach and deposit about 40nm thick blanket shape (porous) nano tube structure layer covering surfaces insulator and wiring layer 10200, but invisible because SEM figure contrast is not enough.Yet corresponding (porous) graphical nanotube blocks is schemed further illustration by SEM among following Figure 10 B.Blanket shape nano tube structure layer uses spraying and deposits.Yet blanket shape nano tube structure layer also can form by a plurality of single nano tube structure layers of spin coating.Contact terminal 10100 shown in Figure 10 A is corresponding to the contact terminal 4010 shown in Fig. 4 A, and contact terminal 10150 is corresponding to contact terminal 4015.Blanket shape nano tube structure layer contact contact terminal of can't see among SEM Figure 100 00 10100 and 10150 top coplanar surface, and the end face of contact insulator and wiring layer 10200, it is corresponding to insulator among Fig. 4 A and wiring layer 4030.Lip-deep patterned mask 10250 images of blanket shape nano tube structure layer and overlapping contacts terminal 10150 are used at the blanket shape nano tube structure layer segment of protecting in the oxygen plasma etch step in technological process after a while under it.Patterned mask image 10250 can use Al2O3, Ge or any other compatible hard mask material to be formed.

Then, as what further describe in the patent documentation of being included in, the preferred approach etching is the expose portion of blanket shape nano tube structure layer in the oxygen plasma for example.Then, preferred approach removes patterned mask 10250 images.Then, preferred approach forms the conductor segment 10400 shown in SEM Figure 103 00 shown in Figure 10 A, and it is corresponding to the conductor 4045 shown in the conductor segment 9030 shown in Fig. 9 B and Fig. 4 A.Conductor segment 10400 also is formed up to the top/contact, side corresponding to the NV NT of the lower floor block (can't see) of contact 4040 shown in Fig. 4 A.Although can use other metal, in this example, conductor segment 10400 is that the Ti/Pd of 2/100nm forms by thickness.Then, preferred approach uses conductor segment 10400 to come the residue exposed region of etching of nano tubular construction as mask layer, to form NV NT block switch 10450 corresponding to the block switch of NV NT shown in Fig. 4 A 4000, and have the conductor segment 10400 that corresponds respectively to combination top/contact, side 4040 and conductor 4045, reach bottom contact 10150 corresponding to bottom contact 4042.

This moment in technology, finish manufacturing, and SEM Figure 103 00 of Figure 10 A shows the plane of top layer corresponding to 16 bit memory arrays of 16 bit memory array layouts 9002.NV NT block corresponding to NV NT block 4035 among Fig. 4 A be can't see in SEM Figure 103 00.Yet in further following Figure 10 B then as seen.Insulator and wiring layer 10200 ' corresponding to insulator and wiring layer 10200, but do not have blanket shape nano tube structure layer.

SEM Figure 105 00 shown in Figure 10 B illustrates SEM angled section image.The lip-deep contact terminal 10550 of insulator and wiring layer 10600 is corresponding to the contact terminal among SEM Figure 103 00 10150, and is formed up to the bottom contact of NV NT block 10650.Top contact terminal 10700 is corresponding to the zone of conductor segment 10400 among SEM Figure 103 00 of the top contact that is formed up to NV NT block 10650.NV NT block 10650 is about 25 * 80nm in this example.

The test and the characteristic description of the schematically illustrated 16 bit memory arrays 9000 of Fig. 9 A, it switches based on the ON/OFF state and resistance states is read, and having the distribution form of the block switch of NV NT shown in Fig. 9 B memory device, and on the top layer of 16 bit memory array structures shown in Figure 10 A, implement among SEM Figure 103 00 of formed NV NT block switch memory block.The ON/OFF status exchange result of NV NT block switch illustrates by waveform 4500 among Fig. 4 B, and it uses about 6 volts single pulse and switches between ON and OFF state.Write 0 operation NV NT block switch is switched to OFF or high resistance state from ON, NV NT block switch is switched to ON or low resistance state from OFF and write 1 operation.Shown in Fig. 4 B, the ON resistance value is in hundreds of K ohm scopes usually, and the OFF resistance value is in the begohm scope usually.If a plurality of pulses be used to write 0 and write 1 the operation, switched voltage just can be lower than for example 6 volts.Write 0, write 1 with read voltage and current waveform can be as the U.S. Patent application No.11/280 that is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " that submits to simultaneously with the application, 786 and U.S. Patent application No. (to be arranged) described in.

The 16 bit memory arrays 9000 that schematically show in the layout of Fig. 9 A and Fig. 9 B have cmos buffer device circuit (not shown) between weld pad and the word line (WL) and the buffer circuits between weld pad and the bit line (BL) as manufacturing ground.Second word line (WWL) then is connected directly to weld pad and does not have cmos buffer device circuit.

In operation, be in for example 5 volts relatively low voltage, and can implement to write 0 by having the word line and the bit line that are in the auxiliary word lines of the reference voltage of ground connection for example, write 1 and read operation.For for example being higher than 5 volts high voltage, can use auxiliary word lines to apply to write 0 and write 1 pulse to the selected unit of respective word, reduce the voltage at unit selecting transistor and cmos buffer device circuit two ends thus.The ability that changes the institute's polarity of voltage that applies and the sense of current is started by the bi-directional nature of NV NT block switch (also putting on NV NT switch), and this switch and applied voltage polarity and the sense of current have nothing to do.As the part of 16 bit memory arrays, 9000 characteristic descriptions, for individual unit write 0 and write 1 voltage and between the magnitude of voltage of broad range, change, thereby write 0 and write 1 pulse and use auxiliary word lines and apply.Use of the auxiliary word lines discharge of the read operation (for example being lower than 4 volts usually) of low-voltage bit line with word line that activates and ground connection.

Aforesaid, demonstration reading shown in Figure 11 A 11000 shows writing 0, write 1 and the result of read operation the exemplary 16 bit memory arrays 9000 with NV NT block switch.For writing 0 operation, wipe along all four bit synchronizations of selected word line.Thereby bit line BL0, BL1, BL2 and BL3 all remain on 0 volt, and switch to for example 5 volts high voltage such as the selected word line of word line WL0 from 0 volt.Then, one or more potential pulses are applied to corresponding auxiliary word lines WWL0.The WWL0 pulse amplitude can be from for example 4 to 8 volts of variations.Corresponding NV NT block switch NT00 switches from ON to OFF, or remains on the OFF state.Write 0 operation with WL1 and WWL1, WL2 and WWL2 and WL3 and WWL3 repetition, all be in the OFF state until all positions.Bit pattern 11100 expression shown in Figure 11 A is write 0 (OFF state) to each of 16 in the 16 bit memory arrays 9000, makes that each is OFF or high resistance state.

For read operation, for example the bit line of bit line BL0 switches to and for example is lower than 3 or 4 volts voltage, and for example the selected word line of word line WL0 selects the transistor activation to be the ON state NFET of for example T00, and connects the extremely for example corresponding auxiliary word lines of the ground connection of WWL0 of BL0 via the corresponding NV NT block of for example NT00.If corresponding NV NT block switch NT00 is in the OFF state, BL0 just remains unchanged and detects " 0 " or OFF state.Yet if corresponding NV NT block switch NT00 is in " 1 " or ON state, bit line BL0 voltage just reduces (decline) and detects " 1 " state so.In this example, read operation produces bit pattern 11150, and wherein all positions all are in " 0 " or OFF state, makes output bit pattern 11150 corresponding to input bit pattern 11100.

Write 1 operation and once carry out one, for example WL0 and for example corresponding auxiliary word lines WWL0 along selected word line.By bit line BL0 is remained on 0 volt, bit line BL1, BL2 and BL3 remain on for example 4 or 5 volts high voltage simultaneously, and with logic " 1 " or low resistance state writing unit C00.Then, one or more potential pulses are applied in to corresponding auxiliary word lines WWL0.The WWL0 pulse amplitude can be from for example 4 to 8 volts variations, and unit C00 is from the switching of logic " 0 " high resistance state, and non-volatile logic " 1 " or low resistance state are stored on the NT00.C01 will store 0 in this example, thereby as above be relevant to and write 0 operation and further describe, because whole array was wiped free of before writing 0 operation, so do not apply pulse.

Be relevant to as mentioned above and write 1 operation and describe describedly, write 1 operation and once implement one, be written into memory array 9000 until checker board pattern 11200.In this example, checker board pattern 11200 is applied to the 16 bit memory arrays of wiping in advance 9000.Then, shown as showing reading 11000, read operation produces corresponding chessboard bit pattern 11250, and 16 maintenances save as non-volatile logic " 0 " or " 1 " state in the memory array 9000.

Aforesaid, because of becoming in applying voltage, the single NV NT block switch 10450 shown in Figure 10 A switches between ON and OFF, low and high resistance state respectively.Under first situation, further describe as the following Figure 11 of being relevant to B, use the quick ascending, descending time such as 2ns.Under second situation, further describe as the following Figure 11 of being relevant to C, use for example slow ascending, descending time of 10 μ s.Under two kinds of situations, write 0 and write 1 and switch and all to use 10 pulses.And, under two kinds of situations, write for 0 retention time of using 20 μ s, write for 1 retention time of using 1ms.Usually, test status is similar to and is relevant to Fig. 4 B and 5B, and the U.S. Patent application No.11/280 that is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " that submits to simultaneously with the application, 786, the ON/OFF described in the U.S. Patent application No. (to be arranged) exchanges.

Schmoo Figure 114 00 shown in Figure 11 B shows 0 operation of writing along 1 to 7 volt scope of trunnion axis, and 1 to 7 volt scope of vertical direction write pass through to reach to fail and distinguishing of 1 operation.Show that to apply voltage be 4 volts and above write 0 and write the successful switch that 1 operation generation is similar to the NV NT block switch of NV NT block switch 10450 by distinguishing 11450.Write 0 and to write 1 voltage invalid by what distinguish 11450 outsides.

Schmoo Figure 115 00 shown in Figure 11 C shows and writes pass through to reach to fail and distinguishing of 1 operation along 1 to 12 volt scope writing 0 operation and vertical direction of 1 to 12 volt scope of trunnion axis.Show that by distinguishing 11550 the voltages that apply are 4 volts and above write 0 and write 1 and operate the successful switch that generation is similar to the NV NT block switch of NV NT block switch 10450.Write 0 and to write 1 voltage invalid by what distinguish 11550 outsides.In certain embodiments, an exception for as position 11600 specified at the NV NT block switch of writing 1 minimum 5 volts of switches of operating.

Use NV NT switch or NVNT block switch memory array as the Nonvolatile nanotube memory node of bit line with contiguous NV memory node position

As shown in the shown memory array sketch 9000 of Fig. 9 A, memory array can form by the interconnection non-volatile memory cells, this non-volatile memory cells comprise for example selection transistor, for example NV NT switch or the NV NT block switch of NFET the Nonvolatile nanotube memory node, and this unit in and the interconnection between the array lines of this unit and for example word line, bit line and auxiliary word lines.Fig. 8 D concludes all kinds of Nonvolatile nanotube memory node 1-13, comprises the simple description of integrated layer and corresponding figures numbering in each type NV NT memory node, the integrated morphology.

For asking integrated easiness, for example some embodiment of the Nonvolatile nanotube memory node of NV NT switch or NV NT block switch can be positioned memory array organization the top or near, and with respect to the bit lines of memory array of integrated morphology bottom and can randomly be offset, so that the first Nonvolatile nanotube storage node and corresponding NFET select direct vertical connection the between the transistorized lower floor source electrode.That is, this NFET selects transistor, and binding post connects source electrode and drain diffusion, and can form before the Nonvolatile nanotube memory node forms such as the array lines of word line, bit line and auxiliary bit line, its can the terminal of technological process or near formation.Place the top of integrated morphology or near Nonvolatile nanotube memory node at the contact terminal metal and insulator is selected and the selection of nonisulated body option provides the flexibility of enhancing, this can promote the electric property of Nonvolatile nanotube memory node.Yet in certain embodiments, the unit area can be bigger, and is for example big by 50% to 100%, and big in some configurations more than 200%.

The top of memory cell or near have NV NT switch or a NV NT block switch memory cell in following unit area of being concluded in Figure 20 B and be relevant to Figure 12 A-15 and further describe.

Use places the memory array of the NV NT switch on the array routing

Figure 12 A illustrates the plane of the memory array 12000 of using four memory cell, and this memory cell uses NV NT switch as being positioned at memory array 12000 structural top or near nonvolatile semiconductor memory member.Figure 12 B illustrates respective memory array 12000 ' sectional view of obtaining along cutting line A1-A1

'.Memory cell

12050A and 12050B are mirror image each other.Memory cell 12050A will be used for describing the cellular construction of memory array 12000 typical units.Though memory cell 12050A shows the NV NT storage node 12150A as nonisulated NV NT switch 2000 shown in above-mentioned Fig. 2 A, and in Fig. 8 D, be listed as NV NT storage node #1, but the arbitrary insulation or the nonisulated NV NT storage node that are numbered 1-8 and list in Fig. 8 D all can use, to replace NV NT storage node 12150A.

Unit selecting transistor 12100A comprises the source electrode 12200 that is formed in the silicon substrate 12300 and drains 12250.Manufacturing has the grid 12350 of sidewall spacer 12400 to be partial array word line 12350, and it forms gate regions and array interconnect, and uses the ON and the OFF state of the FET device operation method control channel region of knowing 12450.On the other hand, the word line conductor (not shown) for example gate regions of the selector of unit selecting transistor 12100A shown in Figure 12 A and 12B that can be used for interconnecting independently.The binding post 12500 of embedding dielectric 12625 provides the conductive path between source electrode 12200 and the binding post 12550, and binding post 12550 forms first contact terminal of NV NT switch 12150A again.Second contact terminal 12600 of NV NT switch 12150A is segmentations of auxiliary word lines 12600.The top coplanar surface of NVNT element 12650 contact contact terminals 12550 and a segmentation of auxiliary word lines 12600, and the end face of coplane insulator 12625.NV NT switch 12150B is the mirror image of NV NT switch 12150A.

The drain electrode 12250 contact binding posts 12700 of unit selecting transistor 12100A, binding post 12700 is the 12800 contact conductor segment 12750 in the contact again.Conductor segment 12750 is the 12850 contact bit lines of memory array 12900 in the contact also, use that drain diffusion 12250 is connected with bit line 12900.Drain electrode 12250 is shared with adjacent unit (can't see in Figure 12 A or 12B).

As mentioned above, NV

NT memory node

12150A and 12150B can be one of several nonisulated NVNT switches.For example, can use the NV NT switch 3000 shown in the NV NT switch 2000 shown in Fig. 2 and Fig. 3, and need not the protectiveness dielectric layer for the application that chip is installed on sealed package.

On the other hand, NV

NT memory node

12150A and 12150B can be one of several insulation NV NT switches.Can use 7000 shown in 6060 shown in 6040 shown in 6020 shown in the NV switch 6000 shown in Fig. 6 A, Fig. 6 B, Fig. 6 C, Fig. 6 D, Fig. 7 A for example, and Fig. 7 B shown in 7050.Also can use other embodiment.Respectively scheme shownly as above-mentioned, these NV NT switches can be used single insulating body layer, the combination of insulator layer, and the combined insulation of insulator layer and interstitial area.As in this article in greater detail, other embodiment covers NV NT switch with conductor.

In certain embodiments, be about 20F such as memory cell 12050A that forms memory array 12000 and the memory cell estimated area of 12050B ², wherein F is the minimum technology node size.Further hypothesis is used when forming cellular construction from aliging the vertical junction terminal.This stacked contact and the through hole (vertical junction terminal) of filling in are at Ryan, J.G. wait the people to show Journal of Research and Development, Vol.39, No.4, July 1995, shown in the prior art document of " development of the interconnection technique of IBM " of pp.371-381 (Theevolution of interconnection technology at IBM), its full content is incorporated herein by reference.As described in more detail below, if the vertical junction terminal is from alignment, the size of unit area (overlay area) is estimated to increase above twice, for greater than the 40F shown in Figure 20 B ²

Use has the memory array of the NV NT block switch of the top/side that places on the array routing and bottom contact

Figure 13 A illustrates the plane of the memory array 13000 of using four memory cell, and this memory cell uses NV NT switch as being positioned at memory array 13000 structural top or near non-volatile storage device selection.Figure 13 B illustrates respective memory array 13000 ' sectional view of obtaining along cutting line A2-A2

'.Memory cell

13050A and 13050B are mirror image each other.Memory cell 13050A will be used for describing the cellular construction of memory array 13000 typical units.Though memory cell 13050A shows the NV NT memory node 13150A as nonisulated NV NT switch 4000 shown in above-mentioned Fig. 4 A, and in Fig. 8 D, be listed as NV NT storage node #9, but

number

9,11 or 12 and the arbitrary insulation or the nonisulated NV NT memory node that in Fig. 8 D, list all can use, to replace NVNT memory node 13150A.Be used for describing the NV NT block switch 4000 of memory array 13000 corresponding to NV NT block switch 10450 shown in SEM Figure 103 00 shown in Figure 10 A.

Unit selecting transistor 13100A comprises the source electrode 13200 that is formed in the silicon substrate 13300 and drains 13250.It is parts of array word line 13350 that manufacturing has the grid 13350 of sidewall spacer 13400, and it forms gate regions and array interconnect, and uses the ON and the OFF state of the FET device operation method control channel region of knowing 13450.On the other hand, the word line conductor (not shown) for example gate regions of the selector of unit selecting transistor 13100A shown in Figure 13 A and 13B that can be used for interconnecting independently.The binding post 13500 of embedding dielectric 13625 provides the conductive path between source electrode 13200 and the binding post 13550, and binding post 13550 is formed up to first contact terminal of the NV NT block 13650 of NV NT switch 13150A again.NV NT block 13650 is surperficial overlapping with binding post 13500 that is used as the bottom contact terminal and SI semi-insulation body 13625, also is called overlap length L as mentioned above _OLFormed by conductor segment 13675 to the end face of NV NT block 13650 and second contact terminal of a side, it also contacts the terminal 13600 of NV NT switch 13150A, and this terminal is the segmentation of auxiliary word lines 13600.NV NT block switch 13150B is the mirror image of NV NT block switch 13150A.

The drain electrode 13250 contact binding posts 13700 of unit selecting transistor 13100A, this binding post 13700 is contact conductor segment 13750 on contact 13800 again.Conductor segment 13750 is contact bit lines of memory array 13900 on contact 13850 also, uses to connect drain diffusion 13250 and bit line 13900.Drain electrode 13250 is shared with adjacent unit (not seeing among Figure 13).

As mentioned above, NV NT memory node 13150A and 13150B can be nonisulated NV NT block switch.For example, can use the NV NT block switch 4000 shown in Fig. 4 A, the application that is installed on sealed package for chip need not the protectiveness dielectric layer.The 16 bit memory arrays 9000 that schematically show among Fig. 9 A are arranged in the layout 9002 of Fig. 9 B, and the SEM Figure 103 00 among Figure 10 A is the example of manufacturing memory array 13000.

Perhaps, NV NT memory node 13150A and 13150B can be one of several insulation NV NT block switch.Can use for example 8020 shown in the NV block switch 8000 shown in Fig. 8 A and Fig. 8 B.Respectively scheme shownly as above-mentioned, these NV NT block switch can be single insulating body layers, the combination of insulator layer, and the insulation of the combination of insulator layer and interstitial area.

In certain embodiments, for example form the memory cell 13050A of memory array 13000 and the memory cell estimated area of 13050B and be about 20F ², wherein F is the minimum technology node size.Further hypothesis is used when forming cellular construction from aliging the vertical junction terminal.This laminated contact and through hole (vertical junction terminal) illustration in the document of being included in of filling in.If the vertical junction terminal is from alignment, the size of unit area (overlay area) is estimated to increase above twice, for greater than the 40F shown in Figure 20 B ²

Use has the memory array of the NV NT block switch of the top that places on the array routing and bottom contact

Figure 14 A illustrates the plane of the memory array 14000 of using four memory cell, and this memory cell uses NV NT block switch as being positioned at memory array 14000 structural top or near nonvolatile semiconductor memory member.Figure 14 B illustrates respective memory array 14000 ' sectional view of obtaining along cutting line A3-A3

'.Memory cell

14050A and 14050B are mirror image each other.Memory cell 14050A will be used for describing the cellular construction of nram memory array 14000 typical units.Memory cell 14050A uses the insulation NV NT block switch 5000 shown in above-mentioned Fig. 5 A, and is listed as NV NT memory node #10 in Fig. 8 D.

Unit selecting transistor 14100A comprises the source electrode 14200 that is formed in the silicon substrate 14300 and drains 14250.The grid 14350 that manufacturing has a sidewall spacer 14400 is one one of subarray word line 14350, and it forms gate regions and array interconnect, and uses the ON and the OFF state of the FET device operation method control channel region of knowing 14450.Perhaps, the word line conductor (not shown) for example gate regions of the selector of unit selecting transistor 14100A shown in Figure 14 A and 14B that can be used for interconnecting independently.The binding post 14500 of embedding dielectric 14625 provides the conductive path between source electrode 14200 and the binding post 14550, and binding post 14550 is formed up to the first bottom contact terminal of the NV NT block 14600 of NV NT block switch 14150A again.The second top contact terminal 14650 to NV NT block 14600 is used as the top contact terminal, and when aliging NV NT block 14650 sides certainly as the qualification that further describes in the patent documentation of being included in, can be used as mask.Top contact terminal 14650 contact auxiliary word lines 14675.NV NT block switch 14150B is the mirror image of NV NT block switch 14150A.

The drain electrode 14250 contact binding posts 14700 of unit selecting transistor 14100A, binding post 14700 is contact conductor segment 14750 on contact 14800 again.Conductor segment 14750 is contact bit lines of memory array 14900 on contact 14850 also, uses to connect drain diffusion 14250 and bit line 14900.Drain electrode 14250 is shared with adjacent unit (not seeing in Figure 14 A or 14B).

Have NV

NT block switch

14150A and 14150B as the memory cell 14050A of the memory array 14000 of NV NT memory node and the memory cell of 14050B such as formation, owing to compact 3 dimension tops and bottom contact NV NT block switch geometry (structure) form dense cell.In certain embodiments, memory cell region (overlay area) estimated area is about 12-15F ², wherein F is the minimum technology node size.Further hypothesis is used when forming cellular construction from aliging the vertical junction terminal.This laminated contact and the through hole (vertical junction terminal) of filling in list in the document of being included in.As the following ground that is shown in further detail, if the vertical junction terminal is from alignment, the size of unit area (overlay area) is estimated to increase above twice, for greater than the 30F shown in Figure 20 B ²

Use has the memory array of the sealing NV NT block switch of top/all sides that place on the array routing and bottom contact

Figure 15 illustrates and show to use the sectional view of sealing NV NT block switch as the memory array 15000 of two memory cell that are positioned at memory array 15000 structural top or near Nonvolatile memory

devices.Memory cell

15050A and 15050B are mirror image each other.Memory cell 15050A will be used for describing the cellular construction of memory array 15000 typical units.Memory cell 15050A replaces and is used for the insulation NV NT block switch 5000 of memory cell 14050A, and is listed as the NV NT memory node #10 with the insulation sealing NV NT block switch 8050 that is listed as NV NT memory node #13 shown in above-mentioned Fig. 8 C and in Fig. 8 D in Fig. 8 D.

The insulator that contacts with NV NT block surface can make electrical characteristic constant, can promote electrical characteristic, or even can limit the electric operation of NV NT block switch.Integrated for ease of NV NT block switch in the memory array, can be by using sealing NV NT block switch to reduce or eliminating the sensitiveness that insulating material is selected, this sealing NV NT block switch comprises with insulator avoids the top of corresponding NV NT block and the top of all contacts side surfaces/all side contact terminals.Memory cell 15050A is similar to the unit 14050A that illustrates respectively in the plane (layout) of Figure 14 A and 14B and the sectional view.Thereby only the sectional view of memory array 15000 is presented among Figure 15.Sealing NV NT block switch 15150A is the variant of NV NT block switch 14150A, to be relevant to as shown in Fig. 8 C sealing NV NT block switch 8050 described as above, and wherein the conductor that contact with the end face of NV NT block 15600 also seals (coating) NV NT block 15600 with manufacturing top/all contacts, side.Should center on (coating) conductor can be thinner relatively, and for example 5 to 50nm, is used to form sealing contact, NV NT block side, and avoid contacts side surfaces with insulating material.

Unit selecting transistor 15100A comprises the source electrode 15200 that is formed in the silicon substrate 15300 and drains 15250.Manufacturing has the grid 15350 of sidewall spacer 15400 to be the part of array word line 15350, and it forms gate regions and array interconnect, and uses the ON and the OFF state of the FET device operation method control channel region of knowing 15450.Perhaps, the word line conductor (not shown) for example gate regions of the selector of the 15100A of unit selecting transistor shown in Figure 15 that can be used for interconnecting independently.The binding post 15500 of embedding dielectric 15625 provides the conductive path between source electrode 15200 and the binding post 15550, and binding post 15550 is formed up to the first bottom contact terminal of the NV NT block 15600 of sealing NV NT switch 15150A again.The end face of contact NV NT block 15600 and the top of all sides/all side contact terminals 15650 form second contact, and as shown in the sectional view of Figure 15, also contact with auxiliary word lines 15675.NV NT block switch 15150B is the mirror image of NV NT block switch 15150A.

The drain electrode 15250 contact binding posts 15700 of unit selecting transistor 15100A, binding post 15700 is contact conductor segment 15750 on contact 15800 again.Conductor segment 15750 also contacts bit lines of memory array (not shown among Figure 15), but the contact (not shown) of contact 14850 is corresponding to bit lines of memory array 14900 in corresponding to Figure 14 A, uses to connect drain diffusion 15250 and bit line (not shown) corresponding to Figure 14 A neutrality line 14900.Drain electrode 15250 is shared with adjacent unit (not seeing in Figure 15).

For example form and have sealing NV

NT block switch

15150A and 15150B as the memory cell 15050A of the memory array 15000 of NV NT memory node and the memory cell of 15050B, because the edge of the transverse gage of top/all side contact terminals 15650 and bottom contact terminal 15550 and the interval between top/all side contact terminals 15650 are (as above-mentioned alleged L _OL), can form the unit that density is lower than

unit

14150A and 14150B, but more for example unit 13150A and 13150B are intensive.In certain embodiments, memory cell region (overlay area) estimated area is about 15-20F ², wherein F is the minimum technology node size.Further hypothesis is used when forming cellular construction from aliging the vertical junction terminal.This stacked contact and the through hole (vertical junction terminal) of filling in further list in the document of being included in.Be shown in further detail as following, if the vertical junction terminal is from alignment, in certain embodiments, the size of unit area (overlay area) is estimated to increase above twice, for greater than the 30-40F shown in Figure 20 B ²

Use NV NT switch or NV NT block switch memory array as Nonvolatile nanotube memory node with integrated NV memory node with lift unit/array density (reducing unit/array overlay area)

In certain embodiments, memory array by interconnection comprise for example transistorized non-volatile memory cells of selection, for example NV NT switch or the NV NT block switch of NFET the Nonvolatile nanotube memory node, and the unit in interconnection mechanism and unit and for example formation of the interconnection mechanism between the array lines of word line, bit line and auxiliary word lines shown in the memory array sketch 9000 shown in Fig. 9 A.Fig. 8 D concludes various Nonvolatile nanotube memory node 1-13, comprises the Short Description of each class NV NT memory node, the interior integrated layer of integrated morphology and corresponding figures numbering.

For improving unit/array density (reducing unit/array overlay area), for example the Nonvolatile nanotube memory node of NV NT switch or NV NT block switch can embed in the memory cell of selecting array bitline below in NFET transistorized source electrode top and the integrated morphology, make that array bitline can be positioned to select on the NFET transistor so that as below be relevant among the shown and Figure 20 B of Figure 16 A-20A and improve cell density inductively.

Use places under the array bitline, selects near the transistor and the memory array of the NV NT switch that contacts with source electrode

Figure 16 A illustrates and shows that use NV NT switch is as embedding the plane of memory array 16000 structures with the memory array 16000 of four memory cell of the nonvolatile semiconductor memory member of raising unit/array density.Figure 16 B illustrates respective memory array 16000 ' sectional view of obtaining along cutting line A4-A4

'.Memory cell

16050A and 16050B are mirror image each other.Exemplary memory unit 16050A will be used for describing the cellular construction of memory array 16000 typical units.Though memory cell 16050A shows the NV NT memory node 16150A as the NV of insulation shown in above-mentioned Fig. 6 A NT switch 6000, and in Fig. 8 D, be listed as NV NT memory node #3, but numbering 3-8 and the arbitrary insulation NV NT memory node that lists in Fig. 8 D all can use, to replace NV NT memory node 16150A.Other embodiment also can use.

Unit selecting transistor 16100A comprises the source electrode 16200 that is formed in the silicon substrate 16300 and drains 16250.Manufacturing has the grid 16350 of sidewall spacer 16400 to be the part of array word line 16350, and it forms gate regions and array interconnect, and uses the ON and the OFF state of the FET device operation method control channel region of knowing 16450.Perhaps, the word line conductor (not shown) for example gate regions of the selector of the unit selecting transistor 16100A shown in Figure 16 A and 16B that can be used for interconnecting independently.The binding post 16500 that embeds dielectric 16625 provides source electrode 16200 and the also conductive path between first contact terminal of the NV NT switch 16150A of embedding dielectric 16625, and wherein binding post 16500 can be used as first contact terminal of NV NT switch 16150A.The part of the auxiliary word lines 16600 that second contact terminal 16600 of NV NT switch 16150A is.The top coplanar surface of NV NT element 16650 contact contact terminals 16500.NV NT switch 16150B is the mirror image of NV NT switch 16150A.

The drain electrode 16250 contact binding posts 16700 of unit selecting transistor 16100A, binding post 16700 again on contact 16800 contact binding post 16900 '.Binding post 16900 ' contact bit line 16900 is used interconnection bit line 16900 and is drained 16250.Binding post 16900 ' reach bit line 16900 can use preferable manufacture method to form in the identical time, for example USP 4,944, conductor deposition described in 836 and chemically mechanical polishing (CMP) method.Drain electrode 16250 is shared with adjacent unit (not seeing in Figure 16 A or 16B).

As mentioned above, NV NT memory node 16150A and 16150B can be one of several insulation NV NT block switch.Can use for example 7050 shown in 7000 and Fig. 7 B shown in 6060 shown in 6040 shown in 6020 shown in the NV switch 6000 shown in Fig. 6 A, Fig. 6 B, Fig. 6 C, Fig. 6 D, Fig. 7 A.Respectively scheme shownly as above-mentioned, these NV NT switches can be used single insulating body layer, the combination of insulator layer, or the combined insulation of insulator layer and interstitial area.

The plane of the memory array 16000 shown in Figure 16 A and the respective cross-section Figure 160 00 ' shown in Figure 16 B show the integrated morphology that limits layer manufacturing via bit line 16900.All the other insulation (and conductor) layer can be formed on bit line 16900 (not shown) that comprise last chip passivation and chip terminal metal level (not shown).

In certain embodiments, for example form the memory cell of the memory cell 16050A and the 16050B of memory array 16000, shown in following Figure 20 B, estimated area is about 12-15F ², wherein F is the minimum technology node size.

Use places under the array bitline, selects near the transistor and the memory array of the NV NT switch with top/side and bottom contact that contacts with source electrode

Figure 17 A illustrates and shows that use has the NV NT switch of top/side and bottom contact terminal as embedding the plane of memory array 17000 structures with the memory array 17000 of four memory cell of the nonvolatile semiconductor memory member of raising unit/array density.Figure 17 B illustrates respective memory array 17000 ' sectional view of obtaining along cutting line A5-A5

'.Memory cell

17050A and 17050B are mirror image each other.Exemplary memory unit 17050A will be used for describing the cellular construction of memory array 17000 typical units.Though memory cell 17050A shows the NV NT memory node 17150A as the insulation NV NT switch 8000 with top/side and bottom contact terminal shown in above-mentioned Fig. 8 A, and in Fig. 8 D, be listed as NV NT memory node #11, but the insulation NV NT memory node 12 that lists in Fig. 8 D or other insulator configuration (not shown) all can be used, to replace NV NT memory node 17150A.

Unit selecting transistor 17100A comprises the source electrode 17200 that is formed in the silicon substrate 17300 and drains 17250.Manufacturing has the grid 17350 of sidewall spacer 17400 to be the part of array word line 17350, and it forms gate regions and array interconnect, and uses the ON and the OFF state of the FET device operation method control channel region of knowing 17450.Perhaps, the word line conductor (not shown) for example gate regions of the selector of unit selecting transistor 17100A shown in Figure 17 A and 17B that can be used for interconnecting independently.The binding post 17500 that embeds dielectric 17625 provides source electrode 17200 and also embeds conductive path between first contact terminal of NV NT switch 17150A of dielectric 17625, and wherein binding post 17500 can be used as to first contact terminal of the NV NT block 17650 of NV NT switch 17150A.Second contact terminal 17675 of NV NT switch 17150A forms by conductor segment 17675, and is formed up to the top/contact, side of NVNT block 17650, and contact auxiliary word lines 17600.NV NT switch 17150B is the mirror image of NV NT switch 17150A.

The drain electrode 17250 contact binding posts 17700 of unit selecting transistor 17100A, binding post 17700 again on contact 17800 contact binding post 17900 '.Binding post 17900 ' contact bit line 17900 is used interconnection bit line 17900 and is drained 17250.Described in the above Figure 16 of being relevant to A-16B and institute's patent documentation of including in, binding post 17900 ' and bit line 17900 can be in identical time formation.Drain electrode 17250 is shared with adjacent unit (not seeing in Figure 17 A or 17B).

As mentioned above, NV NT memory node 17150A and 17150B can be one of several insulation NV NT block switch, for example the NV NT block switch 8020 shown in the NV switch 8000 shown in Fig. 8 A and Fig. 8 B.Respectively scheme shownly as above-mentioned, these NV NT switches can be used single insulating body layer, the combination of insulator layer, or the combined insulation of insulator layer and interstitial area.

The plane of the memory array 17000 shown in Figure 17 A and the respective cross-section Figure 170 00 ' shown in Figure 17 B show the integrated morphology that limits layer manufacturing via bit line 17900.All the other insulation (and conductor) layer can be formed on bit line 17900 (not shown) that comprise last chip passivation and chip terminal metal level (not shown).

In certain embodiments, for example form the memory cell of the memory cell 17050A and the 17050B of nram memory array 17000, shown in following Figure 20 B, estimated area is about 12-15F ², wherein F is the minimum technology node size.

Use places under the array bitline, selects near the transistor and the memory array of the NV NT switch with top and bottom contact that contacts with source electrode

Figure 18 A illustrates and shows that use has the NV NT switch of top and bottom contact terminal as embedding the plane of memory array 18000 structures with the memory array 18000 of four memory cell of the Nonvolatile memory devices of raising unit/array density.Figure 18 B illustrates respective memory array 18000 ' sectional view of obtaining along cutting line A6-A6

'.Memory cell

18050A and 18050B are mirror image each other.Exemplary memory unit 18050A will be used for describing the cellular construction of memory array 18000 typical units.Memory cell 18050A shows the NV NT memory node 18150A as the insulation NV NT switch 5000 with top and bottom contact terminal shown in above-mentioned Fig. 5 A, and is listed as NV NT memory node #10 in Fig. 8 D.

Unit selecting transistor 18100A comprises the source electrode 18200 that is formed in the silicon substrate 18300 and drains 18250.Manufacturing has the grid 18350 of sidewall spacer 18400 to be the part of array word line 18350, and it forms gate regions and array interconnect, and uses the ON and the OFF state of the FET device operation method control channel region of knowing 18450.Perhaps, the word line conductor (not shown) for example gate regions of the selector of the unit selecting transistor 18100A shown in Figure 18 A and 18B that can be used for interconnecting independently.The binding post 18500 that embeds dielectric 18625 provides source electrode 18200 and also embeds conductive path between first contact terminal of NV NT switch 18150A of dielectric 18625, and wherein binding post 18500 can be used as to the bottom contact terminal of the NV NT block 18600 of NV NT switch 18150A.The top contact terminal 18650 of the end face of contact NV NT block 18600 forms second contact, and also contacts with auxiliary word lines 18675.NV NT block switch 18150B is the mirror image of NV NT switch block 18150A.

The drain electrode 18250 contact binding posts 18700 of unit selecting transistor 18100A, binding post 18700 again on contact 18800 contact binding post 18900 '.Binding post 18900 ' contact bit line 18900 is used interconnection bit line 18900 and is drained 18250.Described in the above Figure 16 of being relevant to A-16B, 17A-17B and institute's patent documentation of including in, binding post 18900 ' and bit line 18900 can be in identical time formation.Drain electrode 18250 is shared with adjacent unit (not seeing in Figure 18 A or 18B).

As mentioned above, NV

NT memory node

18150A and 18150B use the NV NT block switch 5000 shown in above-mentioned Fig. 5 A to improve unit/array density (reducing unit/array overlay area).Though NV

NT memory node

18150A and 18150B illustrate the NV NT block switch 5000 with the insulation of single insulating body layer, as above-mentionedly respectively scheme shownly, also can use the combination of insulator layer, and the combination of insulator layer and interstitial area.

The plane of the memory array 18000 shown in Figure 18 A and the respective cross-section Figure 180 00 ' shown in Figure 18 B show the integrated morphology that limits layer manufacturing via bit line 18900.All the other insulation (and conductor) layer can be formed on bit line 18900 (not shown) that comprise last chip passivation and chip terminal metal level (not shown).

In certain embodiments, for example form the memory cell of the memory cell 18050A and the 18050B of nram memory array 18000, shown in following Figure 20 B, estimated area is about 6-8F ², wherein F is the minimum technology node size.

Use places under the array bitline, selects near the transistor and the memory array of sealing (covering) the NV NT switch with top/all sides and bottom contact that contacts with source electrode

Figure 19 illustrates and shows the sectional view of use sealing (covering) NV NT block switch as near the memory array 19000 of two unit of the nonvolatile semiconductor memory member the selection transistor that is positioned at memory array 19000

structures.Memory cell

19050A and 19050B are mirror image each other.Memory cell 19050A will be used for describing the cellular construction of memory array 19000 typical units.Memory cell 19050A replaces and is used for the insulation NV NT block switch 5000 of unit 18050A, and lists in Fig. 8 D as the NV NT memory node #10 with the insulation sealing NV NT block switch 8050 that is listed as NV NT memory node #13 shown in above-mentioned Fig. 8 C and in Fig. 8 D.

As mentioned above, the insulator that contacts with NV NT block surface can make electrical characteristic constant, can promote electrical characteristic, or even can limit the electric operation of NV NT block switch.Integrated for ease of NV NT block switch in the memory array, can be by using sealing NV NT block switch to reduce or eliminating the sensitiveness that insulating material is selected, this sealing NV NT block switch comprises with insulator avoids the top of corresponding NV NT block and the top of all contacts side surfaces/all side contact terminals.Memory cell 19050A is similar to the unit 18050A that illustrates respectively in the plane (layout) of Figure 18 A and 18B and the sectional view.Thereby only the sectional view of memory array 19000 is shown among Figure 19.Sealing NVNT block switch 19150A is the variant of NV NT block switch 18150A, to be relevant to as shown in Fig. 8 C sealing NV NT block switch 8050 described as above, and wherein the conductor that contact with the end face of NV NT block 19600 also seals (coating) NV NT block 19600 with manufacturing top/all contacts, side.Should center on (coating) conductor can be thinner relatively, and for example 5 to 50nm, is used to form sealing contact, NV NT block side, and avoids contacts side surfaces with insulating material in fact.

Unit selecting transistor 19100A comprises the source electrode 19200 that is formed in the silicon substrate 19300 and drains 19250.Manufacturing has the grid 19350 of sidewall spacer 19400 to be the part of array word line 19350, and it forms gate regions and array interconnect, and uses the ON and the OFF state of the FET device operation method control channel region of knowing 19450.Perhaps, the word line conductor (not shown) for example gate regions of the selector of the unit selecting transistor 19100A shown in Figure 19 that can be used for interconnecting independently.The binding post 19500 that embeds dielectric 19625 provides source electrode 19200 and also embeds conductive path between first contact terminal of NVNT block switch 19150A of dielectric 19625, and wherein binding post 19500 can be used as to the bottom contact of the NV NT block 19600 of NV NT block switch 19150A.The end face of contact NV NT block 19600 and the top of all sides/all side contact terminals 19650 form second contact, and also contact with auxiliary word lines 19675.NV NT block switch 19150B is the mirror image of NV NT block switch 19150A.

The drain electrode 19250 contact binding posts 19700 of unit selecting transistor 19100A, binding post 19700 again on contact 19800 contact binding post 19900 '.Binding post 19900 ' contact bit line 19900 is used interconnection bit line 19900 and is drained 19250.As described in the above Figure 16 of being relevant to A-16B, 17A-17B, 18A-18B and the patent documentation included in, binding post 19900 ' and bit line 19900 can form in the identical time.Drain electrode 19250 is shared with adjacent unit (not seeing in Figure 19).

Have sealing NV

NT block switch

19150A and 19150B as the memory cell 19050A of the memory array 19000 of NV NT memory node and the memory cell of 19050B such as formation, in certain embodiments, since the interval of the edge of the transverse gage of top/all side contact terminals 19650 and bottom contact terminal 19550 and top/all side contact terminals 19650 (as above-mentioned alleged L _OL), can form the unit that density is lower than

unit

18150A and 18150B, but more for example unit 16150A and 16150B are intensive.In certain embodiments, shown in following Figure 20 B, memory cell region (overlay area) estimated area is about 12-15F ², wherein F is the minimum technology node size.

Use places under the array bitline, selects near the memory array of the NV NT block switch with top and bottom contact the transistor, and it has to the bit line contact of the top contact of this switch and to the drain contact of this bottom contact

Figure 20 A illustrates and uses the sectional view of NV NT block switch 5000 memory array 20000 of alternative arrangements between bit line contact and respective drain diffusion as shown in Figure 5A.Corresponding auxiliary word lines connects the corresponding source electrode of selecting the NFET device.In certain embodiments, the density of memory arrays of memory array 20000 (overlay area) approximates above-mentioned density of memory arrays with respect to the described memory array 18000 of Figure 18 A-18B (overlay area).

Figure 20 A illustrates and shows that use has the NV NT block switch of top and bottom contact terminal as the sectional view of the nonvolatile semiconductor memory member that embeds memory array 20000 structures with the memory array 20000 of the memory cell of raising unit/array

density.Memory cell

20050A and 20050B are mirror image each other.Exemplary memory unit 20050A will be used for describing the cellular construction of memory array 20000 typical units.Memory cell 20050A shows NV NT memory node 20150A as the insulation NV NT block switch 5000 with top and bottom contact terminal shown in above-mentioned Fig. 5 A, and is listed as NV NT memory node #10 in Fig. 8 D.

Unit selecting transistor 20100A comprises the source electrode 20200 that is formed in the silicon substrate 20300 and drains 20250.Manufacturing has the grid 20350 of sidewall spacer 20400 to be the part of array word line 20350, and it forms gate regions and array interconnect, and uses the ON and the OFF state of the FET device operation method control channel region of knowing 20450.Perhaps, the word line conductor (not shown) for example gate regions of the selector of unit selecting transistor 20100A shown in Figure 20 A that can be used for interconnecting independently.The binding post 20500 that embeds dielectric 20625 provides drain electrode 20250 and also embeds conductive path between first contact terminal of NV NT switch 20150A of dielectric 20625, and wherein binding post 20500 can be used as to the bottom contact terminal of the NV NT block 20600 of NV NT block switch 20150A.The top contact terminal that contacts with the end face of NV NT block 20,600 20650 forms second contact, and also with binding post 20900 ' contact.Binding post 20900 ' contact bit line 20900 is used the top contact terminal 20650 of interconnection bit line 20900 and NV NT block switch 20150A.As the above Figure 16 of being relevant to A-16B, 17A-17B, 18A-18B and 19 and institute's patent documentation of including in described in, binding post 20900 ' and bit line 20900 can form in the identical time.NV NT switch 20150B is the mirror image of NV NT switch 20150A.

The source electrode 20200 contact binding posts 20700 of unit selecting transistor 20100A, binding post 20700 is contact auxiliary word lines 20675 on contact 20800 again.Source electrode 20200 is shared with adjacent unit (not seeing in Figure 20 A).

As mentioned above, NV

NT memory node

20150A and 20150B use the NV NT block switch 5000 shown in above-mentioned Fig. 5 A, with lift unit/array density (reducing high unit/array overlay area).Though NV

NT memory node

20150A and 20150B illustrate the NV NT block switch 5000 with single insulating body layer, as abovely respectively scheme shownly, also can use the combination of insulator layer, and the combination of insulator layer and interstitial area.

The sectional view of the memory array 20000 shown in Figure 20 A shows the integrated morphology that limits layer manufacturing via bit line 20900.All the other insulation (and conductor) layer can be formed on bit line 20900 (not shown) that comprise last chip passivation and chip terminal metal level (not shown).

In certain embodiments, for example form the memory cell of the memory cell 20050A and the 20050B of memory array 20000, estimated area is about 6-8F ², wherein F is the minimum technology node size.

Though note that the NV NT block switch 5000 shown in Fig. 5 A as NV

NT block switch

20150A and 20150B, contacts with insulator 20625 if need to reduce, just can use the sealing NV NT block switch 8050 shown in Fig. 8 C to be replaced.Under this situation, for as be relevant to the same reasons of the memory array 19000 described in Figure 19, can increase the size of array region (overlay area).

Conclusion as the associated memory array density (overlay area) of each embodiment of the NV NT switch of Nonvolatile nanotube memory node, NV NT block switch and sealing NVNT block switch

Figure 20 B concludes the unit size of some exemplary embodiments of above-mentioned memory array based on the type and the configuration of NV NT memory node.Figure 20 B also comprises corresponding figures 8D NV NT memory node numbering, so that reference is as the type of NV NT switch, NV NT block switch or the sealing NV NT block switch of NV memory node in each memory array.

Place and connect NFET and select transistorized word line (WL) and bit line (BL) to go up on the end face of array or near NV NT memory node produces more not intensive realization.Yet, place in advance on the surface of memory array of wiring or near NV NT memory node provides integrated easiness (integrated flexibility), comprise the insulation NV NT memory node that is used for being installed to the nonisulated chip of sealed package and uses various insulators combinations and interstitial area.The NV NT switch that this configuration generation and cmos circuit and NFET selection transistor integrate and the short development time of NV NT block switch.As shown in Figure 20 B, unit area (overlay area) in fact can be greater than fully-integrated structure, yet for example above-mentioned Fig. 9 A-9B, 10A-10B, and the working storage array of the described 16 bit memory arrays 9000 of 11A-11C of being relevant to produces the study of memory array manufacturing faster and acceleration.Note that cell density (overlay area) also depends at NV NT memory node is connected to when selecting the transistor source diffusion, is to use the neat also right and wrong of oneself from aliging binding post.

Place the fully integrated NV NT memory node under the bit line to produce the cell density (less relatively overlay area) that improves.Figure 20 B shows correlation unit zones different with regard to minimum dimension F.Some embodiment of comparatively dense memory cell have 6-8F relatively ²The estimation unit area of scope, it can be reached by the NV NT block switch of top shown in the fully-integrated Figure 20 of the having B and bottom contact.For the technology node of F=45nm, cellar area estimates to be in 0.012-0.016um ²Scope, for the technology node of F=22nm, cellar area estimates to be in 0.003-0.004um ²Scope reaches the technology node for F=10nm, and cellar area estimates to be in 0.0006-0.0008um ²Scope.NV NT block switch is scalable, and has manufactured the size of 22 to 45nm scopes.Zoom to F=10nm or even littler technology node, there is no known basic obstacle at present.

The cross point switches of relative comparatively dense

Non-volatile cross point switch matrix can be used for changing the interconnection of chip after manufacturing is finished.The NVNT block switch can be used for forming the non-volatile cross point switches of relative comparatively dense, to be used for for example reconfigurable logic of FPGA.Below be relevant to Figure 20 A-23C and describe the intensive non-volatile cross point switches that uses NV NT block switch.

Have from the intensive cross point switches structure of the first kind that snaps to the NV NT block switch of array routing

Based on the sub-cross point switches of Nonvolatile nanotube both-end illustration in Figure 21 of " picture frame " layout and the thin nanotube element of usage level direction, and corresponding to U.S. Patent application No.11/280, the sub-cross point switches of the both-end described in 786.Though the relative comparatively dense of " picture frame " embodiment (that is many can in small size, the manufacturing, shown in Figure 21; Have little overlay area), even can be made into the more intensive sub-switch of scalable Nonvolatile nanotube both-end.Reach among the U.S. Patent application No. (to be arranged) that is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " that submits to simultaneously with the application described in detail as mentioned above, with the thin nanotube element of the sub-nonvolatile nanotube blocks of vertical direction (3-D) both-end (NV NT block) switch substitution level direction (2-D), can produce still comparatively dense switch, it is useful in many application, for example electric wiring able to programme, nonvolatile memory, comprises array logic, FPGA and the logic of other application for example.

Figure 21 illustrates sub-Nonvolatile nanotube switch 21000 sectional views of picture frame both-end, comprises at the bottom of the back lining conducting element 21105 in the support insulator 21100 on the (not shown) and through hole 21110.Nonvolatile nanotube switch 21000 can repeatedly switch between ON and OFF state.Nanotube element 21125 contacts with the conducting element 21050 that forms one of double nano pipe switch 21000 terminals.But optional conductive element 21107 can be used for strengthening contacting between nanotube element 21125 and the conducting element 21105.In conducting element 21155 contact zones 21135 nanotube element 21125 around, use forming second two-terminal nanotube switches, 21000 terminals.Conducting element 21155 is separated with selecting conducting element 21107 and nanotube segment element 21125 by insulator 21120.In certain embodiments, two-terminal nanotube switches 21000 sizes are about 3F in the horizontal X direction, and are about 3F at vertical Y direction (not shown), and wherein F is the minimum lithographic printing qualification size on the particular technology node.The minimum interval is F between the proximity switches, makes two-terminal nanotube switches 21000 to put (not shown) with the cycle of 4F along X and Y direction.In certain embodiments, single two-terminal nanotube switches 21000 occupies 9F ²Area, and when in the array configurations that is placed in other switch gap minimum range F, then occupy 16F ²

Figure 22 A illustrates the plane of nonvolatile nanotube blocks switch matrix 22000 of the sub-nonvolatile nanotube blocks switch of four vertical direction (3-D) both-end (22100-1,22100-2,22100-3 and 22100-4) of 2 * 2 cross point switches array configurations.As shown in Figure 22 B and 22C, the example cross section XI-XI ' that passes the part of the NV NT block switch 22100-1 shown in Figure 22 A reaches the element that Y1-Y1 ' further illustrates the NV NT block switch of vertical direction (3-D) structure.Details and manufacture method corresponding to the sub-NV NT of the first kind both-end block switch of the sub-nonvolatile nanotube blocks switch of both-end 22100-1,22100-2,22100-3 and 22100-4 are described as mentioned above and in the patent documentation of being included in.NV NT block for example can use with the application submit to simultaneously be entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " U.S. Patent application No. (to be arranged) the layer described in the patent documentation of including in go up multiple spin coating or pass through spraying technology and deposit.

Line 22050-1 interconnection both-end NV NT block switch 22100-1 and 22100-2 shown in Figure 22 A, it forms (lower floor) contact, bottom and the sub-NV NT of each these both-end block switch has size F * F and F spaced apart.Line 22050-2 interconnection both-end NV NT block switch 22100-3 and 22100-4, it forms (lower floor) contact, bottom and the sub-NV NT of each these both-end block switch has size F * F and F spaced apart.

Though F represents to obtain the minimum feature size of maximum switch arrays density, size can be optionally used, and non-square-section can be used greater than F, for example rectangle and circle are so that obtain low ON resistance value or other required feature.For example, can make big switch obtaining the ON resistance value of 50 to 100 ohm of scopes, thus the characteristic impedance of matched transmission line (Zo).And, for example can form array, for example 100 * 100 or bigger greater than 2 * 2.

Line 22600-1 shown in Figure 22 A, by contact top (upper strata) contact interconnect both-end NV NT block switch 22100-1 and 22100-3, and the sub-NV NT of each both-end block switch has size F * F and F spaced apart.Line 22600-2 is by contact top (upper strata) contact interconnect both-end NV NT block switch 22100-2 and 22100-4, and the sub-NV NT of each both-end block switch has size F * F and F spaced apart.Line 22600-1 and 22600-2 are graphical on the surface of the insulator 22500 of filling in the zone between NV NT block switch.Though F represents to obtain the minimum feature size of maximum switch arrays density, can use size greater than F.

Figure 22 B illustrates via reaching along the sectional view X1-X1 ' of the line 22600-1 of directions X.The vertical orientations of the sub-NV NT of Z direction indication both-end block switch 22100-1, and the direction of also indicating the electric current (vertically) of ON state to flow.The sub-NV NT of both-end block switch 22100-1 comprises one section bottom (lower floor) contact 22050-1 ' as line 22050-1, top (upper strata) the contact 22400-1 that contacts with line 22600-1, and the NV NT block 22200-1 that contacts with bottom (lower floor) contact 22050-1 ' and top (upper strata) contact 22400-1.For example reach the U.S. Patent application No.11/280 that is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " that submits to simultaneously with the application as mentioned above, 786 and U.S. Patent application No. (to be arranged) described in the patent documentation of including in, NV NT block 22200-1 can repeatedly switch between ON and OFF state.

Figure 22 C illustrates via reaching along the sectional view Y1-Y1 ' of the line 22050-1 of Y direction.The vertical orientations of the sub-NV NT of Z direction indication both-end block switch 22100-1, and the direction of also indicating the electric current (vertically) of ON state to flow.The sub-NV NT of both-end block switch 22100-1 comprises one section bottom (lower floor) contact 22050-1 ' as line 22050-1, top (upper strata) the contact 22400-1 that contacts with circuit 22600-1, and the NV NT block 22200-1 that contacts with bottom (lower floor) contact 22050-1 ' and top (upper strata) contact 22400-1.Reach as mentioned above described in the patent documentation of including in, NV NT block 22200-1 can repeatedly switch between ON and OFF state.The manufacture method of NV NT block switch and array interconnect is included in the patent documentation in the institute of the U.S. Patent application No. (to be arranged) that is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " that for example submits to simultaneously with the application and to be described.

The size of the sub-NV NT of both-end block switch 22100-1,22100-2,22100-3 and 22100-4 is about F in the horizontal direction, and is about F in vertical Y direction, and wherein F is the size of the minimum lithographic printing qualification of particular technology node.The minimum interval is F between the proximity switches, makes the sub-NVNT block switch of both-end 22100-1,22100-2,22100-3 and 22100-4 to put with the periodicity of 2F along X and Y direction shown in Figure 22 A.Single two-terminal nanotube switches 22100-1,22100-2,22100-3 and 22100-4 occupy 1F ²Area, and when in the array configurations that is placed in other switch gap minimum range F, then occupy 4F ²Therefore, single two-terminal nanotube switches 22100-1,22100-2,22100-3 and 22100-4 are than the sub-switch of the both-end shown in Figure 21 21000 intensive 9 times.Have along X and Y direction at interval in the array configurations of the single switch of F, based on two-terminal nanotube switches 22100-1,22100-2,22100-3 and 22100-4 and have the array of the periodic Nonvolatile nanotube switch of 2F, occupying 4F ²Area, need 16F more in certain embodiments ²Area based on intensive 4 times of the array of the Nonvolatile nanotube switch of the sub-switch 21000 of both-end.F can be on the large scale scope convergent-divergent.F can be 250nm and bigger; F can be less than 100nm, for example 45nm and 22nm; Or be less than 10nm.As described in the patent documentation of being included in, be manufactured on and have the NV NT block channel length L that the 35nm by (upper strata) contact to the top, contact, bottom (lower floor) is limited at interval on vertical (Z) direction _SW-CHNV NT switch.L _SW-CHScope can be from＜10nm to greater than 250nm.

Size F is definite by technology node, for example 45nm.Obtain required NV NT block switch ON resistance value if nano tube structure density (number of nanotubes of per unit area) is enough high, NV NT block switch size can be for example F=45nm.Yet, when using minimum F * F switch size,, can use size greater than F if NV NT block switch resistance value is too high, increasing the quantity of nanotube in the NV NT block switch, and reach low NV NT block switch ON resistance value thus.Suppose that cmos driver is driving the input of cmos circuit capacitive character, so to the incoming level of next logical stage with track to track (at chip power supply voltage and with reference between (ground connection) voltage) swing, no matter the combined serial ON resistance value of NV NT block switch and FET raceway groove how.Yet, because the network RC time constant that the combination of serial resistance and interconnection capacitance value causes postpones may need to limit the ON resistance value of NV NT block switch.For example, if the time delay that routing path need be lacked, so in this example, the ON resistance of NV NT block switch just can be not more than the NMOS of 1k to 10k ohm and PMOS ON resistance 1/10th, use ON resistance limits to 100 ohm resistance to 1k ohm scope with NV NT block switch.Yet if do not need short time delay, so in this example, the ON resistance of NV NT block switch can equal the ON resistance of (or even greater than) NMOS and PMOS, herein in the scope of 1k ohm to 10k ohm.Reach the U.S. Patent application No.11/280 that is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " that submits to simultaneously with the application as mentioned above, 786 and U.S. Patent application No. (to be arranged) described in, NV NT block switch OFF resistance be generally 1G ohm and more than, and some devices are low to moderate 100M ohm.

NVNT block switch 22100-1,22100-2,22100-3 and 22100-4 are in the ON state when making in the non-volatile switch matrix 22000.In operation, these NV NT block switch switch to the OFF state usually.Then, this application judges which NV NT block switch switches to the ON state in the non-volatile switch matrix 22000, to form interconnection wiring.

In operation, be that the NV NT block switch of ON can all switch to OFF from ON simultaneously by starting all row during manufacturing, or can once switch delegation, or can once switch a NV NT block switch.In this example, delegation ground of switch switches to OFF from ON.NV NT block switch 22100-1 and 22100-3 switch to OFF by writing 0 (be also referred to as and wipe) operation from ON.At first, vertical line 22050-1 and 22050-2 are set and remain on for example reference voltage of 0 volt (ground connection).Then, horizontal line 22100-2 is set to 0 and remain on 0 volt, and horizontal line 22100-1 is from even 0 voltage of writing that fades to 4 to 8 volts of scopes for example of the reference voltage of for example 0 volt (ground connection).Reach as mentioned above described in the patent documentation of including in, even variable Rate can be in 1 to 10ns scope or slower, and the writing under 0 electric current of each switch of 1uA to 100uA scope, is in for example hundreds of nanoseconds or microsecond scope.Though described 2 * 2 arrays of NV NT block switch in this example, can use bigger N * M switch matrix, wherein N and M comprise hundreds of, thousands of or even more NV NT block switch.

In operation, arbitrary non-volatile electric programming and the combination that is connected of programming again between level and the horizontal path, all can use and write 1 (being also referred to as programming) the operation combination by electrically activated (going to the ON state from the OFF state) arbitrary NV NT block switch and realize, wherein the ON state of NVNT block switch 22100-1,22100-2,22100-3 and 22100-4 determines that vertical line 22050-1 and 22050-2 are connected (route) with electric wiring between horizontal line 22600-1 and the 2260-2.In this example, writing 1 operation writes with the voltage of 4 to 8 volts of scopes usually.As U.S. Patent application No.11/280,786 and U.S. Provisional Patent Application No.60/855, described in 109, even variable Rate can be in the following scope of 10ns or slower, and, be in for example hundreds of nanoseconds or microsecond scope the writing under 1 electric current of each switch of 1uA to 100uA scope.

As example, NV NT block switch 22100-1 can be in the ON state of connecting line 22600-1 and 22050-1, and NV NT block switch 22100-4 also can be in the ON state of connecting line 22600-2 and 22050-2.NV NT block switch 22100-2 and 22100-3 can be in for example OFF state.Many line can similarly connect.Figure 22 D that below illustrates shows the various interconnection that can use nonvolatile nanotube blocks switch matrix 22000 to form.

Figure 22 D illustrates one of four NV NT block switch and is in the ON state, and its excess-three switch is in non-volatile electric programming wiring (route) connection of OFF state.Also be shown as (in four two) NV NT block switch is in the ON state, and the non-volatile electric programming wiring (route) that all the other two switches are in the OFF state connects.Shown in Figure 22 D, selected (ON) NV NT block switch is to can be used for forming each vertically and the right single contact of horizontal line, or between a vertical line and two horizontal lines or multiple connection the between a horizontal line and two vertical lines.Can use three NV NT block switch to be in the combination that ON state and all the other switches are in OFF state (not shown), or all four NV NT block switch are in ON state (not shown), form the electric programming wiring of other NV (route) and connect.Though described 2 * 2 arrays of NV NT block switch in this example, can use bigger N * M switch matrix, wherein N and M comprise hundreds of, thousands of or even more NV NT block switch.Non-volatile electric programming wiring (route) connect Reprogrammable thousands of or more times, to change wiring (route) configuration.

In operation, be written into and after being in ON or OFF state at NV NT block switch, electric signal will be via the NV NT block switch that is in the ON state in wiring (route) interflow.Voltage level remains on writes 0 and write under 1 operational threshold.In this example, electronic signal is maintained at about under 4 volts.

Have from the intensive cross point switches structure of second class that snaps to the NV NT block switch of array routing

Nonvolatile nanotube blocks switch matrix 22000 is shown in the plane of above-mentioned Figure 22 A, and non-volatile nanotube blocks switch 22100-1 is the representative of NV NT block switch 22100-1,22100-2,22100-3 and 22100-4, it is shown in the sectional view of Figure 22 B and 22C, and demonstration first kind NV NT block switch, wherein summit (upper strata) contact 22400-1 forms, and the contact, upper strata is etched X of NV NT block 22200-1 and Y size that mask layer limits nonvolatile nanotube blocks switch 22100-1.

In another embodiment, eliminate and substitute contact, summit (upper strata) in the second class NV NT block switch with (upper strata) contact, summit and the array line of combination.For example, shown in following Figure 23, remove summit (upper strata) the contact 22400-1 shown in Figure 22 A-22C, and replace with the contact, summit (upper strata) in the zone (part) of array lines 23600-1.

Figure 23 A illustrates the plane of nonvolatile nanotube blocks switch matrix 23000 of the sub-nonvolatile nanotube blocks switch of four vertical direction (3-D) both-end (23100-1,23100-2,23100-3 and 23100-4) of 2 * 2 cross point switches array configurations.Pass the example cross section X2-X2 ' of the part NV NT block switch 23100-1 shown in Figure 23 A and the element that Y2-Y2 ' further illustrates the NV NT block switch of vertical direction shown in Figure 23 B and the 23C (3-D) structure.The details of the second class both-end NV NT block switch and manufacture method, it is corresponding to the sub-Nonvolatile nanotube switch of both-end 23100-1,23100-2,23100-3 and 23100-4, based on the NV NT block switch manufacturing described in the patent documentation of being included in.Yet, replace and use contact, top (upper strata) as etching mask to device NV NT block surface, and use the shape of contact, top (upper strata) and based on sacrifice (disposable use) the etching mask (not shown) of known industry pattern technology, to limit the X and the Y size of NV NT block areas, for example the NV NT block 23200-1 shown in Figure 23 A-23C.Then use the size of etching manufacture method qualification NVNT block 23200-1 preferable in the patent documentation of being included in, to form the NV NT block 23200-1 shown in Figure 23 A-23C.As the technology described in the patent documentation of being included in of the U.S. Patent application No. (to be arranged) that is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " that for example submits to simultaneously with the application, NV NT block can use a plurality of spin-coated layer or deposit by spraying.

Line 23050-1 interconnection shown in Figure 23 A forms the both-end NVNT block switch 23100-1 and the 23100-2 of (lower floor) contact, bottom, and the sub-NV NT of each these both-end block switch has size F * F and spaced apart F.Line 23050-2 interconnection forms the both-end NVNT block switch 23100-3 and the 23100-4 of (lower floor) contact, bottom, and the sub-NV NT of each these both-end block switch has size F * F and spaced apart F.Though F represents to obtain the minimum feature size of maximum switch arrays density, can optionally use size, and can use non-square-section, as above-mentioned for example rectangle and circle greater than F.And, for example can form array, for example 100 * 100 or bigger greater than 2 * 2.

Circuit 23600-1 interconnection both-end NV NT block switch 23100-1 and 23100-3 shown in Figure 23 A, also form for example contact, top (upper strata) of top (upper strata) contact 23600-1 ' simultaneously, and the sub-NV NT of each both-end block switch have size F * F and spaced apart F.Circuit 23600-2 interconnection both-end NV NT block switch 23100-2 and 23100-4, and form for example contact, top (upper strata) of top (upper strata) contact 23600-1 ', and the sub-NV NT of each both-end block switch has size F * F and spaced apart F.Circuit 23600-1 and 23600-2 are graphical on the surface of the insulator 23500 of filling in the zone between the sub-NV NT of both-end block switch.Though F represents to obtain the minimum feature size of maximum switch arrays density, can optionally use size, and can use non-square-section, as above-mentioned for example rectangle and circle greater than F.And, for example can form array, for example 100 * 100 or bigger greater than 2 * 2.

Figure 23 B illustrates and passes and along the sectional view X2-X2 ' of the line 23600-1 of directions X.The vertical orientations of the sub-NV NT of Z direction indication both-end block switch 23100-1, and also represent the direction that the electric current (vertically) of ON state flows.Direction is mobile up or down to note that electric current.The sub-NVNT block switch of both-end 23100-1 comprises bottom (lower floor) the contact 23050-1 ' by the formed zone of line 23050-1, by top (upper strata) the contact 23600-1 ' in the formed zone of line 23600-1 (part), and the NV NT block 23200-1 that contacts with bottom (lower floor) contact 23050-1 ' and top (upper strata) contact 23600-1 '.As the U.S. Patent application No.11/280 that is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " that for example submits to simultaneously with the application, 786 and U.S. Patent application No. (to be arranged) described in the patent documentation of including in, NV NT block 23200-1 can repeatedly switch between ON and OFF state.

Figure 23 C illustrates and passes and along the sectional view Y2-Y2 ' of the line 23050-1 of Y direction.The vertical orientations of the sub-NV NT of Z direction indication both-end block switch 23100-1, and also represent the direction that the electric current (vertically) of ON state flows.Direction is mobile up or down to note that electric current.The sub-NVNT block switch of both-end 23100-1 is included as bottom (lower floor) the contact 23050-1 ' in the zone (section) of line 23050-1, by formed top, zone (section) (upper strata) the contact 23600-1 ' of circuit 23600-1, and the NV NT block 23200-1 that contacts with bottom (lower floor) contact 23050-1 ' and top (upper strata) contact 23600-1 '.For example reach the U.S. Patent application No.11/280 that is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacture method " that submits to simultaneously with the application as mentioned above, 786 and U.S. Patent application No. (to be arranged) described in the patent documentation of including in, NV NT block 23200-1 can repeatedly switch between ON and OFF state.

The size of the sub-NV NT of both-end block switch 23100-1,23100-2,23100-3 and 23100-4 is about F in the horizontal direction, and is about F in vertical Y direction, and wherein F is the size of the minimum lithographic printing qualification of particular technology node.The minimum interval is F between the proximity switches, makes the sub-NVNT block switch of both-end 23100-1,23100-2,23100-3 and 23100-4 to put with the periodicity of 2F along X and Y direction shown in Figure 23 A.The sub-NV NT of single both-end block switch 23100-1,23100-2,23100-3 and 23100-4 occupy 1F ²Area, and when in the array configurations that is seated in other switch gap minimum range F, then occupy 4F ²

In operation, the electric switch characteristic of NV NT block switch 23100-1,23100-2,23100-3 and 23100-4 approximately is relevant to the identical of switch 22100-1,22100-2,22100-3 and 22100-4 description with above-mentioned.

In operation, the electric ON of Figure 22 D and above-mentioned corresponding NV NT block switch and OFF state illustrate the various non-volatile electric programming wiring (route) at the combination of the NV NT block switch 22100-1,22100-2,22100-3 and the 22100-4 that are in the NV NT block switch array 22000 in each ON and the OFF combinations of states.The combination of NV NT block switch 23100-1,23100-2,23100-3 and 23100-4 is corresponding to described in above-mentioned Figure 22 D in the NV NT block switch array 23000, and its difference is that NV NT block switch 23100-1,23100-2,23100-3 and 23100-4 correspond respectively to NV NT block switch 22100-1,22100-2,22100-3 and 22100-4; V circuit 23050-1 and 23050-2 correspond respectively to V circuit 22050-1 and 22050-2; And H circuit 23600-1 and 23600-2 correspond respectively to H circuit 22600-1 and 22600-2.

The patent documentation of being included in

The application relates to following application, and its full content is incorporated herein by reference, and is called " patent documentation of being included in ":

The U.S. Patent application No.10/128 that on April 23rd, 2002 submitted to, 118, be U.S. Patent No. 6,706,402 now, be entitled as " nanotube films and goods " (" Nanotube Films and Articles ");

The U.S. Patent application No.10/776 that on February 11st, 2004 submitted to, 572, it now is U.S. Patent No. 6,924,538, be entitled as " device and manufacture method thereof " (" Devices Having Vertically-Disposed Nano fabric Articles and Methods ofMaking the Same ") with nanostructured goods of arranged perpendicular;

The U.S. Patent application No.10/864 that on June 9th, 2004 submitted to, 186, it now is U.S. Patent No. 7,115,901, be entitled as " imitating device and its circuit and forming method thereof for non-volatile dynamo-electric " (" Non-Volatile Electromechanical Field Effect Devices and Circuits Using Same andMethods of Forming Same ");

The U.S. Patent application No.10/917 that on August 13rd, 2004 submitted to, 794, be U.S. Patent No. 7,115,960 now, be entitled as " based on the switch element of nanotube " (" Nanotube-Based SwitchingElements ");

The U.S. Patent application No.10/918 that on August 13rd, 2004 submitted to, 085, now be U.S. Patent No. 6,990,009, be entitled as " switch element " (" Nanotube-Based Switching Elements with Multiple Controls ") based on nanotube with multiple control;

The U.S. Patent application No.09/915 that submit to July 25 calendar year 2001,093, it now is U.S. Patent No. 6,919,592, be entitled as " electromechanical memory array and the manufacture method thereof of using the nanotube ribbon element " (" Electromechanical Memory Array Using Nanotube Ribbons and Method forMaking Same ");

The U.S. Patent application No.09/915 that submit to July 25 calendar year 2001,173, it now is U.S. Patent No. 6,643,165, be entitled as " with the dynamo-electric memory that circuit is selected in the unit that has of nanotube technology structure " (" Electromechanical Memory Having Cell Selection Circuitry ConstructedWith Nanotube Technology ");

The U.S. Patent application No.09/915 that submit to July 25 calendar year 2001,095, now be U.S. Patent No. 6,574,130, be entitled as " hybrid circuit " (" Hybrid CircuitHaving Nanotube Electromechanical Memory ") with the dynamo-electric memory of nanotube;

The U.S. Patent application No.10/033 that submit to December 28 calendar year 2001,323, be U.S. Patent No. 6,911,682 now, be entitled as " dynamo-electric three trace junction devices " (" Electromechanical Three-TraceJunction Devices ");

The U.S. Patent application No.10/033 that submit to December 28 calendar year 2001,032, now be U.S. Patent No. 6,784,028, be entitled as " manufacture methods of dynamo-electric three trace junction devices " (" Methods of MakingElectromechanical Three-Trace Junction Devices ");

The U.S. Patent application No.10/128 that on April 23rd, 2002 submitted to, 117, be U.S. Patent No. 6,835,591 now, be entitled as " methods of nanotube films and goods " (" Methods of Nanotube Filmsand Articles ");

The U.S. Patent application No.10/341 that on January 13rd, 2003 submitted to, 005, be entitled as " manufacture methods of carbon nano-tube film, layer, structure, ribbon element, element and goods " (" Methods of MakingCarbon Nanotube Films; Layers; Fabrics; Ribbons, Elements and Articles ");

The U.S. Patent application No.10/341 that on January 13rd, 2003 submitted to, 055, be entitled as " using thin metal layer " (" Methodsof Using Thin Metal Layers to Make Carbon Nanotube Films; Layers; Fabrics; Ribbons, Elements and Articles ") to make the method for carbon nano-tube film, layer, structure, ribbon element, element and goods;

The U.S. Patent application No.10/341 that on January 13rd, 2003 submitted to, 054, be entitled as " using preformed nanotube " (" Methods of Using Pre-formed Nanotubes to Make Carbon NanotubeFilms; Layers; Fabrics; Ribbons, Elements and Articles ") to make the method for carbon nano-tube film, layer, structure, ribbon element, element and goods;

The U.S. Patent application No.10/341 that on January 13rd, 2003 submitted to, 130, be entitled as " carbon nano-tube film, layer, structure, ribbon element, element and goods " (" Carbon Nanotube Films; Layers; Fabrics, Ribbons, Elements and Articles ");

The U.S. Patent application No.10/776 that on February 11st, 2004 submitted to, 059, now be United States Patent (USP) publication No.2004/0181630, be entitled as " device and manufacture method thereof " (" Devices Having Horizontally-Disposed Nano fabric Articles andMethods of Making the Same ") with nanostructured goods of horizontal arrangement;

The U.S. Patent application No.10/936 that on September 8th, 2004 submitted to, 119, now be United States Patent (USP) publication No.2005/0128788, be entitled as " graphical nanoscale articles and manufacture method thereof " (" PatternedNanoscopic Articles and Methods of Making the Same ");

The U.S. Provisional Patent Application No.60/836 that on August 8th, 2006 submitted to, 343, be entitled as " as the scalable Nonvolatile nanotube switch of electrical fuse alternative elements " (" Scalable Nonvolatile NanotubeSwitches as Electronic Fuse Replacement Elements ");

The U.S. Patent application No.11/280 that on November 15th, 2005 submitted to, 786, be entitled as " two-terminal nanotube device and system and manufacture method thereof " (" Two-Terminal Nanotube Devices and Systems andMethods of Making Same ");

The U.S. Patent application No.11/274 that on November 15th, 2005 submitted to, 967, be entitled as " memory array of using nanotube articles " (" Memory Arrays Using NanotubeArticles With Reprogrammable Resistance ") with Reprogrammable resistance;

The U.S. Patent application No.11/280 that on November 15th, 2005 submitted to, 599, be entitled as " the non-volatile shadow door bolt that uses nanotube switch " (" Non-Volatile Shadow Latch Using a NanotubeSwitch ");

The United States Patent (USP) 4 that submit to July 31 nineteen ninety, 944,836, be entitled as " being used for producing the chemically mechanical polishing of coplane metal/insulator film " (" Chem-Mech Polishing for Producing CoplanarMetal/Insulator Films on a Substrae ") at substrate; And

The United States Patent (USP) 4,256,514 that on March 17th, 1981 submitted to is entitled as " method that forms the narrow dimension district on body " (" Method for Forming a Narrow Dimensioned Region on a Body ").

Do not departing under spirit of the present invention and the essential characteristic, the present invention can other particular form embody.Thereby various embodiments of the present invention can be considered as exemplary and non-limiting in every respect.

Claims

1. clad nano pipe switch comprises:

(a) nanotube element comprises unjustified a plurality of nanotube, and this nanotube element has an end face, a bottom surface and a plurality of side;

(b) first and second conducting terminal, it contacts with described nanotube element, wherein said first conducting terminal places and covers in fact the whole top of described nanotube element, and wherein said second conducting terminal contacts the part of the bottom surface of described nanotube element at least; And

(c) control circuit, itself and described first and second conducting terminal electric connection also can apply electro photoluminescence to it,

Wherein apply corresponding a plurality of electro photoluminescence in response to described control circuit to described first and second conducting terminal, described nanotube element can switch between a plurality of electronic states, and

Wherein for each different electronic state of a plurality of electronic states, described nanotube element provides the electrical path that has corresponding different resistance between described first and second conducting terminal.

2. clad nano pipe switch as claimed in claim 1 is characterized in that described first conducting terminal also places and cover in fact at least one side of described a plurality of sides.

3. clad nano pipe switch as claimed in claim 1 is characterized in that, described first conducting terminal also places and cover in fact described a plurality of side.

4. clad nano pipe switch as claimed in claim 3 further comprises an insulator layer that contacts with the bottom surface of described nanotube element, and described insulator layer and described second conducting terminal cover the whole bottom surface of described nanotube element in fact together.

5. clad nano pipe switch as claimed in claim 1 further comprises an insulator layer, and it contacts one of at least with one of the described bottom surface of described nanotube element and side of described nanotube element.

6. clad nano pipe switch as claimed in claim 5 is characterized in that described insulator layer comprises SiO ₂, SiN and Al ₂O ₃One of them.

7. clad nano pipe switch as claimed in claim 1 further comprises a passivation layer of described at least first conducting terminal of covering, and described passivation layer makes described first and second conducting terminal and described nanotube element to described environmental sealing in fact.

8. clad nano pipe switch as claimed in claim 7 is characterized in that described passivation layer comprises SiO ₂, SiN, Al ₂O ₃, polyimides, phosphosilicate glass oxide, polyethylene fluoride, polypropylene carbonate and polybutene carbonate one of them.

9. clad nano pipe switch as claimed in claim 1 is characterized in that described second conducting terminal contacts the whole bottom surface of described nanotube element in fact.

10. clad nano pipe switch as claimed in claim 1, it is characterized in that, described first and second conducting terminal comprises the conductive material that independently is selected from by the following group that constitutes separately, comprises Ru, Ti, Cr, Al, Al (Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu, TiPd, PbIn, TiW, RuN, RuO, TiN, TaN, CoSi _xAnd TiSi _x

11. a clad nano pipe switch comprises:

(a) nanotube element comprises unjustified a plurality of nanotube, and described nanotube element has end face and bottom surface;

(b) first and second conducting terminal, it contacts with described nanotube element and is spaced apart from each other;

(c) first insulator layer, its end face with described nanotube element contacts;

(d) second insulator layer, its bottom surface with described nanotube element contacts, wherein said first and second conducting terminal with described first and second insulator layer in fact around described nanotube element; And

(e) control circuit also can apply electro photoluminescence to it with described first and second conducting terminal electric connection,

12. clad nano pipe switch as claimed in claim 11 is characterized in that, the spaced apart gap of end face of described first insulator layer of at least a portion and described nanotube element.

13. clad nano pipe switch as claimed in claim 12 is characterized in that, a spaced apart gap, bottom surface of described second insulator layer of at least a portion and described nanotube element.

14. clad nano pipe switch as claimed in claim 11 is characterized in that described first and second conducting terminal contacts the bottom surface of described nanotube element, and wherein said first insulator layer contacts with the whole top of described nanotube element.

15. clad nano pipe switch as claimed in claim 11 is characterized in that described first and second conducting terminal contacts the end face of described nanotube element.

16. clad nano pipe switch as claimed in claim 11 is characterized in that described first conducting terminal contacts the bottom surface of described nanotube element, and described second conducting terminal contacts the end face of described nanotube element.

17. clad nano pipe switch as claimed in claim 11 is characterized in that described first and second insulator layer comprises the insulating materials that independently is selected from by the following group that constitutes separately, comprises SiO ₂, SiN and Al ₂O ₃

18. clad nano pipe switch as claimed in claim 11, it is characterized in that, described first and second conducting terminal comprises the conductive material that independently is selected from by the following group that constitutes separately, comprises Ru, Ti, Cr, Al, Al (Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu, TiPd, PbIn, TiW, RuN, RuO, TiN, TaN, CoSi _xAnd TiSi _x

19. a clad nano pipe switch comprises:

(c) first insulator layer places on the end face of described nanotube element and spaced away;

(d) second insulator layer places under the bottom surface of described nanotube element and spaced away, wherein said first and second conducting terminal with described first and second insulator layer in fact around described nanotube element; And

20. clad nano pipe switch as claimed in claim 19 is characterized in that described first and second insulator layer comprises the insulating materials that independently is selected from by the following group that constitutes separately, comprises SiO ₂, SiN and Al ₂O ₃

21. clad nano pipe switch as claimed in claim 19, it is characterized in that, described first and second conducting terminal comprises the conductive material that independently is selected from by the following group that constitutes separately, comprises Ru, Ti, Cr, Al, Al (Cu), Au, Pd, Pt, Ni, Ta, W, Cu, Mo, Ag, In, Ir, Pb, Sn, TiAu, TiCu, TiPd, PbIn, TiW, RuN, RuO, TiN, TaN, CoSi _xAnd TiSi _x