CN101542631B

CN101542631B - Nonvolatile resistive memories, latch circuits, and operation circuits having scalable two-terminal nanotube switches

Info

Publication number: CN101542631B
Application number: CN2007800358842A
Authority: CN
Inventors: C·L·伯廷; T·鲁克斯; J·W·沃德; F·郭; S·L·孔瑟科; M·梅恩霍德
Original assignee: Nantero Inc
Current assignee: Nantero Inc
Priority date: 2006-08-08
Filing date: 2007-08-08
Publication date: 2012-06-20
Anticipated expiration: 2027-08-08
Also published as: CN101541489B; CN101541489A; CN101542631A; CN101558449A; CN101558449B

Abstract

A non-volatile resistive memory is provided. The memory includes at least one non-volatile memory cell and selection circuitry. Each memory cell has a two-terminal nanotube switching device having and a nanotube fabric article disposed between and in electrical communication with conductive terminals. Selection circuitry is operable to select the two-terminal nanotube switching device for read and write operations. Write control circuitry, responsive to a control signal, supplies write signals to a selected memory cell to induce a change in the resistance of the nanotube fabric article, the resistance corresponding to an informational state of the memory cell. Resistance sensing circuitry in communication with a selected memory cell, senses the resistance of the nanotube fabric article and provides the control signal to the write control circuitry.; Read circuitry reads the corresponding informational state of the memory cell. A non-volatile latch circuit and a non-volatile register file configuration circuit for use with a plurality of non-volatile register files are also provided.

Description

Nonvolatile resistive memories, latch circuit and operating circuit with scalable two-terminal nanotube switches

MULTIPLE-BLADE

The application requires to protect the interests under the united states patent law § 119 (e) of following application, and its full content is incorporated into this by reference:

The U.S. Provisional Patent Application No.60/836 that on August 8th, 2006 submitted to; 343, be entitled as " as the scalable Nonvolatile nanotube switch of electrical fuse replacement element " (" Scalable NonvolatileNanotube Switches as Electronic Fuse Replacement Elements ");

The U.S. Provisional Patent Application No.60/836 that on August 8th, 2006 submitted to, 437, be entitled as " Nonvolatile nanotube diodes " (" Nonvolatile Nanotube Diode ");

The U.S. Provisional Patent Application No.60/840 that on August 28th, 2006 submitted to, 586, be entitled as " Nonvolatile nanotube diodes " (" Nonvolatile Nanotube Diode ");

The U.S. Provisional Patent Application No.60/855 that on October 27th, 2006 submitted to, 109, be entitled as " nonvolatile nanotube blocks " (" Nonvolatile Nanotube Blocks ");

The U.S. Provisional Patent Application No.60/918 that on March 16th, 2007 submitted to; 388, be entitled as " memory storage element and cross point switches and the array thereof that use nonvolatile nanotube blocks " (" MemoryElements and Cross Point Switches and Arrays of Same Using NonvolatileNanotube Blocks ").

The application is the continuation application of following application, and requires the right of priority under the united states patent law § 120, and its full content is incorporated into this by reference:

The U.S. Patent application No.11/280 that on November 15th, 2005 submitted to; 786, be entitled as " two-terminal nanotube device and system and manufacturing approach thereof " (" Two-Terminal Nanotube Devices AndSystems And Methods Of Making S ame ");

The U.S. Patent application No.11/274 that on November 15th, 2005 submitted to; 967, be entitled as " use and have the memory array of the nanotube that can adapt journey resistance " (" Memory Arrays Using NanotubeArticles With Reprogrammable Resistance "); And

The U.S. Patent application No.11/280 that on November 15th, 2005 submitted to, 599, be entitled as " the non-volatile shadow door bolt that uses nanotube switch " (" Non-Volatile Shadow Latch Using ANanotube Switch ").

The application is relevant to the following application of submitting to simultaneously, and its full content is incorporated into this by reference:

U.S. Patent application No. (to be arranged) is entitled as " latch circuit and the function circuit of replacing the scalable Nonvolatile nanotube switch of tool of element as electrical fuse " (" Latch Circuits andOperation Circuits Having Scalable Nonvolatile Nanotube Switches asElectronic Fuse Replacement Elements ");

U.S. Patent application No. (to be arranged) is entitled as " Nonvolatile resistive memories of tool scalable two-terminal nanotube switches " (" Nonvolatile Resistive Memories Having ScalableTwo-Terminal Nanotube Switches ");

U.S. Patent application No. (to be arranged) is entitled as " memory element and cross point switches and the array thereof that use nonvolatile nanotube blocks " (" Memory Elements and Cross Point Switchesand Arrays of Same Using Nonvolatile Nanotube Blocks ");

U.S. Patent application No. (to be arranged) is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacturing approach " (" Nonvolatile Nanotube Diodes andNonvolatile Nanotube Blocks and Systems Using Same and Methods ofMaking Same ");

U.S. Patent application No. (to be arranged) is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacturing approach " (" Nonvolatile Nanotube Diodes andNonvolatile Nanotube Blocks and Systems Using Same and Methods ofMaking Same "); And

U.S. Patent application No. (to be arranged) is entitled as " Nonvolatile nanotube diodes and nonvolatile nanotube blocks and system thereof and its manufacturing approach " (" Nonvolatile Nanotube Diodes andNonvolatile Nanotube Blocks and Systems Using Same and Methods ofMaking Same ").

Technical field under the invention

The present invention relates generally to the field of nanotube switching element.

Scalable non-volatile latch circuit

Semicon industry is used for fuse or anti-fuse the nonvolatile storage of logic state.The Nonvolatile resistance sexual state of fuse (or anti-fuse) (being in conduction state or non-conductive state) is used to indicate first or second logic state.Latch circuit becomes the Nonvolatile resistive state exchange of fuse (or anti-fuse) the corresponding electrical voltage level of

presentation logic

1 or 0.

In one type fuse (being sometimes referred to as laser fuse), fuse element is formed by metal or polycrystalline silicon material.Fuse is programmed (quilt is blown or becomes non-conductive) through laser ablation (ablation), and corresponding latch circuit reads the non volatile state of this fuse, like United States Patent(USP) No. 5,345, and 110 descriptions, its full content is incorporated into this by reference.

Semicon industry has used more flexible and more intensive electrically programmable fuse (e-fuse; Electric fuse) element replaces laser fuse; Yet; Electric fuse needs the program current of milliampere (milli-Ampere) scope usually and is difficult to new comparatively dense technology node, and for example 90nm, 65nm, 45nm, and more intensive person are contracted to less physical size and lower program current level.

Semicon industry has also used more flexible and more intensive electric programmable antifuse (a-fuse) element to replace laser fuse.Anti-fuse is reduced to low microampere (micro-Ampere) scope (for example 1-10 μ A) with program current, yet program voltage is usually in 8 to 12 volt range.Anti-fuse is difficult to be contracted to less physical size and lower program current level to new comparatively dense technology node.Use in the United States Patent(USP) No. 6,570,806 that is latched in people such as Bertin of fuse and anti-fuse and describe, its full content is incorporated into this by reference.

Expectation can provide scalable element; It can be used as fuse or anti-fuse or fuse and anti-fuse or can repeatedly or more generally between ON and OFF state, switch element repeatedly in switching (toggle) between fuse and anti-fuse; And corresponding latch circuit, its with silicon technology can be easily integrated, can be contracted to less physical size, use a nanoampere level low current value or a low microampere scope to programme and can be contracted to lower program current (5 volts reach lower).

In application-specific, it is desirable that scalable element is provided, and it can be used between ON and OFF state, switch, and selects the register file level (stage) in (bypass) a series of register files with selection or cancellation.If this scalable element is used as fuse, then corresponding register file level can be cancelled selection (bypass), from a series of, to eliminate defective register file level.

In application-specific, it is desirable that scalable element can be provided, and it can be used between ON (conducting) and OFF (ending) state, switch, so that the information state in the storage unit to be provided.In addition, in other was used, it was desirable that scalable element is provided, and it can be used in a plurality of conduction states, switch, so that a plurality of information states in the storage unit to be provided.Desirable especially with existing integrated this element of memory technology.Existing commercial techniques available is not non-volatile (but not being random access and limited capability that have low-density, high production cost and repeatedly write with the high reliability of circuit function) usually, is exactly volatibility (and have complicated system design or have low-density).Desirable nonvolatile memory (at least some purposes) is the storer that allows the nonvolatile storage of a plurality of information states, and wherein storage unit can optionally be activated and correctly be programmed for information state.

Summary of the invention

The present invention provides and comprises scalable latch circuit, nonvolatile memory and function circuit, and it is based on nano structural material and scalable Nonvolatile nanotube switch.

According to an aspect of the present invention, a kind of non-volatile latch circuit is provided, comprises: input end, can the input logic state; Output terminal can the output logic state; One nanotube switching element has and is arranged at two nano tube structure goods between the conductive contact, and these nano tube structure goods are electrically connected with two conductive contacts.This nanotube switching element can be at relatively low resistance states and is switched between the higher-resistivity state relatively, and can keep relatively low or relative higher-resistivity state non-volatilely.This non-volatile latch circuit comprises the volatibility latch circuit; It has at least one semiconductor element that electrically is arranged between input end and the nanotube switching element, and this non-volatile latch circuit can receive and volatibility ground stores the logic state that inputs to input end.When nanotube switching element was in relatively low resistance states, this volatibility latch circuit kept first logic state and exports first logic state at output terminal.When nanotube switching element was in relative higher-resistivity state, this volatibility latch circuit remained on second logic state of output terminal output.

In one embodiment of the invention, the electronics latch circuit comprises phase inverter (INV) circuit, and this inverter circuit comprises a plurality of field effect transistors.

In another embodiment of the present invention, this nanotube switching element can be at relatively low resistance states and is repeatedly switched between the higher-resistivity state relatively.

In another embodiment of the present invention, this electronics latch circuit is converted to relative higher voltage level with the relatively low resistance states of nanotube switching element, and it is corresponding to first logic state in output terminal output.The electronics latch circuit is converted to relatively low voltage level with the relative higher-resistivity state of nanotube switching element, and it is corresponding to second logic state in output terminal output.

In another embodiment of the present invention, non-volatile latch circuit is electrically connected with a storage unit.When non-volatile latch circuit was exported first logic state, storage unit was effectively, and when non-volatile latch circuit was exported second logic state, storage unit was invalid.

In another embodiment of the present invention, non-volatile latch circuit comprises the redundant circuit that is used for storage unit, and can be when storage unit be unavailable this storage unit of bypass.

In another embodiment of the present invention, non-volatile latch circuit is electrically connected with a storage unit, and can store first and second memory states.The first memory state is input to input end as first logic state, and is kept non-volatilely and be output as first logic state by non-volatile latch circuit.The second memory state is input to input end as second logic state, and is kept non-volatilely and be output as second logic state by non-volatile latch circuit.

In another embodiment of the present invention, non-volatile latch circuit comprises the redundant circuit that is used for storage unit, and can keep corresponding respectively to first and second logic states of first and second memory states non-volatilely.

In another embodiment of the present invention, storage unit comprises the storage unit that is in the NRAM array.

In another embodiment of the present invention, non-volatile latch circuit keeps one of first and second logic states with the mistake in the correcting storing unit.

In another embodiment of the present invention, non-volatile latch circuit is electrically connected with a storage unit.Electro photoluminescence in the input end input comprises a time dependent electro photoluminescence.Electro photoluminescence in output terminal output comprises a time dependent electro photoluminescence.Through between the time dependent electro photoluminescence of input end and output terminal, producing controllable delay, the operation of non-volatile latch circuit control store circuit.

In another embodiment of the present invention, non-volatile latch circuit produces controllable delay, and this controllable delay comprises the essence dual mode signal with fall time that selected rise time of essence and essence selectes.

In another embodiment of the present invention, nanotube switching element comprises fuse once able to programme, and this fuse once able to programme can only switch to relative higher-resistivity state from relatively low resistance states.

According to a further aspect in the invention, provide a kind of being used for to pile configuration circuit with the non volatile register that a plurality of non volatile register heaps use.This non volatile register heap configuration circuit comprises: Input voltage terminal; Select circuit; A plurality of nanotube fuse elements, it is electrically connected with Input voltage terminal.Each nanotube fuse element is electrically connected with one of a plurality of non volatile register heaps and selection circuit.Each nanotube fuse element comprises nano tube structure goods and two conductive contacts, and the nano tube structure goods are set between two conductive contacts and with two conductive contacts and are electrically connected.In response to electro photoluminescence, the nanotube fuse element can switch to cut-off state from conducting state, and conducting state is corresponding to the relatively low resistance between first and second ends, and cut-off state is corresponding to the relatively low resistance between two conductive contacts.When the nanotube fuse element was in conducting state, corresponding non volatile register heap was effectively and at Input voltage terminal electro photoluminescence to be responded.When the nanotube fuse element is in cut-off state, corresponding non volatile register heap be invalid and at Input voltage terminal to not reaction of electro photoluminescence.Select circuit can electro photoluminescence be applied to each of selected nanotube fuse element, with the corresponding register file of bypass optionally.

In another embodiment of the present invention,, select optionally this register file of bypass of circuit in response to one of a plurality of register files defectiveness.

In another embodiment of the present invention, when one of a plurality of nanotube fuse elements were in conducting state, corresponding non volatile register heap can be operated with a plurality of information states in response to the electro photoluminescence on the Input voltage terminal.

In another embodiment of the present invention, the nanotube fuse element is once able to programme.

According to a further aspect in the invention, a kind of nonvolatile memory comprises: bit line; Word line; At least one non-volatile memory cells.Each non-volatile memory cells has: two-terminal nanotube switches device, the nano tube structure goods that it comprises first and second conducting terminals and is arranged between first and second conducting terminals and is electrically connected with it.Each storage unit also has the unit and selects circuit, and it is electrically connected with bit line and word line to select this two-terminal nanotube switches device to read and write operation in response to the activation one of at least of bit line and word line.This nonvolatile memory comprises write control circuit; It is reacted in order to the supply write signal to selected memory cell to control signal; With the nano tube structure goods changes in resistance of inducting, so that the value of nano tube structure goods resistance is corresponding to the information state of storage unit.This nonvolatile memory comprises the resistance sensing circuit, and it is electrically connected with selected non-volatile memory cells, offers write control circuit in order to the resistance of reading the nano tube structure goods and with control signal.And this nonvolatile memory comprises and reads circuit that it is electrically connected with selected non-volatile memory cells, in order to read the corresponding informance state of this storage unit.

In another embodiment of the present invention, first conducting terminal of nanotube switch device selects circuit to be electrically connected with the unit, and second conducting terminal of nanotube switch device is electrically connected with reference voltage line.

In another embodiment of the present invention, write control circuit is electrically connected with bit line and word line.

In another embodiment of the present invention, first conducting terminal of nanotube switch device receives the write signal by the write control circuit supply, and being electrically connected one of at least of second conducting terminal of nanotube switch device and word line and bit line.

In another embodiment of the present invention, the supply write signal comprises: supply has the electro photoluminescence of selected voltage.

In another embodiment of the present invention, the supply write signal comprises: supply has the electro photoluminescence of selected electric current.

In another embodiment of the present invention, nanotube switching element further comprises first and second insulator regions, and first and second insulator regions are arranged at the two opposite sides of nano tube structure goods basically.

In another embodiment of the present invention, first and second insulator regions comprise one of at least dielectric substance.

In another embodiment of the present invention, the spaced apart gap of at least a portion of one of at least a portion of nano tube structure goods and first and second insulator regions.

In another embodiment of the present invention, the information state of storage unit can repeatedly be programmed and wiped.

In another embodiment of the present invention; Write control circuit comprises the circuit that is used to write at least three write signals; Each of these at least three write signals is the signal of the corresponding resistance value in the nano tube structure goods of can inducting, and this resistance value is different from the resistance value corresponding to other write signal.

In another embodiment of the present invention, the corresponding resistance value of being inducted by at least three write signals comprises a plurality of low-resistance values and a high resistance.

In another embodiment of the present invention, a plurality of low-resistance values from about 1 kilo-ohm to the scope of about 1 megaohm, and wherein high resistance is at least 100 megaohms.

In another embodiment of the present invention, write control circuit comprises in order to write four write signals makes storage unit can store the circuit of one of first information state, second information state, the 3rd information state, the 4th information state.

In another embodiment of the present invention; The resistance sensing circuit comprises feedback circuit; This feedback circuit is electrically connected with selected non-volatile memory cells and has a reference electrode resistance; This feedback circuit can: resistance and the reference electrode resistance of the nano tube structure goods of selected non-volatile memory cells are made comparisons, and stop that optionally write signal gets into the non-volatile memory cells of selecting.

In another embodiment of the present invention, the value of the resistance of nano tube structure goods is selected from relatively low resistance value and one of relative high electrical resistance value.

In another embodiment of the present invention, relatively low resistance value is corresponding to first information state, and relative high electrical resistance value is corresponding to second information state.

In another embodiment of the present invention, the supply write signal comprises: with a plurality of potential pulses continuous, that increment ground changes of selected interval supply.

In another embodiment of the present invention, after each potential pulse of write control circuit supply, feedback circuit is read the resistance of nano tube structure goods and the resistance and the reference electrode resistance of nano tube structure goods is made comparisons.

In another embodiment of the present invention, nonvolatile memory can carry out one first write operation, and wherein applying potential pulse is a relatively low resistance value up to the resistance that feedback circuit reads into the nano tube structure goods, and optionally stops write signal.

In another embodiment of the present invention, nonvolatile memory can carry out one second write operation, and wherein applying potential pulse is a relative high electrical resistance value up to the resistance that feedback circuit reads into the nano tube structure goods, and optionally stops write signal.

In another embodiment of the present invention, nanotube switching element comprises nanotube fuse once able to programme, and these nano tube structure goods only can switch to relative higher-resistivity state from relatively low resistance states.

In another embodiment of the present invention, write control circuit is selected the reference electrode resistance from the resistance value of a scope.

In another embodiment of the present invention, when the resistance value of nanotube switch goods approximated the reference electrode resistance, feedback circuit stopped that optionally the write signal on the bit line gets into the nanotube switch device of selected non-volatile memory cells.

In another embodiment of the present invention; Read circuit and comprise sense amplifier circuit; And the resistance sensing circuit is electrically connected with sense amplifier circuit; The resistance sensing circuit is reacted to sense amplifier circuit, to write control circuit control signal being provided, thereby write control circuit is stopped to selected non-volatile memory cells supply write signal.

In another embodiment of the present invention, the control signal that offers the resistance sensing circuit by sense amplifier circuit optionally makes the write control circuit nano tube structure goods changes in resistance that stops to induct.

In another embodiment of the present invention, the value of nano tube structure goods resistance is selected from one of a plurality of resistance values that comprise a plurality of low-resistance values and a relative high electrical resistance value.

In another embodiment of the present invention, after each potential pulse of write control circuit supply, sense amplifier circuit detects the resistance value of nano tube structure goods.

In another embodiment of the present invention, nonvolatile memory can carry out first write operation, and wherein potential pulse is provided to selected non-volatile memory cells, up to sense amplifier circuit detect a plurality of low-resistance values one of at least.

In another embodiment of the present invention; When sense amplifier circuit in selected storage unit, detect a plurality of low-resistance values one of at least the time; The resistance sensing circuit is reacted to sense amplifier circuit, write control circuit is stopped to write the information state of selected storage unit.

In another embodiment of the present invention, nonvolatile memory can carry out second write operation, and wherein potential pulse is provided to selected non-volatile memory cells, up to detecting relative high electrical resistance.

In another embodiment of the present invention; When sense amplifier circuit detects relative high electrical resistance value in selected non-volatile memory cells; The resistance sensing circuit is reacted to sense amplifier circuit, write control circuit is stopped to write the information state of selected storage unit.

In another embodiment of the present invention, nanotube switching element comprises nanotube fuse once able to programme, and nanotube fuse once able to programme has the nano tube structure goods that only can switch to second resistance value from first resistance value.

The accompanying drawing simple declaration

In the accompanying drawings:

Figure 1A is the schematic diagram of non volatile register heap.

Figure 1B is the schematic diagram of non volatile register heap level circuit.

Fig. 1 C is result's the synoptic diagram that is used for the loop-around data of Nonvolatile nanotube switch according to an embodiment of the invention.

Fig. 2 is the representative synoptic diagram that has the non volatile register heap of additional redundancy non volatile register heap level and Figure 1A of the selection circuit of correspondence according to another embodiment of the present invention.

Fig. 3 A-3C be according to other embodiments of the present invention when forming final non volatile register heap, be used for selecting or the representative synoptic diagram of the switch of (bypass) non volatile register heap level is selected in cancellation.

Fig. 4 is the latch circuit synoptic diagram of laser fuse breech lock according to another embodiment of the present invention, and it can be used as the part of non volatile register heap circuit shown in Figure 2.

Fig. 5 illustrates the synoptic diagram of the waveform that is used for the performed operation of latch circuit shown in Figure 4 according to another embodiment of the present invention.

Fig. 6 A-6D illustrates the synoptic diagram of patterned according to another embodiment of the present invention nanostructured resistor.

Fig. 7 illustrates the synoptic diagram of the fuse latches of using electrical fuse or electron back fuse according to another embodiment of the present invention, and it can be used as the part of non volatile register heap circuit shown in Figure 2.

Fig. 8 illustrates and uses the synoptic diagram of Nonvolatile nanotube switch as the fuse latches of programmed element according to another embodiment of the present invention, and it can be used as the part of non volatile register heap circuit shown in Figure 2.

Fig. 9 A-D illustrates the sectional view and the SEM planimetric map of Nonvolatile nanotube switch according to other embodiments of the present invention.

Figure 10 A illustrates the diagrammatic sketch of several Nonvolatile nanotube switches of the different passage lengths of the convergent-divergent that has the illustration erasing voltage according to another embodiment of the present invention.

Figure 10 B illustrates illustration erasing voltage according to another embodiment of the present invention and wipes the diagrammatic sketch of Nonvolatile nanotube switch that electric current is the function of time.

Figure 10 C illustrates the diagrammatic sketch of the nanotube switch of measured ON state electricity group and OFF state resistance in 100 cycles of illustration according to another embodiment of the present invention.

Figure 11 illustrates the synoptic diagram of configuration control register according to another embodiment of the present invention.

Figure 12 illustrates alternative (to Fig. 2) synoptic diagram of the non volatile register heap of the Figure 1A that has additional redundancy non volatile register heap level and corresponding selection circuit according to another embodiment of the present invention.

Figure 13 A illustrates alternative (to Figure 12) synoptic diagram of the non volatile register heap of the Figure 1A that has additional redundancy non volatile register heap level and corresponding selection circuit according to another embodiment of the present invention.

Figure 13 B illustrates the circuit diagram of the non-volatile configuration control register that is used for Figure 13 A of this embodiment according to the present invention.

Figure 14 A illustrates according to another embodiment of the present invention through synchronous register file framework applications.

Figure 14 B illustrates has the controlled delay circuit according to another embodiment of the present invention with the synchronous register file framework of the warp of optimization clock sequential.

Figure 15 A-E illustrates according to other embodiments of the present invention CPU and the key between high-speed cache through the example of synchronous sequence.

Figure 15 F-H illustrates the optimization sequential of using the may command delay circuit between CPU and high-speed cache according to other embodiments of the present invention.

Figure 16 illustrates the delay control circuit that will be used for sequential control based on the breech lock of Nonvolatile nanotube switch according to other embodiments of the present invention.

Figure 17 A illustrate according to other embodiments of the present invention change the drive circuit of the state of the Nonvolatile nanotube switch in the latch circuit in order to the working voltage source.

Figure 17 B illustrates the drive circuit that according to other embodiments of the present invention the voltage source in order to use the belt current restriction changes the state of the Nonvolatile nanotube switch in the latch circuit.

Figure 17 C illustrates the drive circuit that according to other embodiments of the present invention the voltage source that is used for using electric current to be controlled by current mirror changes the state of the Nonvolatile nanotube switch in the latch circuit.

Figure 17 D illustrates the Nonvolatile nanotube switch resistance control circuit that the NRAM array element is urged to predetermined resistance according to other embodiments of the present invention.

Figure 17 E illustrates the circuit that is integrated into Figure 17 D in the nram memory system according to other embodiments of the present invention.

Figure 18 A illustrates the ON resistance value of manufacturing state Nonvolatile nanotube switch according to other embodiments of the present invention.

Figure 18 B illustrates ON and OFF resistance value at 50 all after date Nonvolatile nanotube switches according to other embodiments of the present invention.

Figure 19 A illustrates the example of a plurality of nanotube switch of on selected voltage level, programming according to other embodiments of the present invention.

Figure 19 B illustrates the example corresponding to a plurality of nanotube switch through programming of each read current of one volt of bit line read-out voltage that has according to other embodiments of the present invention.

Figure 19 C illustrates the example of a plurality of nanotube switch of in selected resistance range (wherein resistance value is corresponding to the read current on one volt of Figure 19 B), operating of according to the present invention this embodiment.

Figure 19 D illustrates intermediate value current level and the example of corresponding saturated current level on the selected voltage level of this embodiment according to the present invention.

Figure 19 E illustrates the example of the intermediate value saturated current level on the selected intermediate value switch ON state resistance level of this embodiment according to the present invention.

Figure 20 illustrates series circuit according to an embodiment of the invention.

Figure 21 illustrates parallel circuit according to another embodiment of the present invention.

Figure 22 illustrates combined serial/parallel circuit according to another embodiment of the present invention.

Figure 23 A illustrates NFlash storer synoptic diagram according to another embodiment of the present invention.

Figure 23 B illustrates NFlash storer synoptic diagram according to another embodiment of the present invention.

Figure 24 illustrates according to another embodiment of the present invention the planimetric map corresponding to the NFlash storer.

Figure 25 illustrates the sectional view of NAND subarray according to another embodiment of the present invention.

Figure 26 A illustrates electronically controlled according to another embodiment of the present invention resistance in series network, and wherein nanotube resistors in series network uses programming or erase operation to form electronically or be tuning.

Figure 26 B illustrates the synoptic diagram of nanotube resistors in series equivalent electrical circuit according to another embodiment of the present invention.

Figure 27 illustrates according to another embodiment of the present invention the chip power voltage regulator based on the electronic tuning of nanotube.

Figure 28 A illustrates and forms electronically according to another embodiment of the present invention and tuning combined serial/parallel resistance network.

Figure 28 B illustrates combined serial/resistors in parallel equivalent electrical circuit according to another embodiment of the present invention.

Figure 29 A illustrates and forms electronically according to another embodiment of the present invention and tuning resistance device network.

Figure 29 B illustrates the series connection/resistors in parallel/capacitor equivalent electrical circuit of combination according to another embodiment of the present invention.

Describe in detail

The non volatile register heap

The present invention provides based on the scalable latch circuit of nano structural material and storage unit and scalable Nonvolatile nanotube switch.

The present invention also provides non volatile register heap, more specifically, provide through from comprise be used for productive rate promote purpose redundant level select the non volatile register heap that forms than smaller subset of single non volatile register heap than big collection.

The present invention also provides high-speed asynchronous logic and synchronous logic and memory circuitry; Wherein clock sequential and signal sequence use the new scalable latch circuit based on nano structural material to improve, and to the more high-performance of high yield more scalable Nonvolatile nanotube switch are provided.

Usually expectation fuse latches circuit can store the logic state of expression corresponding fuse (or anti-fuse) logic state; Thereby when breech lock is connected to other circuit; It can offer other electronic circuit with programming information; Such as address reallocation, operator scheme configuration, to store tracking code (tracking code) about for example build date or other situation for redundant memory element.An application of this kind breech lock is the field that the productive rate of non volatile register heap promotes.

Figure 1A shows the non volatile register heap 10 of a succession of N level, and it has N repetition and substantially the same single non-volatile level, begins to finish to level N from level 1.Non volatile register piles up U.S. Patent application No.11/280, more detailed explanation is arranged in 599.

Data input DI is provided to the input of NV register file level 1.The data input of the data output driving N V register file level 2 of level 1, by that analogy, up to the input of the output driving N V of NV register file level N-1 register file level N.The output of NV register file level N provides data output DO.

Non volatile register heap 10 is with the pattern operation synchronous with the clock CLK of the register file that is supplied to each grade 10.The non volatile register heap 10 of each grade comprises volatibility master breech lock; Its driving is non-volatile from breech lock; Wherein this non-volatilely comprises the Nonvolatile nanotube switch of volatibility breech lock and corresponding coupling from breech lock, and this Nonvolatile nanotube switch is in order to be removed at power supply or to store the latched logic state with non-volatile pattern during power down.Before recovering register file 10 operations, power supply is removed or the logic state during power down is stored.Register file 10 is being operated with general volatibility pattern at full speed and on corresponding to the voltage level VDD of selected technology node.V _DDIt can be for example 1.5 to 2.5 volts.Clock frequency can be in for example 1 to 10GHz scope or more.

To lose power supply (removing power supply or power down) if comprise the part of the chip of non volatile register heap; Then the volatibility partial data (logic state) from each grade non volatile register heap 10 can be transferred to the Nonvolatile nanotube switch; Like U.S. Patent application No.11/280,599 is said.Clock CLK stops, and then the operator scheme pulse was used to just before power remove, and the state of each breech lock is stored in corresponding Nonvolatile nanotube switch.Then, power supply can be piled 10 from non volatile register and removes with related logic and memory circuit.

If general register file 10 operations will be resumed, then then energising again of the part that loses power supply of chip or entire chip (if all power supplys are removed or power down).Then, the operator scheme pulse can be used to the data of each Nonvolatile nanotube switch (logic state) are transferred to the non volatile register heap level of its corresponding non volatile register heap 10, and like patent application No.11/280,599 is said.Then, clock CLK is activated and high speed operation begins.Programming mode is for example wiped, is programmed and reads U.S. Patent application No.11/280, describes in 599.The manufacturing of Nonvolatile nanotube switch, be integrated into semiconductor technology, electrical specification, and operator scheme and condition of work at U.S. Patent application No.11/280, describe in 786.

Non volatile register heap level circuit

Figure 1B is illustrated in U.S. Patent application No.11/280, the embodiment of the non volatile register heap level circuit of describing in 599 15, and it is corresponding to non volatile register heap level 1 among Figure 1A ... Any of N.U.S. Patent application No.11/280; 599 describe various non volatile register heap level circuit; Some have the register file level circuit that is coupled to the Nonvolatile nanotube switch through coupled circuit, and other then has the register file level circuit that couples directly to the Nonvolatile nanotube switch.In this example, register file level circuit 1102 is coupled to Nonvolatile nanotube switch 1110 through circuit 1108.

Non volatile register heap level circuit 15 has two operator schemes, promptly general operational mode and the zero non-volatile retained-mode of power logic state (or data mode) (wherein power supply can break off).Volatibility master's latch stage circuit 1104 from a level of register file level circuit 1102 also can be described as the LSSD register stage with volatibility from latch stage circuit 1106.

Shown in Figure 1B; The input node 1115 of volatibility master's latch stage circuit 1104 receives data input signal DI and drives CMOS transmission grid 1130, and it is connected to by cross-linked CMOS phase inverter 1145 and 1150 and forms storage node 1135 and drive this storage node 1135.CMOS transmission grid 1130 use NMOS and the replacement of PMOS device for example to have only the transmission grid of NMOS, to guarantee logical one and the logical zero state-transition between full power supply supply and ground voltage level through the abatement device threshold voltage drop.Clock CLK 1140 is used to transmit grid 1130 permissions or stop that the input signal DI on the input node 1115 drives storage node 1135 through conducting (ON) or by (OFF) CMOS with complementary clock CLKb 1140 ', thereby confirms the logic storing state of cross-linked CMOS phase inverter 1145 and 1150.Only if it should be noted that to specialize that the phase inverter that is shown is all the CMOS phase inverter.The CMOS phase inverter comprises NMOS drop-down (pull-down) device that draws (pull-up) device on the PMOS that is connected to power supply and be connected to ground connection, " Circuits, the Interconnections; and Packaging for VLSI " that operate in H.B.Bakoglu of CMOS phase inverter; Addison-Wesley Publishing Company, Inc, 1990; Describe among the pp.152, its full content is incorporated into this by reference.Cross-linked phase inverter 1145 and 1150 drives the storage node 1155 that is connected to CMOS transmission grid 1160.Clock CLK and complementary clock CLKb are used to transmit grid 1160 permissions or stop that stored logic state node 1155 drives from latch stage circuit 1106 input nodes 1120 through conducting (ON) or by (OFF) CMOS.

Shown in Figure 1B, volatibility drives phase inverter 1170 from the input node 1120 (it also is the output node of main latch stage circuit 1104) of latch stage circuit 1106.The output of phase inverter 1170 is the data output signal DO on the output node 1125, and also drives the input of phase inverter 1175.The output 1180 of phase inverter 1175 is connected to CMOS transmission grid 1185.Clock CLK and complementary clock CLKb are used to allow or stop the existence of feedback control loop (feedback loop), and this feedback control loop is

cross coupling inverter

1170 and 1175 when being allowed to.For 130nm CMOS technology node, during general high speed operation, clock CLK switches at a high speed with the clock frequency of for example 3GHz.Phase inverter 1190 produces the benefit of complementary CLKb or RESTORE ENABLE.When storage data, CMOS conversion grid 1185 form the cross-couplings memory device that node 1120 wherein is used as storage node for ON and phase inverter 1170 and 1175.When CMOS conversion grid 1185 were OFF,

phase inverter

1170 and 1175 did not have cross-couplings and does not form memory device.Be coupled to Nonvolatile nanotube switch 1110 from breech lock storage circuit 1106 through coupled circuit 1108.

Shown in Figure 1B, Nonvolatile nanotube switch 1110 is connected to supply voltage VEPR, and its supply is corresponding to the erasing voltage pulse (or a plurality of pulse) of using the selected operator scheme of coupled circuit 1108.Nonvolatile nanotube switch 1110 also uses electrical connection 1114 to be connected to the node 1116 of coupled circuit 1108.Coupled circuit 1108 is connected to volatibility from latch stage circuit 1106, and the

electrical connection

1119 and 1329 that wherein is connected to

node

1180 and 1125 respectively is used to programming mode, is used to the recovery pattern and be electrically connected 1118.

Shown in Figure 1B, coupled circuit 1108 comprises erase feature.Erasing circuit comprises nmos pass transistor 1320, and its drain electrode is connected to that common node 1317, source electrode are connected to ground connection, the input grid is connected to wipe and launches pulse.During erase operation, transistor 1342 is launched pulse through the programming of zero volt and is activated, and common node 1317 is connected to common node 1116, and it is connected to Nonvolatile nanotube switch 1110, so that allow erase operation.

Shown in Figure 1B; Coupled circuit 1108 also comprises programing function; Comprise PMOS transistor 1343, its drain electrode is connected to that common node 1116, source electrode are connected to common node 1350, the input grid is connected to wipe and launches pulse, and the input of phase inverter 1330 is connected to programming and launches input.Common node 1350 is connected to the cross-couplings nmos pass transistor 1325 that forms high voltage change-over circuit 1360 ' and 1325 ' and PMOS transistor 1327 and 1327 '.Nmos pass transistor 1325 and 1325 ' source electrode are connected to ground connection, and the source electrode of PMOS transistor 1327 and 1327 ' is connected to program voltage V _PROGComplementary input 1119 and 1329 is connected to high voltage change-over circuit 1360 ' input NMOS transistor 1325 and NMOS1325 ' respectively, makes the logic state of high voltage change-over circuit 1360 ' corresponding to the state of volatibility from latch stage 1106.V _PROGThe comparable volatibility of voltage is much higher from latch stage potential circuit 1106.Program voltage is applied to common node 1350 through PMOS transistor 1327, and it then is applied to common node 1116 and Nonvolatile nanotube switch 1110 through PMOS transistor 1343.If common node 1350 keeps ground connection through nmos pass transistor 1325, then do not have program voltage to be applied to common node 1350, and Nonvolatile nanotube switch 1110 is not programmed.

Shown in Figure 1B, coupled circuit 1108 also comprises restore funcitons, comprises PMOS transistor 1365, and its source electrode is connected to V _DD, drain electrode is connected to volatibility from latch stage circuit 1106 input 1120 through connector 1118.During recovery operation, PMOS transistor 1365 is used to input node 120 is precharged to V _DD, then ended into OFF.Nmos pass transistor 1370 have through connector 1118 be connected to input 1120 source electrode, be connected to common node 1317 drain electrode, be connected to and recover to launch the grid of input.Nmos pass transistor 1342 is the ON state during recovery operation, and through Nonvolatile nanotube switch 1110 discharge path between input node common node 1317 and the VEPR is provided.VEPR is zero volt during recovery operation.When transistor 1370 is activated through recovering to launch input,, then imports node 1120 quilts and discharged if Nonvolatile nanotube switch 1110 be ON; If Nonvolatile nanotube switch 1110 is OFF, then imports node 1120 and remain on V _DDVolatibility is resumed the state corresponding to the non volatile state of Nonvolatile nanotube switch 1110 from the state of latch stage circuit 1106.

When being in general operational mode, coupled circuit 1108 is invalid, and non-volatile nanotube switch 1110 is not from V _EPRObtain power supply and also decouple (decoupled) from volatibility from latch stage circuit 1106.Therefore; Volatibility master's latch stage circuit 1104 with volatibility from latch stage circuit 1106 with the high-frequency clock frequency (for using the made logic product of 130nm technology node; Be generally 3GHz, the VDD=1.3 volt) operate through the master/slave register operational mode of synchronous logic with general (routine).

In general operational mode; The clock period at the beginning; Clock CLK 1140 is converted to low-voltage and keeps low-voltage preceding half section of clock period from high voltage, and complementary clock CLKb 1140 ' keeps high voltage from low voltage transition to high voltage and preceding half section of clock period.Thereby 1130 conductings of CMOS switching device will be imported node 1115 voltage V _INBe coupled to storage node 1135.CMOS switching device 1160 ends and the output and the volatibility of volatibility master latch stage circuit 1104 is isolated from the input node 1120 of latch stage circuit 1106.In general operational mode; Clock CLK is connected to the pattern input 1192 of volatibility from latch stage circuit 1106; Clock CLK is connected to CMOS switching device 1185, and the complementary clock CLKb of phase inverter 1190 output also is connected to CMOS switching device 1185, makes the CMOS switching device also end; Thereby the feedback path between the output 1180 of disconnection phase inverter 1175 and the input 1120 of phase inverter 1170 makes node 1120 not be used as storage node.The DI signal can convert the magnitude of voltage corresponding to correct logic state in any time before preceding half section end of clock period to, thereby provides before corresponding logic state is stored in storage node 1155 for cross-linked phase inverter 1145 with 1150 clock conversions when the second half section of clock period begins enough excess times.

In general operational mode; Clock CLK 1140 remains in high voltage from low voltage transition to high voltage and when the second half section of clock period begins, and complementary clock CLKb 1140 ' is converted to low-voltage and remains in low-voltage in the second half section of clock period from high voltage.CMOS switching device 1130 ends; Thereby storage node 1135 is decoupled from input node 1115 input signal DI; It remains in the state corresponding to half section DI of input signal when finishing before the clock period, and storage node 1155 remains in the complementary state complementary with storage node 1135.CMOS switching device 1160 conductings and with the state exchange of the storage node 1155 input node 1120 to phase inverter 1170, it is urged to data output signal DO with output node 1125, and drives the input of phase inverter 1175.In general operational mode; Clock CLK is connected to the pattern input 1192 of volatibility from the latch stage circuit; Clock CLK is connected to CMOS switching device 1185, and the complementary clock CLKb of phase inverter 1190 output also is connected to CMOS switching device 1185, makes the also conducting of CMOS switching device; Thereby the feedback path between the output 1180 of formation phase inverter 1175 and the input 1120 of phase inverter 1170 makes node 1120 be used as storage node.When 1185 conductings of CMOS switching device, the input 1180 of phase inverter 1175 drives the input of phase inverter 1170 and stores the state from latch mode level circuit, and the subordinate phase up to the clock period finishes.

When being in the zero non-volatile retained-mode of power logic state (or data), coupled circuit 1108 is invalid, and Nonvolatile nanotube switch 1110 is not by V _EPRSupply power, and decouple from latch stage circuit 1106 from volatibility.Volatibility master's latch stage circuit 1104 is in zero volt with volatibility from latch stage circuit 1106 power supplys.

In operation, when being transformed into the zero non-volatile retained-mode of power supply from general operational mode, coupled circuit 1108 converted logic state to Nonvolatile nanotube switch 1110 from volatibility from latch stage circuit 1106 before power supply is turned off.When power supply was held open, clock CLK stopped at low-voltage state, and complementary clock CLKb is in high-voltage state, and wherein high-voltage state is in V _DD(for example 1.3 to 2.5 volts) and low-voltage state are in zero volt.If Nonvolatile nanotube switch 1110 is not wiped free of as yet, and therefore stored previous logic state, then coupled circuit 1108 is directed carrying out erase operation, carries out programming operation subsequently.If Nonvolatile nanotube switch 1110 is in erase status, then use coupled circuit 1108 to start programming mode.

During erase operation, programming is launched input voltage and is in zero volt, and the output of transistor 1342 through phase inverter 1330 remains in the ON state.Wipe and launch pulse and be converted to V from zero volt _DD(for example 1.3 to 2.5 volts) make transistor 1320 conductings and through the ON transistor 1342 and 1320 shown in Figure 1B the conductive path between node 1116 and ground connection are provided.Launch voltage by programming and be in zero volt, transistor 1343 remains in the OFF state through the output of phase inverter 1330.Recovery launches that voltage is in zero volt and transistor 1370 is OFF, is in V and recover pre-charge voltage _DDAnd transistor 1365 is OFF, and input 1220 is by being isolated, make volatibility from the state of latch stage circuit 1106 in not multilated of node 1120.Amplitude is V _EV _EPRThe erasing voltage pulse is applied to Nonvolatile nanotube switch 1110 terminals, wherein V _ECan be in 5 to 10 volts scope for example.The resistance of the transistor 1342 of series connection and 1320 resistance ratio Nonvolatile nanotube switch 1110 is much little, also is like this even switch 1110 is in the ON state.If switch 1110 is in the ON state, then electric current from node 1112 through switches 1110 be electrically connected 1114 with ON transistor 1342 and 1320 raceway groove to ground connection, and non-volatile nanotube switch 1110 quilts are switched to OFF (wiping) state.If switch 1110 is in the OFF state, then it keeps OFF (wiping) state.It should be noted that Nonvolatile nanotube switch 1110 can be wiped free of in any time before the programming.If the switch 1110 known erase statuses that are in, then programming can begin immediately.According to a particular embodiment of the present inventionly wipe stimulation at U.S. Patent application No.11/280,786 have more detailed explanation.

It should be noted that during erase operation,

transistor

1370,1365 and 1343 is all OFF, thereby Nonvolatile nanotube switch 1110 and volatibility are isolated from latch stage circuit 1106.Therefore, erase operation can be carried out in any time during the general operational mode, and did not influence the performance of volatibility from latch stage circuit 1106, and can be therefore transparent to the logical operation of device.

The experiment test of single Nonvolatile nanotube switch has been explained that Nonvolatile nanotube switch (switch 1110 shown in Figure 1B and the following non-volatile how mitron switch that further schematically shows with reference to Fig. 9) has been recycled and has been surpassed 5,000 ten thousand times, shown in the curve 16 among Fig. 1 C.For differential more than five one magnitude of resistance value between conduction and the non-conductive state, in 10 kilo-ohms to 50 kilo-ohms scope, non-conductive state resistance surpasses 1 begohm to conduction state resistance usually usually.

The productive rate of Nonvolatile nanotube switch depends on the quantity in required ON/OFF cycle.For 1/2 cycle (conduction is to non-conductive), productive rate is near 100%.Reach quality that thousands of or millions of cycles depend on nanostructured, bulk treatment, passivation, and other factor.In the stage technique, use redundancy to guarantee that enough non volatile register heap productive rates are favourable in early days.

The restriction of non volatile register heap

Pursue higher performance in view of semicon industry and manage energy consumption (like U.S. Patent application No.11/280,599 is said) simultaneously, can introduce new device (such as the Nonvolatile nanotube switch) so that bigger elasticity to be provided.This new device promotes at the productive rate of making that several years ago can need through increasing the means of 10 levels of the defective non volatile register heap of additional redundancy function and bypass, is enough to reduce or eliminate the needs to this redundancy feature up to productive rate study.

For the heap of the non volatile register shown in Figure 1A 10, the quantity of required good level is N, for example 256.Can add additional M level, for example the M=116 position makes that the total N+M of available level is 372.Selection approach can be used to the defective register of bypass, makes that altogether 256 register stages in 372 available levels can be used to form the non volatile register heap that is equivalent to non volatile register heap 10 on the function.

Selection approach can comprise traditional fuse latches device (such as laser fuse), and for example United States Patent(USP) No. 5,345,110, and its full content is incorporated into this by reference.Selection approach can comprise the fuse latches of (with the anti-fuse) type that has a plurality of fuses, and such as described in people's such as Bertin the United States Patent(USP) No. 6,570,802, its full content is incorporated into this by reference.Other selection approach can comprise the fuse latches with essence high electrical resistance trip point, and its scope is in 100K Ω, and like United States Patent(USP) No. 6,570,802 is said.This breech lock hold its ON resistance range at 10K Ω (or lower) for example to 50K Ω; And OFF (programme or blow) resistance range surpasses the fuse of 1M Ω; And be very suitable for new non-volatile fuse type (such as the Nonvolatile nanotube switch; Its electrical specification is at U.S. Patent application No.11/280, describes in 786) replace the traditional use metal or the fuse type of polycrystalline silicon material.The tradition fuse latches is generally OTP (usefulness able to programme once).Use the breech lock of new Nonvolatile nanotube switch the OTP pattern to operate, perhaps can be programmed and wipe for example several thousand times.

Other selection approach can comprise the non-volatile redundancy registers heap, a variant version of non volatile register heap 10 promptly shown in Figure 1, and it can be used to discern good non volatile register heap level.

Be used for comprising or the control of the single non volatile register heap of bypass level is included in each latch stage of the non volatile register heap 10 of modification to circuit (controlling through the state of tradition or new fuse latches or through non-volatile redundancy registers heap level) that it is specified in the back literary composition.

The performance of optimization volatibility principal and subordinate latch stage

Above-mentioned non volatile register heap comprises high speed volatile register (each level comprises principal and subordinate's breech lock usually) and for example is coupled to each Nonvolatile nanotube switch from breech lock (NV NT switch).NV NT switch can couple directly to from breech lock, maybe can use coupled circuit to be coupled.Except the productive rate of the nonvolatile operation of above-mentioned optimization non volatile register heap breech lock, also need the high speed performance of optimization volatile register.Likewise, be not all register files all need be non-volatile.Yet register file needs (high clock speed) synchronous operation at a high speed.

In high clock speed, for example surpass 1GHz, the productive rate of register breech lock can reduce owing to the device parameters that causes change logical delay or high-speed cache (cache) postpones to change changes.This parameter change can betide during the manufacturing batch with batch between (lot-to-lot), and (changing (drift) by device parameters causes) change under the situation about also using at the scene.For example, synchronous high-speed cache needs cache accessing time of 170ps for example on CPU and the plate, can be ready to a clock period after sending the cpu data request on the CPU end from the data that high-speed cache is read guaranteeing.

It is desirable that non-volatile scalable element is provided, and it can be used as fuse or anti-fuse or fuse and anti-fuse or can between ON and OFF state, switch repeatedly element, and corresponding latch circuit.Sequential (adjusting crucial timing path) when integrated this latch circuit and delay control circuit can be used to the optimization manufacturing and middle at the scene optimization higher yields and the performance that promotes fiduciary level.

Non volatile register heap with redundant level

Fig. 2 illustrates the non volatile register heap 20 of N+M level, has N+M single non-volatile level that repeats, and finishes at level 22-(N+M) (non volatile register heap level N+M) from level 22-1 (non volatile register heap level 1) beginning.In level 22-1 to 22-(N+M) each is identical in fact, and in fact with volatile register heap 10 (Fig. 1) among NV register file level 1 to the NV register file level N each identical.Arbitrary N level subclass in the level 1 to N+M can be used to form the non volatile register heap 20 with N level.

Switch SW 1 to SW (N+M) is used as two inputs, one output multiplexer (mux), with when forming N level of non volatile register heap 20, selects (comprising) or cancellation to select (bypass) arbitrary grade of 22-1 to 22-(N+M).Each non volatile register heap level has corresponding switch.For example, the output of level 22-1 is gone to first input of the correspondence of switch SW 1, and the input DI of level 22-1 by-pass 22-1 and directly go second input to switch SW 1 also.The output of switch SW 1 can be the output of grade 22-1, perhaps if by-pass 22-1 then can be the input DI of grade 22-1.When the formation non volatile register piled 20, selecting signal S1 to judge was to select or by-pass 22-1.

For arbitrary grade of 22-K between the level 22-1 to 22-(N+M), correspondence first input to switch SW K is gone in the output of level 22-K; The input (it be the output of switch SW (K-1)) of level 22-K is by-pass 22-K and directly go to import to second of switch SW K also.The output of switch SW K can be the output of grade 22-K, or the input of level 22-K, thus by-pass 22-K.When the formation non volatile register piled 20, selecting signal SK to judge was to select or by-pass 22-K.The input of level 22-K can be the output of a grade 22-(K-1), when by-pass 22-(K-1), can be the output of a grade 22-(K-2) for example perhaps.But a plurality of levels of bypass.For example, if the level of all before the by-pass K, then the input of level 22-K can be DI, i.e. the input of level 1.

The output of afterbody 22-(N+M) is gone to first input of the correspondence of switch SW (N+M), and the input of level 22-(N+M) by-pass 22-(N+M) and directly go second input to switch SW (N+M) also.Switch SW (N+M) is output as data output DO.Non volatile register pile 20 data output DO can be a grade 22-(N+M) but output or by-pass 22-(N+M).Data output DO signal can be from any first prime, for example level K.When the formation non volatile register piled 20, selecting signal S (N+M) to judge was to select or by-pass 22-(N+M).

Control signal S1 ... S (N+M) is by the non-volatile configuration breech lock 1 (24-1) of correspondence ... Non-volatile configuration breech lock N+M (24-(N+M)) provides.Each non-volatile configuration breech lock K (24-K) provides output signal SK, and (bypass) non volatile register heap level K is selected in its selection or cancellation, is described below.Which non-volatile configuration breech lock selection of configuration circuit 26 can be used to select be programmed and which reservation former state.

Selection of configuration circuit 26 can be the decoder logic with control input, for example is used for the subsequent use column or row of memory array and selects, and like United States Patent(USP) No. 5,345,110 is said, and its full content is incorporated into this by reference.Alternatively, selection of configuration circuit 26 series arrangement control registers capable of using, like United States Patent(USP) No. Re.34,363 is said, and its full content is incorporated into this by reference.Below will further describe the selection of configuration circuit.

Be used for selecting the routing switch of non volatile register heap level

Fig. 3 A illustrates on-off circuit 30, and it can be used to pile in the non volatile register that forms Fig. 2 and comprised in 20 o'clock or non volatile register heap level that bypass is corresponding.On-off circuit 30 output C are connected to the side of each CMOS switching device TR1 and TR2, and wherein the CMOS switching device forms based on generic industry practice parallelly connected PFET of use and NFET device, shown in Fig. 3 A.The opposite side of switching device TR1 is connected to signal A and the opposite side of switching device TR2 is connected to signal B.Control signal SK drives the input of phase inverter INV1.The output of phase inverter INV1 drives the NFET control grid of the input of phase inverter INV2, the PFET control grid that reaches TR1 and TR2.The output of phase inverter INV2 drives the NFET control grid of TR1 and the PFET control grid of TR2.

Fig. 3 B illustrates on-off circuit 35, and it can be used to pile in the non volatile register that forms Fig. 2 and comprised in 20 o'clock or non volatile register heap level that bypass is corresponding.On-off circuit 35 terminal C are connected to the side of each CMOS switching device TR1 and TR2, and wherein the CMOS switching device forms based on parallelly connected PFET and the NFET device shown in generic industry practice use Fig. 3 B, shown in Fig. 3 A.The opposite side of switching device TR1 is connected to terminal A and the opposite side of switching device TR2 is connected to terminal B.Control signal SK drives the PFET control grid of TR2 and the NFET control grid of TR1.Complementary control signal SKb drives the NFET control grid of TR2 and the PFET control grid of TR1.

In when operation, shown in Fig. 3 C, if input control signal SK be high (for example 1.5 to 2.5 volts), then CMOS conversion grid TR1 is ON, and the PFET of correspondence and the parallelly connected device of NFET all be in the ON state, and terminal C is connected to terminal A.CMOS switching device TR2 is OFF.Yet if input signal SK is low (for example zero volt), CMOS conversion grid TR2 is ON, and corresponding PFET all is in the ON state with the parallelly connected device of NFET, and terminal C is connected to terminal B.CMOS switching device TR1 is OFF.It should be noted that as SK when being high, then SKb is low, and when SK when low, then SKb be a height.

When on-off circuit 30 or on-off circuit 35 operations, as shown in Figure 3, terminal A and B can be input signal, and it can route to output C because of becoming in control signal SK (or control signal SK and SKb).Alternatively, terminal C can be input signal, and it can route to terminal A or terminal B because of becoming in control signal SK (or control signal SK and SKb).When on-off circuit 30 or on-off circuit 35 are used as switch SW 1 ... During the representation switch SK (as shown in Figure 2) of SW (M+N); Terminal A can be used as first input that is connected to corresponding to the output of non volatile register heap level K; And terminal B can be used as second input of the input that is connected to non volatile register heap level K; It can be used to the for example corresponding non volatile register heap level K of bypass, as above-mentioned said for non volatile register heap 20 operations shown in Figure 2.

Utilize the routing switch control of non-volatile signal source

To in order to selecting or cancellation selects the routing circuit 30 of single non volatile register heap level (for example above with respect to the described non volatile register heap of a Fig. 2 and Fig. 3 grade K) or 35 control signal to supply through non-volatile breech lock, breech lock of each switch for example.A mode is based on laser fuse (it uses laser ablation to programme) and uses various breech locks.These laser fuses can be made up of for example patterned metal or polysilicon component.Alternatively; This laser fuse can use patterned nanostructured resistor to form; This nanostructured resistor is similar to the resistor based on nanostructured; It is being entitled as " Resistive Elements using Carbon Nanotubes " the U.S. Patent application No.11/230 that submits in 20 days September in 2005, describe in 876, its full content is incorporated into this by reference.

Other type is for using the breech lock based on electrical fuse or electron back fuse, and of people's such as Bertin United States Patent(USP) No. 6,570,806, its full content is incorporated into this by reference.These breech lock types are used as the OTP breech lock.

Another mode is for introducing new breech lock based on the resistance of Nonvolatile nanotube switch as logic state fuse or anti-fuse storage cell, U.S. Patent application No.11/280 for example, 786 described switches.To come the new breech lock of stored logic state can be OTP or can use once above (repeatedly) with erasing-programming/read mode described in 786 as at U.S. Patent application No.11/280 based on the resistance of Nonvolatile nanotube switch.It should be noted, at U.S. Patent application No.11/280, the non volatile register heap level described in 599 (or like the following stated, the variant of this level) can be used as non-volatile logic state storage breech lock.

In all situations, be in the fuse of closure (conduction) state or disconnection (non-conductive) state or the Nonvolatile resistance sexual state of anti-fuse and be used to represent first or second logic state.This latch circuit becomes fuse (or anti-fuse) Nonvolatile resistive state exchange the corresponding electrical voltage level of presentation logic 1 or 0.The control signal that this corresponding voltage level is used as routing circuit shown in Figure 3 30 or 35 transmits.In this way, the logic state of non-volatile breech lock can be used to select or cancel non volatile register heap level of selecting (bypass) shown in Figure 2.

Based on the non-volatile signal source of the laser ablation that uses fuse as the non-volatile breech lock of program means

Fig. 4 illustrates the OTP fuse circuit 40 that comprises fuse element 41, and this fuse element 41 is shown as to have at node 42 and is connected to the first fuse terminal of gating (strobe) device (transistor) T5 and is connected to the second fuse terminal of ground connection at node 43.Second terminal that is connected to the gating device T5 of terminal 45 also is connected to by transistor T 1, T2, T3 and inverter device 46 formed latch circuits.Breech lock precharge device (transistor) T4 also is shown as and is connected to power supply VPS and terminal 45.In this latch circuit 40, during chip power, precharge and gate voltage are retained as low (for example ground connection), and node 45 is precharged to positive voltage (V through precharge transistor T4 _PS) and latch circuit 40 is in first logic state, and node 45 is in high voltage and V on the node 47 _OUTBe in low-voltage.During chip power, transistor T 2 remains on the OFF state through low pre-charge voltage, therefore keeps latch circuit 40 feedback paths open circuit, and latch circuit 40 is held in the first logic state (V to guarantee finishing afterwards by chip power _OUT=0).After chip power finishes; Then pre-charge voltage changes (following further said with reference to Fig. 5) at the gating high voltage and changes paramount value before; Thereby make transistor T 2 for ON and with the first logic state breech lock (storage) in latch circuit 40, making precharge device T4 simultaneously is OFF.When transistor T 2 was in the ON state, latch circuit 40 feedback paths were accomplished, and it makes latch circuit 40 can store first logic state.Latch circuit 40 uses one of metal or two logic states of resistive fuse element 41 expressions of poly non-volatile.For example, if fuse element 41 is kept perfectly (conduction), then when gating transistor T 5 is activated, node 45 is by discharge and latch circuit 40 is converted to second logic state, makes node 45 be in low-voltage and V on the node 47 _OUTBe in high voltage.Yet if fuse 41 is programmed (becoming non-conductive) through laser ablation, node 45 is not discharged, and latch circuit 40 remains on first logic state.That is, latch circuit 40 converts the resistive value of non-volatile fuse to the electrical voltage level of presentation logic 0 (first logic state) or logical one (second logic state).

Non volatile register shown in Figure 2 heap 20 is to be tested after manufacturing, and available (good) and disabled (bad) non volatile register heap level from whole N+M can with grade identify.If identify the good non volatile register heap level of sufficient amount, be at least 256 grades in this example, then produce the tester that shows good and bad level and produce figure (productive rate figure).If pile the level that will comprise such as non volatile register heap level K at 20 o'clock in the formation non volatile register, then the fuse 41 corresponding to non-volatile breech lock K is held complete (conducting), and corresponding latch circuit 40 is converted to second logic state.Yet; If the non volatile register heap level such as level J will be by bypass (promptly getting rid of from non volatile register heap 20); Then the fuse 41 corresponding to non-volatile breech lock J is programmed to (being write as) high resistance state (blowing) through laser ablation, and corresponding latch circuit 40 remains in first logic state.The productive rate figure that tester produces is converted into fuse position coordinates (for example X, Y), carries out laser ablation to use laser ablation tool (being generally ready-made industry standard laser tool).

Be shown in Fig. 5 by latch circuit shown in Figure 4 40 performed typical read operations with waveform 50: at first, precharge transistor device T4 is imposed pulse and node 45 is precharged to voltage V by signal 51 _PS, and latch circuit 40 is precharged to first logic state, end then.In its first logic state, latch circuit 40 nodes 45 voltages are the output voltage V on the height node 47 _OUTBe low-voltage.Then, gating device T5 is imposed pulse by signal 52 and becomes ON.If fuse element 41 is kept perfectly, then its for conduction and remove pre-charge voltage from node 45, thereby force latch circuit 40 to become second logic state that node 45 wherein is in low-voltage, and the V on the node 47 _OUTBe in high voltage.If fuse element 41 has been programmed, then it will no longer enough conduct electricity to remove enough electric charges from latch nodes 45, to change the logic state of breech lock.In this case, when the gating device was activated, latch circuit 40 remained in its first logic state, and node 45 is the output voltage V on the high voltage terminal 47 _OUTFor low.

If non-volatile heap latch stage K will be included as a level in the non volatile register heap 20 shown in Figure 2, the fuse 41 in the then corresponding latch circuit 40 keeps being in conduction state.Therefore, when corresponding latch circuit 40 during by gating, it changes aforesaid second logic state into, and wherein node 45 is in low-voltage and V on the node 47 _OUTBe in high voltage.If routing switch 30 is used to non volatile register heap 20, then export the positive voltage V on 47 _OUTBe transferred into and select signal input SK, CMOS conversion grid TR1 is activated and CMOS conversion grid TR2 is deactivated (deactivated), as so that said with reference to Fig. 3 A.Routing switch 30 connects input A and output C, and its output with 20 grades of K of non volatile register heap is sent to the input of 20 grades of K+1 of non volatile register heap, therefore level K is included in the non volatile register heap 20.

It should be noted, if use the routing switch 35 shown in Fig. 3 B to replace routing switch 30, then corresponding to V on the node 47 _OUTSignal input SK and select signal input SKb all to be provided corresponding to the complementation of the node 45 of circuit breech lock 40.Therefore, routing switch 35 connects input A and output C, and its output with 20 grades of K of non volatile register heap is sent to the input of 20 grades of K+1 of non volatile register heap, therefore level K is included in the non volatile register heap 20.

If non-volatile heap latch stage J will be excluded as a level in the non volatile register heap 20, the fuse 41 in the then corresponding latch circuit 40 is programmed to non-conductive state.Therefore, when corresponding latch circuit 40 during by gating, it remains aforesaid first logic state, and wherein node 45 is in high voltage and V on the node 47 _OUTBe in low-voltage.If routing switch 30 is used to non volatile register heap 20, then export low (near zero) the voltage V on 47 _OUTBe transferred into and select signal input SJ, CMOS conversion grid TR2 is activated and CMOS conversion grid TR1 is deactivated, as above said with reference to Fig. 3 A.Routing switch 30 connects input B and output C, and it is included in the input of 20 grades of J+1 of output bypass to non volatile register heap of 20 grades of J of non volatile register heap in the non volatile register heap 20 with level J thus.

It should be noted, if use the routing switch 35 shown in Fig. 3 B to replace routing switch 30, then corresponding to V on the node 47 _OUTSignal input SJ and select signal input SJb all to be provided corresponding to the complementation of the node 45 of circuit breech lock 40.Therefore, routing switch 35 connects input B and output C, and it is included in the input of 20 grades of J+1 of output bypass to non volatile register heap of 20 grades of J of non volatile register heap in the non volatile register heap 20 with level J thus.

Based on the non-volatile signal source of the laser ablation that uses patterned nanostructured fuse as the non-volatile breech lock of program means

The patterned laser fuse (resistor) of use metal or polyresistor element need be removed the material of a great deal of during laser ablation.The opening that typical case's industry demand in practice penetrates dielectric layer exposes the fuse zone to the open air, makes fuse materials discharge through opening during laser ablation because of suitable wide variety of materials (metal or semiconductor).

Any point that the laser fuse that is formed by patterned nanotube layer is easy in semiconductor technology is integrated.Likewise, the patterned nanotube layer of fuse (or resistor) formation needs to remove a spot of material during laser ablation.Therefore, patterned nanotube laser fuse can carry out laser ablation with the opening that penetrates dielectric layer, or when covering with the protectiveness dielectric film, it is transparent as far as laser energy that dielectric layer is provided.Patterned nanostructured resistor is at U.S. Patent application No.11/230, describes in 876.

Because fuse blows the minimum gap of generation in resistor improperly, metal and polysilicon fuse also can restore voluntarily.If this device uses in the hot environment of for example highly radioactive environment, but then generating material diffusion, and it will make the resistor short circuit of before having blown, and produce the leakage path through fuse element.Because the strong C-C bonding character that exists in the small size of nano tube structure and the nanotube, the concatenation ability again of blowing structure is little of not existing.

Fig. 6 illustrates patterned nanostructured fuse and corresponding contact, and it can replace the fuse 41 in the latch circuit shown in Figure 4 40.Fig. 6 fuse is corresponding to the patterned resistor based on nanostructured (for example U.S. Patent application No.11/230, shown in 876), and it can be included in any perpendicular layers in semiconductor (or ceramic, organic or other encapsulation) technology.Patterned nanostructured fuse can be used in any logic product, such as processor, controller, digital signal processor, ASIC, programmable logic array and other logic product.Patterned nanostructured fuse also can be used for memory product, such as DRAM, SRAM, EEPROM, CRAM; FeRAM, MRAM and NRAM.In the situation of non volatile register heap breech lock 20; Owing to the Nonvolatile nanotube switch that is used for 20 grades of non volatile register heap breech locks shown in Figure 2 uses the sedimentary deposit (it then can use the specific light carving method to be patterned to the Nonvolatile nanotube switch) of one or more nanostructureds to form, therefore can be useful especially as the fuse element 41 in the latch circuit 40 with patterned nanostructured fuse.Can be deposited in the vertically integrated structure Anywhere in order to the nanostructured layers that forms fuse 41.Alternatively, the nanotube fuse can use the Nonvolatile nanotube switch that is used in non volatile register heap level in order to manufacturing) form.This nanostructured layers can be arranged in vertically integrated structure Anywhere.The method of making nanostructured layers and element has more detailed explanation in the patent document of being included in.

Fig. 6 A illustrates the planimetric map of the patterned nanostructured resistor fuse 60 of making state (before the insulating layer deposition), and it comprises patterned nanostructured 61 resistors with contact 62 and contact 62 '.The poriness (porosity) of the sheet resistance of patterned nanostructured elements 61 through the control nanostructured, in order to quantity and other Variable Control of the nano tube structure layer that forms nanostructured elements 61.Nanostructured can reliably even mode be applied to a surface, makes the electrical properties of nanostructured to be controlled.Can use for example spin coating or spraying technology to apply nanostructured layers.Patterned nanostructured 61 can be controlled as from for example 1 kilo-ohm of sheet resistance to 1 megaohm.The various examples of contact resistance and sheet resistance are at U.S. Patent application No.11/230, provide in 876.Fig. 6 B illustrates the fuse 60 after laser ablation has removed zone 63.

Contact 62 and 62 ' can be used for the purpose that contacts and interconnect, shown in Fig. 6 C sectional view (after the insulator deposition).Insulator 68 can be deposited as insulating protective layer, to accomplish the patterned nanostructured resistor fuse 65 of insulation.Fig. 6 D illustrates the cross section of fuse 65 (laser ablation has removed 63 backs, zone).Contact and interconnection material be exemplified as metal element (for example Ru, Ti, Cr, Al, Au, Pd, Ni, W, Cu, Mo, Ag, In, Ir, Pb, Sn) and metal alloy (for example TiAu, TiCu, TiPd, PbIn and TiW); Also can use U.S. Patent application No.11/230,876 described other suitable conductors or conductive nitride, oxide or silicide (for example RuN, RuO, TiN, TaN, CoSi _xAnd TiSi _x).Insulator layer can be SiO ₂, SiN _x, Al ₂O ₃, BeO, polyimide (polyimide), alkyd resin (Mylar) or other insulating material that is fit to.

Through the patterned nanostructured resistor fuse 65 of deposition insulation, patterned nanostructured resistor fuse 65 can be used as the fuse 41 in the breech lock 40 shown in Figure 4, makes terminal 62 contact nodes 42 and make terminal 62 ' contact node 43.

Fuse 65 can be kept perfectly or can be through laser ablation programming (blowing).Fig. 6 B and 6D illustrate respectively before the laser ablation and afterwards Fig. 6 A and 6C.Fuse materials (for example metal or polysilicon) need to remove the material of relatively large amount and remain usually on-insulated, as previously mentioned.The nanostructured (its diameter range is respectively 1 to 5nm or 5 to 20nm) that is made up of a plurality of SWNT and/or MWNT causes the removal that relates to small quantity of material (laser ablation) of a plurality of SWNTs and/or MWNTs; Make fuse 65 under the situation that insulation course exists, to be programmed (blowing), thereby the regulation insulation course is transparent for employed laser light wavelength.Alternatively, for the purpose of laser ablation, can remove the part of the insulating material 68 on patterned nanostructured 61 elements.

When operation, the logic state reflection of breech lock 40 shown in Figure 4 is as the resistance states of the patterned nanostructured resistor fuse 65 of fuse 41 in the breech lock 40.For example, (conduction) (shown in Fig. 6 A or 6C) if fuse element 41 remains unchanged, then when gating transistor T 5 is activated, node 45 is by discharge and latch circuit 40 is converted to second logic state, makes node 45 be in low-voltage and V on the node 47 _OUTBe in high voltage.Yet if fuse 41 is programmed (becoming non-conductive) (shown in Fig. 6 B or 6D) through laser ablation, node 45 is not by discharge and latch circuit 40 remains on first logic state.That is, latch circuit 40 converts non-volatile fuse 65 resistance values to the electrical voltage level of presentation logic 0 (first logic state) or 1 (second logic state).

Based on the non-volatile signal source of using electrical fuse or anti-fuse as the non-volatile breech lock of program means

Since laser-light spot size with aim at, laser ablation need place fuse the zone of large scale (big overlay area), and and proximate circuitry between need the gap.Can not place any device under the fuse.

The electrical fuse (electric fuse) that is made up of metal or the resistive trace of polysilicon can be fit to insert more the zone of small size (compared to the zone of the fuse that uses laser ablation).Equally, electrical fuse can be activated before or after chip is packed.Electrical fuse is in the resistive state of ON (conduction) (being generally hundreds of ohms) when processing, and through causing local I ²The electric current of R heating and be programmed (blowing) to greater than 100 kilo-ohms of OFF (non-conductive) state to 1 megaohm scope.Usually, this program current is in milliampere scope.It should be noted that electric fuse abbreviates fuse sometimes as.

Electron back fuse (anti-fuse) is formed by capacitor arrangement usually, and this capacitor arrangement comprises metal or polysilicon capacitor plate and thin insulator, for example SiO ₂And/or SiN _xThe electron back fuse is in OFF (non-conductive) state (usually in the scope of 10 megaohms more than it) and is programmed (blowing) to ON (conduction) state through the voltage that applies 8 to 12 volts when processing, and program current is in milliampere scope.ON (conduction) resistance value is in 1K to 50 kilo-ohm of scope usually.It should be noted that the electron back fuse abbreviates anti-fuse sometimes as.

Fig. 7 illustrates the diagrammatic sketch of the general fuse latches 70 that is designed to meet electronic programmable (OTP) electric fuse and the anti-fuse of electronic programmable (OTP) (United States Patent(USP) No. 6,570,806 like people such as Bertin is described).General breech lock 70 is suitable for to different fuses or anti-fuse latches circuit types the resistive trip point of different breech locks (trip point) (being called intrinsic breech lock breaking resistor) being provided; To regulate poor in ON state and the OFF state resistance value; Like United States Patent(USP) No. 6,570,806 is described.Breech lock 70 can be used as the non-volatile configuration breech lock 1 (24-1) among Fig. 2 ... Non-volatile configuration breech lock N+M (24-(N+M)).

At general latch circuit 70 shown in Figure 7, fuse latches circuit 40 shown in Figure 4 has been modified and has comprised first electric fuse or pass through transistor T 5 and the gating path 80 of T6, and it comprises the node 72 that is connected to transistor T 6 and is connected to source voltage V _{SOURCE_F}(V _{Source _ F}) the electric fuse element 71 of node 73.Transistor T 6 is maintained in the range of linearity, and its channel resistance that has, is causing like United States Patent(USP) No. 6,570 when combining with the resistance (being generally for example 200 ohm) of electric fuse 71,806 said 10 kilo-ohms resistive trip points of breech lock.10 kilo-ohms resistive trip point meets hundreds of ohm electric fuse ON resistance and at least 100 kilo-ohms OFF resistance.It should be noted that when the state of breech lock 70 was set, node 73 was in zero (ground connection) voltage.

Transistor T 7 has been added between node 72 and ground connection, to be used for the purpose of electric fuse programming.During the electric fuse programming, voltage source V _{SOURCE_F}Be applied to node 73.If transistor T 7 is through input programming activation voltage V _P-FAnd be switched on, then program current flows through fuse 71, and fuse 71 is converted to high resistance state.If transistor T 7 keeps OFF, then fuse 71 is not programmed and remains in low resistance (ON) state.Anti-fuse 74 can only be programmed once.Usually, need be at the program current in the milliampere scope.The example that polysilicon fuse and programming require is at United States Patent(USP) No. 6,624, describes in 499 and No.6,008,523, and its full content is incorporated into this by reference.

In general latch circuit 70 shown in Figure 7, fuse latches circuit 40 shown in Figure 4 has been modified comprising the second anti-fuse or the gating path 81 through transistor T 8 and T9, and it comprises the node 75 that is connected to transistor T 9 and is connected to source voltage V _{SOURCE_AF}(V _{Source _ AF}) the electric antifuse element 74 of node 76.Transistor T 9 is controlled in the range of linearity; When its channel resistance that has makes up at the resistance (being generally for example 10 kilo-ohms to 50 kilo-ohms) with anti-fuse 74; Cause like United States Patent(USP) No. 6,570 the resistive trip point of breech lock that 806 (its full content is incorporated into this by reference) are described 100 kilo-ohms.100 kilo-ohms resistive trip point meets thousands of ohm the anti-fuse ON resistance and the OFF resistance of at least 1 megaohm.It should be noted that when the state of breech lock 70 was set, node 76 was in zero (ground connection) voltage.

Transistor T 10 has been added between node 75 and ground connection, to be used for the purpose of anti-fuse programming.During anti-fuse programming, voltage source V _{SOURCE_AF}Be applied to node 76.If transistor T 10 is through input programming activation voltage V _P-AFAnd be switched on, then program current is applied in anti-fuse 74 two ends, little current (microampere) flows and anti-fuse 74 is converted to low resistance state.If transistor T 10 keeps OFF, then anti-fuse 74 is not programmed and keeps being in high resistance (OFF) state.Fuse can only be programmed once.Usually, V _{SOURCE_AF}Be in 8 to 12 volts scope, and corresponding program current is in the microampere scope.The example that anti-fuse and programming require is at United States Patent(USP) No. 5,956, describes in 282, and its full content is incorporated into this by reference.

General latch circuit 70 output nodes 78 are corresponding to latch circuit 40 output nodes 47.General latch circuit 70 nodes 77 (being the benefit of output node 78) are corresponding to latch circuit 40 nodes 45.If the intrinsic breech lock breaking resistor of general latch circuit 70 is designed to 100 kilo-ohms, 40 pairs of disturbances that caused by the cosmic rays of the α particle that hole-electron pair produced of then general latch circuit 70 comparable latch circuits are more responsive.Therefore, can ballast capacitor 79 be added into output node 78, and can ballast capacitor 79 ' be added into complementary node 77.The ballast capacitor value can be for example 10 to 20fF.

When electric fuse 71 is used for gating path 80, identical with the read operation that uses 41 pairs of latch circuits 40 of fuse to the read operation of general latch circuit 70.Therefore, if non-volatile heap latch stage K will be included as a level in the non volatile register heap 20 shown in Figure 2, then the electric fuse 71 in the corresponding general latch circuit 70 remains on conduction state.Therefore, when corresponding general latch circuit 70 during by gating, it is converted to foregoing second logic state, and wherein node 77 is in low-voltage and V on the node 78 _OUTBe in high voltage.If routing switch 30 is used to non volatile register heap 20, then export the positive voltage V on 78 _OUTBe transmitted to select signal input SK, CMOS conversion grid TR1 is activated and CMOS conversion grid TR2 is deactivated, as above said with reference to Fig. 3 A.Routing switch 30 connects input A and output C, and its output with 20 grades of K of non volatile register heap is sent to the input of 20 grades of K+1 of non volatile register heap, therefore level K is included in the non volatile register heap 20.

When electric fuse 71 is used for gating path 80, identical with the read operation that uses 41 pairs of latch circuits 40 of fuse to the read operation of general latch circuit 70.Therefore, if non-volatile heap latch stage J will be excluded as a level in the non volatile register heap 20 shown in Figure 2, then the electric fuse 71 in the corresponding general latch circuit 70 is programmed to non-conductive state.Therefore, when corresponding general latch circuit 70 during by gating, it remains in foregoing first logic state, and wherein node 77 is in high voltage and V on the node 78 _OUTBe in low-voltage.If routing switch 30 is used to non volatile register heap 20, low (near zero) voltage of then exporting on 78 is transmitted to select signal input SJ, and CMOS conversion grid TR2 is activated and CMOS conversion grid TR1 is deactivated, as above said with reference to Fig. 3 A.Routing switch 30 connects input B and output C, and therefore it get rid of level J with the input of 20 grades of J+1 of output bypass to non volatile register heap of 20 grades of J of non volatile register heap in non volatile register heap 20.

It should be noted, for general latch circuit 70, if if node 78 for just and node 78 output can be used for selecting 77 outputs of signal input SK complementary node to can be used for the signal input SKb of selected on-off circuit 35, then a level K will be included in the register file 20.Yet, if node 78 is zero and can be used for selecting signal input SJ and complementary node 77 can be used for the signal input SJb of selected on-off circuit 35 that a level J will be excluded, as above said with reference to latch circuit 40 in register file 20.

When anti-fuse 74 is used for gating path 81, use the read operation of 41 pairs of latch circuits 40 of fuse opposite to the read operation of general latch circuit 70 and about programming.Therefore, if non-volatile heap latch stage K will be included as the one-level in the non volatile register heap 20 shown in Figure 2, then the anti-fuse 74 in the corresponding general latch circuit 70 is programmed to conduction state from constant general non-conductive state.Therefore, when corresponding general latch circuit 70 during by gating, it is converted to foregoing second logic state, and wherein node 77 is in low-voltage and V on the node 78 _OUTBe in high voltage.If routing switch 30 is used to non volatile register heap 20, then export the positive voltage V on 78 _OUTBe transmitted to select signal input SK, CMOS conversion grid TR1 is activated and CMOS conversion grid TR2 is deactivated, as above said with reference to Fig. 3 A.Routing switch 30 connects input A and output C, and its output with 20 grades of K of non volatile register heap is sent to the input of 20 grades of K+1 of non volatile register heap, therefore level K is included in the non volatile register heap 20.

When anti-fuse 74 is used for gating path 81, use the read operation of 41 pairs of latch circuits 40 of fuse opposite to the read operation of general latch circuit 70 and about programming.Therefore, if non-volatile heap latch stage J will be excluded as the one-level in the non volatile register heap 20 shown in Figure 2, then the anti-fuse 74 in the corresponding general latch circuit 70 remains non-conductive state.Therefore, when corresponding general latch circuit 70 during by gating, it remains in foregoing first logic state, and wherein node 77 is in high voltage and V on the node 78 _OUTBe in low-voltage.If routing switch 30 is used to non volatile register heap 20, then export low (near zero) the voltage V on 78 _OUTBe transmitted to select signal input SJ, CMOS conversion grid TR2 is activated and CMOS conversion grid TR1 is deactivated, as above said with reference to Fig. 3 A.Routing switch 30 connects input B and output C, and therefore it get rid of level J with the input of 20 grades of J+1 of output bypass to non volatile register heap of 20 grades of J of non volatile register heap in non volatile register heap 20.

Based on the Nonvolatile nanotube switch being used as electrical fuse or anti-fuse non-volatile signal source as the non-volatile breech lock of program means

Usually, use the OTP electrical fuse of metal or polysilicon trace to have less relatively resistance value (usually in 100 ohm of scopes) and need relatively large electric current (in the milliampere scope), to reach sufficiently high I ²The R power consumption is so that fuse changes non-conductive state into from conduction state.Equally, thus electrical fuse length avoid needing even higher electric current to reach enough resistance than minimum dimension length usually.As a result, the electrical fuse convergent-divergent is not good and keep relatively large size, even the technical size in each technology of new generation reduces.

Usually, OTP electron back fuse is at thin insulator layer (5 to 10nm SiO for example ₂And/or SiN _x) either side use the capacitor arrangement of condenser armature with metal or semiconductor (for example polysilicon) material, and need higher relatively breakdown current (for example in 8 to 12 volts scope), its size is not easy convergent-divergent.The convergent-divergent of electron back fuse is not good and keep relatively large size, even the technical size in each technology of new generation reduces.

Needed is scalable fuse and/or scalable anti-fuse; Its available silicon integrated circuit technique (for example CMOS and bipolar memory, logic, mixed signal etc.) is easily integrated; And reduced size is introduced into as the program voltage and the electric current in new technology epoch.Nonvolatile nanotube switch (at U.S. Patent application No.11/280,786 in describe) is scalable Nonvolatile nanotube switch, and it can add by any convenient point in process flow.These scalable Nonvolatile nanotube switches can be in order to replace non-volatile electronic fuse or anti-fuse.

Fig. 8 illustrates the latch circuit 82 that is designed to hold Nonvolatile nanotube switch 83, and it is at U.S. Patent application No.11/280, and 786 describe and further summarize with reference to figure 9 hereinafter.Breech lock 82 is designed to provide breech lock resistive trip point, and it is equivalent to United States Patent(USP) No. 6,570,806 said 100 kilo-ohms intrinsic breech lock breaking resistors, and the full content of this patent is incorporated into this by reference.The intrinsic breech lock breaking resistor of selecting 100 kilo-ohms be because Nonvolatile nanotube switch ON resistance usually in 10 kilo-ohms to 50 kilo-ohms resistance ranges, shown in Fig. 1 C.Nonvolatile nanotube switch OFF resistance is usually greater than 1G Europe or bigger, shown in Fig. 1 C.

Latch circuit 82 shown in Figure 8, general fuse latches 70 shown in Figure 7 have been modified comprising the Nonvolatile nanotube switching gate path 86 through transistor T 5 and T6 ', and it comprises the node 85 that is connected to transistor T 6 ' and to voltage source electrode V _{SOURCE_F}The Nonvolatile nanotube on-off element 83 of node 84.Transistor T 6 ' is maintained in the range of linearity; When its channel resistance that has makes up at the resistance (being generally for example 10 kilo-ohms to 50 kilo-ohms) with the Nonvolatile nanotube switch; Cause like United States Patent(USP) No. 6,570 806 described 100 kilo-ohms resistive trip points of breech lock.The resistive trip point of 100 kilo-ohms breech lock meets 10 kilo-ohms to 50 kilo-ohms Nonvolatile nanotube switch ON resistance and the OFF resistance of at least 1 megaohm (Nonvolatile nanotube switch OFF resistance is generally 1G Europe or bigger).It should be noted that when the state of breech lock 82 was set, node 84 was in zero (ground connection) voltage.

The above breech lock 82 that further specifies with reference to Fig. 8 shows NV NT switch 83; It has a terminal (program/erase pulse VOUT is applied in enlightenment) that is connected to node 84 and is connected to common node 85 and second terminal of the drain electrode of operator scheme selection transistor T 7 '.The operation of latch circuit 82 is explained with higher relatively resistance range (10 kilo-ohms to 50 kilo-ohms) about NV NT switch 83.Yet NV NT switch 83 can be in lower resistance range, for example 100 ohm to 10 kilo-ohms scopes.

Latch circuit 82 also disposes about the specific breech lock that is connected to common node 85 and explains, and it comprises phase inverter INV, have the feedback that is made up of transistor T 1, T2, T3 launches/phase inverter of forbidden device and corresponding interconnection device.What comprise equally has precharge and gate transistor T4 and T5 and interconnection thereof and a bias transistor T6 ' (being in the range of linearity usually) that is connected to common node 85.Different breech lock configurations can be connected to common node 85 to reach corresponding function and operation, as said with reference to latch circuit 82.Latch circuit 82 (with many other latch circuit configurations known in the industry) can be used to the low resistance and the high resistance state of NV NT switch 83 are converted to corresponding to high and low voltage output V _OUTThe logic of value " 1 " and logic " 0 " state.Equally, the capacitor 89 and 89 ' that is used for additional latch stability is optional, and in many configurations, does not use.These capacitors also can save from latch circuit 82.

When talking about the state of warp programming; For example; At the non-volatile electric fuse of OTP (electric fuse) that is used for non-volatile breech lock (breech lock 70 for example shown in Figure 7) be used for having the different situation of term between the scalable Nonvolatile nanotube switch of the non

volatile register heap

10,15,20 shown in Fig. 1 and 2.When non-volatile breech lock and non volatile register heap was discussed in same instructions, the different situation of these terms can cause confusion.For the purpose of clarifying, table 1 and table 2 show the difference of term.

In table 1, the electric fuse that is used for a breech lock is in the ON state when processing, and can be programmed once (OTP) and become the OFF state.Therefore, electric fuse OFF state is called as through programming state in the corresponding term in the conventional term of correspondence and this instructions.

On the contrary; As shown in table 2; The Nonvolatile nanotube switch (NV NT switch) (as illustrated in fig. 1 and 2) that is generally used for the non volatile register heap is in the ON state when processing, the corresponding term of NV NT switch OFF state in this instructions of patent document neutralization of institute's reference is called as erase status.Because but the NV NT switch cycle repeatedly, the corresponding term of ON state in this instructions of patent document neutralization of institute's reference that therefore causes because of OFF state to ON state-transition is called as through programming state.

Table 1

Table 2

Reference table 1, under the situation that electric fuse has been replaced by scalable Nonvolatile nanotube switch (NV NT switch) in breech lock, term depends on application.If NV NT switch application need change repeatedly between ON and OFF state, then the OFF state be regarded as wipe and the ON state for through programming when processing (or for).Yet, if will being used as the OTP electric fuse, NV NT switch replaces, and NV NT switch can be described as nanotube fuse (nt fuse), and it is a new terminology.Therefore, in the OTP pattern, the OFF state can be called as through programming state, and is as shown in table 1, but not the state of having wiped.Through the OFF state of programming only in the non-volatile breech lock 82 of Fig. 8, and only use when breech lock 82 uses with the OTP pattern.In breech lock 82, when being used for the OTP pattern, term " nt fuse " is corresponding to NV NT switch 83.

It should be noted, be different from electric fuse, NV NT switch is (and being used as) Nonvolatile nanotube switch, and therefore can between ON and OFF state, change for several times.Therefore, NV NT on-off ratio OTP electric fuse has more versatility.Product can be changed after being configured in programming, even at the scene that NV NT switch is used as the part of latch circuit.For example, non volatile register shown in Figure 2 piles up in one or more 256 levels and can experience inefficacy.This can take place in the general operation situation, or can because of be exposed to rugged surroundings (for example radiation, the high temperature of height or ought use at the scene in other situation of operating) take place.When if this situation takes place; Then the additional untapped breech lock of hypothesis exists; And suppose that employed non-volatile configuration control breech lock is similar with breech lock 82 shown in Figure 8; The ON that then selection of configuration circuit 26 can be through changing corresponding NV NT switch and the OFF state non-volatile configuration breech lock that resets is as required operated to recover non volatile register heap 20.

, describe in 806 shown in the table 1 and about the employed term of non-volatile breech lock that uses electric fuse at United States Patent(USP) No. 6,570.About the non volatile register of using NV NT switch pile employed term at table 1 with table 2 illustrates and at U.S. Patent application No.11/280, description in 786 and 11/280,599.

Transistor T 7 ' has added between node 85 and the ground connection, to be used for NV NT switch programming purpose.During the programming of NV NT switch, voltage source V _SOURCEBe applied to node 84.Transistor T 7 ' can be at V _SOURCEPass through input program/erase activation voltage V before or after the transformation _PEAnd be switched on, and can apply (or a several) potential pulse, and electric current can flow through NV NT switch 83, and depends on action required, and NV NT switch can be converted to high resistance state from low resistance state, or is converted to low resistance state from high resistance state.If transistor T 7 ' remains OFF, then NV NT switch 83 remains on equal state.NV NT switch 83 can be changed state once or can between ON and OFF state, circulate repeatedly.

Fig. 9 A illustrates the sectional view of the sub-Nonvolatile nanotube switch 90 of both-end.Nanostructured elements 93 is set on the substrate 95, and it comprises insulator layer 94.Channel length L _CHANNEL(L _{Raceway groove}) nanostructured elements 93 cover two terminals at least in part, like conducting

element

91 and 92, they all directly are deposited on the nanostructured elements 93.The method of making nanostructured elements has more detailed explanation in the patent references that is combined.

90 passivation of Nonvolatile nanotube switch relate to the dielectric layer 96 that deposition is fit on the Nonvolatile nanotube switch.One of this mode is exemplified as use through spin coating polyvinylidene fluoride resin (PVDF), polyimide or other insulating material that is fit to, and directly contacts with the Nonvolatile nanotube switch.Then, use suitable assisted dielectric diaphragm (for example alumina or silicon dioxide) to seal following PVDF, polyimide or other insulator, and the passivation strong to the Nonvolatile nanotube switching manipulation is provided.Nonvolatile nanotube switch 90 or 90 ' can be comprised (insertion) any point in integrated circuit technology stream.Be used for the typical programmed of switch 90 and wipe electric current being about the 1-50 microampere, promptly size is lower than required electric current two to three one magnitude of the conventional electric fuse of programming.

Fig. 9 B illustrates the sectional view of the sub-Nonvolatile nanotube switch 90 ' of both-end.Nanostructured elements 93 ' is set on insulator 97 and contact 91 ' and 92 '.Insulator 97 and contact 91 ' and 92 ' are set on the substrate 95 ', and it comprises insulator 94 '.Insulator 97 can have the heat conductivity lower than insulator 94 '.Has channel length L _{Raceway groove}Nanostructured elements 93 ' cover two terminals at least in part, like conducting element 91 ' and 92 ', it is deposition before the deposition of nanostructured elements 93 ' all.Switch 90 ' more is prone in semiconductor technology integrated than switch 90.

An advantage of structure 90 ' is a large amount of I ²The R power substrate that is depleted; Therefore, if select to have insulator 97 than 94 ' little heat conductivity, then nano tube structure switch in reduced-current the time can transfiguration be prone to because loss is few to the thermal change of following substrate.Do not expect bound by theory, the inventor believes that two-terminal nanotube switches can play a major role, because the heat in the structure causes the fracture and the formation again of the key of carbon-to-carbon and/or carbon-metal, like U.S. Patent application No.11/280,786 is said.Therefore, I haven't seen you for ages makes less voltage " disconnection " nanotube switch that applies to the heat of substrate in loss, thereby make switch switch to the OFF state.

90 ' the passivation of Nonvolatile nanotube switch relates to the dielectric layer 97 ' that deposition is fit on the Nonvolatile nanotube switch.One of this mode is exemplified as use through spin coating) polyvinylidene fluoride resin (PVDF), polyimide or other insulator, directly contact with the Nonvolatile nanotube switch.Then, use suitable assisted dielectric passivating film (for example alumina or silicon dioxide) to seal following PVDF, polyimide or other insulator, and the passivation strong to the Nonvolatile nanotube switching manipulation is provided.Nonvolatile nanotube switch 90 or 90 ' can be comprised (insertion) any point in integrated circuit technology stream.Nonvolatile nanotube switch 90 or 90 ' is at U.S. Patent application No.11/280, more detailed explanation arranged in 786 and 11/280,599.Typical programmed (wiping) electric current that is used for switch 90 ' is about the 1-20 microampere, or its size is lower than required tens of milliamperes electric current three one magnitude of the conventional electric fuse electric current of programming.

Fig. 9 C illustrates Nonvolatile nanotube switch 90 " before the passivation and corresponding to the SEM figure of the Nonvolatile nanotube switch 90 ' in Fig. 9 B sectional view.Nonvolatile nanotube switch 90 " comprise nanotube element 93 ", contact 91 " and 92 " and insulator 94 ".Nonvolatile nanotube switch 90 and 90 ' has been manufactured to has the channel length L of size at 250nm to 22nm _{Raceway groove}Thereby, reduce the Nonvolatile nanotube switch size and reduce program voltage, shown in following.

Fig. 9 D illustrates the sub-NRAM switch 90 of both-end " ' variant, it comprise have the suspention nano tube structure 98

suspention gap area

99 and 99 '.This structure is at U.S. Patent application No.11/280, and the nanotube switch of describing in 786 can have optimized electric and thermal property.The improved reason of switching capability 90 " ' is: in the zone of suspention, do not have heat loss to arrive substrate on every side.Therefore, nanotube is heated to preferred temperature so that less voltage and electric current (as at U.S. Patent application No.11/280, described in 786) only need to take place switch.The scope of this channel length is from about 50nm to hard contact 91 " the whole length of active region between ' and 92 " '.Another advantage of this structure is: do not need convergent-divergent to reduce lithography node to reach lower switching voltage.It should be noted, only use lower gap 99 promptly enough.

Suitable design conditions has been arranged, and nanotube will can only not interrupt in the zone of suspention.What anticipation obtained is that the nanotube of a part will be at substrate 97 in this structure " ' on switch to OFF, to allow the circulation of NRAM switch.

The hole that is used to suspend in midair the zone is available oxygen oxidizing gases (O for example also ₂Or O ₃) fill further to reduce to blow the required electric current of nanotube fuse.This will be useful to the OTP parts that does not need reprogramming.

Nonvolatile nanotube switch shown in Figure 9 is generally ON when processing.When Nonvolatile nanotube switch (the NV NT switch 16 shown in Fig. 1 C) can circulate good millions of times (shown in Fig. 1 C) between ON and OFF state, it was initially formed higher relatively resistance switch.Non-volatile breech lock 82 with reference to shown in Figure 8 if Nonvolatile nanotube switch 83 is similar to NV NT switch 16, then is in the R of conduction state _ONThe resistance range that will have 10 kilo-ohms to 50 kilo-ohms usually.If be similar to NV NT switch 16 about latch circuit 82NV NT switch 83 described NV NT Switch, then be in the R of non-conductive state _OFFUsually will have 1G Europe or higher resistance value.

Figure 10 A curve 100 illustrates works as L _{Raceway groove}When 250nm reduces to 50nm, channel length L _{Raceway groove}Reduce voltage scaling effect to the erasing voltage of Nonvolatile nanotube switch.It should be noted, in table 2, define about ON and the employed term of OFF state.L _{Raceway groove}Be called the switch channel length, as said about Fig. 9.The validity that channel length reduces illustrates according to erasing voltage; This erasing voltage is the function of channel length minimizing and erasing-programming cycle productive rate (cycling yield), and wherein each data point representes that 22 devices and the quantity in ON/OFF erasing-programming cycle are five.Erasing voltage is the majorant of channel length and when Nonvolatile nanotube switch (shown in curve 100 of Figure 10 A) when 250nm reduces to 50nm, erasing voltage drops to 5 volts from 8 volts.Corresponding program voltage (not shown) is less than erasing voltage, usually in 3 to 5 volts scope for example.To the erasing voltage of the structure that changes channel width (data not shown goes out) measure do not show erasing voltage to the device channel width (when channel width when 500nm becomes 150nm) remarkable dependence.To the erasing voltage of the structure of nanostructured to the contact terminal overlay length (data not shown goes out) that changes measure do not show erasing voltage to overlay length (when overlay length when 800 change to 20nm) remarkable dependence.

Figure 10 B illustrate to erasing voltage be 8 volts, correspondence to wipe electric current be 15 microamperes device, as the erasing voltage and the corresponding curve of wiping electric current 125 of the function of time.It should be noted that when test, negative voltage is applied to the Nonvolatile nanotube switch.The Nonvolatile nanotube switch is worked under the situation that arbitrary direction flows applying plus or minus voltage and electric current.Depend on the quantity of the interior SWNT that activates of nanostructured in the channel region, wipe electric current usually in 1 to 20 μ A scope.Program current is usually also in 1 to 20 μ A scope.For some NV NT switches, to have observed during programming, Control current flows can improve programming characteristic.The method that Control current flows with reference to Figure 17 in following description; These methods can be applied to programming with erase operation during the control of electric current.Obliterated data shown in Figure 10 B and the corresponding details of measuring be at U.S. Patent application No.11/280, describes in 786.Usually, the electric fuse program current is in tens of milliamperes of scopes, so the nt fuse reduces about 1000 times of program current.

Figure 10 C illustrates nearest loop-around data 150 on the device of channel width of passage length with about 22nm and about 22nm.Has the erasing voltage that the device of the channel length of about 20nm has 4 to 5 volts of scopes usually.Certain device shown in Figure 10 C has 5 volts erasing voltage, 4 volts program voltage, and experiences 100 times erasing-programming circulation.ON resistance (R _ON) just below 100 kilo-ohms, and OFF resistance (R _OFF) just more than 100 megaohms.

For example need 10 as the Nonvolatile nanotube switch of the shadow device of the heap of the non volatile register shown in Fig. 1 and 2 ⁴To 10 ⁶Inferior operation cycle, the non volatile register heap level of therefore additional (redundancy) is introduced into, and is as shown in Figure 2.For the latch circuit 82NV NT switch 83 that is in the OTP pattern, the single programming operation (seeing table 1 programming definition) as the Nonvolatile nanotube switch 83 of switch had the Nonvolatile nanotube switch productive rate near 100%.Even ON/OFF circulates when nanotube switch 83 receives several times, its productive rate is still near 100%.

When NV NT switch 83 is used for gating path 86, identical with the read operation that uses 71 pairs of latch circuits 70 of electrical fuse to the read operation of latch circuit 82.Therefore, if non-volatile heap latch stage K will be included as a level in the non volatile register heap 20 shown in Figure 2, then corresponding general latch circuit 82 is maintained at conduction state.Therefore, when corresponding latch circuit 82 during by gating, it is converted to foregoing second logic state, and wherein node 87 is in low-voltage and V on the node 88 _OUTBe in high voltage.If routing switch 30 is used to non volatile register heap 20, then export the positive voltage V on 88 _OUTBe transmitted to select signal input SK, CMOS conversion grid TR1 is activated and CMOS conversion grid TR2 is deactivated, as above said with reference to Fig. 3 A.Routing switch 30 connects input A and output C, and its output with 20 grades of K of non volatile register heap is sent to the input of 20 grades of K+1 of non volatile register heap, therefore level K is included in the non volatile register heap 20.

Read operation to latch circuit 82 when NV NT switch 83 is used for gating path 86 is identical with the read operation that uses 71 pairs of latch circuits 70 of electric fuse.Therefore, if non-volatile heap latch stage J will be excluded as a level in the non volatile register heap 20 shown in Figure 2, the NV NT switch 83 in the then corresponding latch circuit 82 is programmed to non-conductive state.Therefore, when corresponding general latch circuit 82 during by gating, it remains in foregoing first logic state, and wherein node 87 is in high voltage and V on the node 88 _OUTBe in low-voltage.If routing switch 30 is used to non volatile register heap 20, low (near zero) voltage of then exporting on 88 is transmitted to select signal input SJ, and CMOS conversion grid TR2 is activated and CMOS conversion grid TR1 is deactivated, as above said with reference to Fig. 3 A.Routing switch 30 connects input B and output C, and therefore it get rid of level J with the input of 20 grades of J+1 of output bypass to non volatile register heap of 20 grades of J of non volatile register heap in non volatile register heap 20.

It should be noted, for general latch circuit 82, if if node 88 for just and node 88 output can be used for selecting 87 outputs of signal input SK complementary node to can be used for the signal input SKb of selected on-off circuit 35, then a level K will be included in the register file 20.Yet, if node 88 is zero and can be used for selecting signal input SJ and complementary node 87 can be used for the signal input SJb of selected on-off circuit 35 that a level J will be excluded, as above said about latch circuit 70 in register file 20.

It should be noted that breech lock 82NV NT switch 83 can become the OFF state from the ON state, returns the ON state then, it is inferior arbitrarily then to return the OFF state.Therefore, the setting of breech lock 82 can change repeatedly according to expectation.The specific characteristic that this breech lock 82 is provided (because of NV NT switch 83 elements) provides the dirigibility of usefulness for the fabricator with for renewable, the re-configurable product in scene on module layer.

Latch circuit 82 output nodes 88 are corresponding to general latch circuit 70 output nodes.Latch circuit 82 nodes 87 (being the benefit of output node 88) are corresponding to latch circuit 70 nodes 77.If the intrinsic breech lock breaking resistor of latch circuit 82 is designed to 100 kilo-ohms, then latch circuit 82 can be to responsive for more by the caused disturbance of cosmic rays of the α particle that hole-electron pair produced.Therefore, can ballast capacitor 89 be added into output node 88, and can ballast capacitor 89 ' be added into complementary node 87.The ballast capacitor value for example can be 10 to 20fF.

Use the non-volatile latch circuit of selection of configuration circuit to select

Above-mentioned general latch circuit 70 (Fig. 7) and latch circuit 82 (Fig. 8) can be used as the non-volatile configuration breech lock 1 of electronic programmable to N+M, and the corresponding output signal S1 to S (N+M) (as shown in Figure 2) of supply.Selection of configuration circuit 26 (Fig. 2) can be used to judge the state of latch circuit output, thereby confirms that which non volatile register heap level is included in the non volatile register heap

20.Latch circuit

70 and 82 can be applied to storer, logic, numeral and simulation unit and embedded product generally, and is not limited to non volatile register heap example.It should be noted that latch circuit 40 (Fig. 4) does not need selection of configuration circuit 26, because the state of latch circuit 40 is confirmed by laser ablation.

In one realized, selection of configuration circuit 26 can be the decoder logic (as being used for the subsequent use column or row selection of memory array) with control input.Reconfigure latch circuit in order to the redundant row alignment that replaces the ranks line of memory array in DRAM and the SRAM storer at Itoh; The reference book of Kiyoo " VLSI Memory Chip Design "; Springer-Verlag Berlin Heidelberg 2001; Describe among the pp.178-183, its full content is incorporated into this by reference.

Substitute in the realization one, selection of configuration circuit 26 can use configuration control register, and like United States Patent (USP) Re.34,363 is said.Because of easily forming non volatile register shown in Figure 2 and pile 20 with non volatile register heap latch stage is integrated, configuration control register is selected as selection of configuration circuit 26 in this example.

Figure 11 illustrates the diagrammatic sketch of configuration control register 110, has shown two levels of multistage offset register, at United States Patent (USP) Re.34, more detailed explanation is arranged in 363.Configuration control register 110 illustrates two offset register unit, but the actual disposition control register comprises a plurality of unit that configuration logic unit is required, is N+M offset register unit in this example.Basic offset register unit comprises the switching device 112-1 that connects with phase inverter INV-1 ', and this phase inverter INV-1 ' connects with switching device 116-1, and switching device 116-1 connects with phase inverter INV-1.The output of phase inverter INV-1 is fed back to the input of phase inverter INV-1 ' via switching device 114-1; Thereby launch CELL-1 stored logic state, as long as configuration control register 110 is kept power supply (operation of volatibility offset register) and HOLD voltage remains high.The output of phase inverter INV-1 also is connected to the input of offset register CELL-2 (it is identical with cell 1), and also is connected to the terminal of switching device 118-1.The output of phase inverter INV-1 ' is connected to the input of switching device 116-1.Two clock Ψ 1 that do not overlap are connected to the control grid of switching device 112-1 and 116-1 respectively with Ψ 2, and are connected to the corresponding conversion device of other offset register unit.The corresponding conversion device of switching device 114-1 and other unit depends on the state of HOLD input, launches or forbid the feedback path between INV-1 output and the INV-1 ' input.Redundant data is transferred into configuration control register 110 through LOGIC INPUT signal.When APPLY control input is activated, output C1, C2 ... C (N+M) is converted to the programming input of breech lock (such as breech lock 70 and breech lock 82).In this example, configuration control register 110 is used as the selection of configuration circuit 26 of Fig. 2.

In operation, whole configuration control register 110 can be set to high or low voltage for height and HOLD voltage for low through setting Ψ 1 and Ψ 2 voltages.Be set under the high-tension situation at HOLD, clock Ψ 1 and Ψ 2 can be used to

logical schema

1 and 0 is sent in the offset register, with (or not programming) the non-volatile configuration breech lock 1 of programming based on test result (productive rate figure) ... N+M.Should speak and allow the configuration control register 110 that chien shih INPUT signal when enough transmits whole length.On this time point, APPLY can be converted to positive voltage and phase inverter output C1, C2 ... C (N+M) is transferred into corresponding configuration control breech lock 1 ... N+M.

Referring to Fig. 2, configuration control register 110 can be used as the selection of configuration circuit 26 that is used for non volatile register heap 20, and it exports C1 ... C (N+M) controls non-volatile configuration breech lock 1 ... The state of non-volatile configuration breech lock (N+M).Non-volatile configuration breech lock 1 ... (N+M) be programmed to keep corresponding configuration control register 110 logic states.

If latch circuit 70 is used as non-volatile configuration control breech lock; Then the OTP state is stored in each non-volatile configuration control breech lock, and single non-volatile heap register stage is selected from N+M single non-volatile heap register stage and quilt interconnects to form non volatile register heap 20.This register file configuration can not be changed.

Alternatively, if latch circuit 82 is used as non-volatile configuration control latch mode, then non-volatile ON or OFF state are stored in the NV NT switch 83.Because NV NT switch 83 is non-volatile nanotube switch; So NV NT switch 83 can circulate repeatedly between ON and OFF state; Make configuration control breech lock to circulate, and therefore the configuration of non volatile register heap 20 can change (even at the scene) from its virgin state through several logic states.

Based on the non-volatile signal source that the Nonvolatile nanotube switch is piled as the non volatile register of program means

Can replace selection of configuration circuit 26 and non-volatile configuration breech lock 1 to N+M through the non-volatile configuration heap 122 that shown in figure 12 comprising has the non-volatile configuration register heap level 1 to N+M of output S1 to S (N+M).Non-volatile configuration heap 122 and the non-volatile configuration heap 120 of being combined to form of non-volatile configuration heap 124.Non-volatile configuration heap 120 is corresponding to non-volatile configuration heap 20.

Comprising non-volatile configuration control register heap level 1 ... In first configuration of the non-volatile configuration heap 122 of level (N+M), the input data of the form of the input traffic of logical one and " 0 " are loaded in the register 122.Non-volatile configuration register heap level is identical with non volatile register heap level.Yet round-robin quantity is limited.For example, in this case,, wipe (the breech lock term is " programming ") and only on selected Nonvolatile nanotube switch, carry out once (1/2 circulation) for the OTP operation.Above about

latch circuit

70 and 82 further described corresponded manners in, productive rate is high (for example between 99 and 100%), and output S1 to S (N+M) selects or (bypass) non volatile register heap level is selected in cancellation.About breech lock 70, programming is possible because the electrical fuse mode of blowing has only OTP.About breech lock 82, several operation cycle are possible, because the electronics blown fuse is replaced by the Nonvolatile nanotube switch.

When operation, this first configuring non-volatile configuration register 122 can be carried out to wipe with program cycles about the described operator scheme input of Fig. 1 and change for several times through use.Change into several circulations through restriction; For example 1 to 3 circulation; Non-volatile configuration control register 122 productive rates remain between 99% and 100%, are provided at factory-configured non volatile register heap (comprise or gets rid of (bypass) each level) simultaneously or (transport after the product) as required the ability of configuring non-volatile register file (changing the level of included/eliminating) more at the scene.

Based on the non-volatile signal source that the Nonvolatile nanotube switch is used as the new configuration sequence breech lock of program means

In second configuration, non-volatile configuration control register 132 is shown in Figure 13 A.Register 132 is the variant of register 122, makes 1/2 circulation only carry out and once wipes (the breech lock term is " programming "), the Nonvolatile nanotube switch productive rate of correspondence is brought up to 99 and 100% scope, as said hereinafter about Figure 13 B.It should be noted, in Figure 13 A, the Nonvolatile nanotube switch wipe programming corresponding to electrical fuse.Figure 13 B is the variant of register stage 15 among Figure 1B.Non-volatile configuration register is piled the input data (it is loaded in the register 132) of 132 RLs " 1 " and " 0 " input traffic form.Non-volatile configuration register heap level is above variant about the described non-volatile heap level of Figure 1B, makes only to allow to wipe 1/2 cycling, productive rate is increased to 99 to 100% scopes.Thus, when in the OTP pattern, operating, the class of operation of non-volatile configuration register heap 132 is similar to the operation of non-volatile configuration register heap 122, allows to wipe (the breech lock term is " programming ") 1/2 circulation; And be similar to Fig. 2, have the selection of configuration circuit 26 that uses configuration control register 110 and use latch circuit 70 or latch circuit 82 supply control signal S1 ... The non-volatile configuration breech lock 1 of S (N+M) ... (N+M).

When operation, this second non-volatile configuration register 132 can use half the circulation erase operation and only be changed once.This operator scheme following about Figure 13 B explanation.

OTP non volatile register breech lock 135 is the variant of the non volatile register heap 15 shown in Figure 1B, and wherein erase_enable_NFET 1320 is eliminated and is connected replacement with

NFET

1321,1322 and phase inverter 1323 with corresponding.The terminal of NFET 1321 is connected to ground connection and another terminal is connected to NFET 1322, itself then be connected to node 1116 '.The input of NFET 1321 is by the output 1350 ' control of high voltage change-over circuit 1360 ', and the input of NFET 1321 is by the output control of phase inverter 1323.The input of phase inverter 1323 is connected to the output of phase inverter 1330, and it also drives the grid of PFET 1343.

When operation, the PROGRAMENABLE (program enable) of the non volatile register heap level 15 shown in Figure 1B has been eliminated and has converted to OTP ERASE ENABLE (OTP wipes and enables) input, shown in the non-volatile configuration controlled stage 135 shown in Figure 13 B.The programming be eliminated and one wipe 1/2 the circulation be allowed to.

Based on the non-volatile signal controlling source that is used for being directed against more at a high speed and increases the non-volatile breech lock of nanotube of productive rate optimization key path time sequence

More than further described non volatile register heap comprise high speed volatile register (each level comprises principal and subordinate's breech lock usually) and for example be coupled to each Nonvolatile nanotube switch (NVNT switch) from breech lock.NV NT switch can directly be coupled to from breech lock, maybe can use coupled circuit to be coupled.Except the productive rate of the nonvolatile operation of above further described optimization non volatile register heap breech lock, also need the high speed performance of optimization volatile register.Equally, be not all register files need be non-volatile.Yet register file needs (high clock speed) synchronous operation at a high speed.

When being in high clock speed, when for example surpassing 1GHz, the productive rate of register breech lock reduces owing to device parameters changes, and these device parameters variations cause logical delay or high-speed cache to postpone.These parameters change and can take place in each batch during manufacture, and change under the situation about also using at the scene.For example, synchronously on CPU and the plate high-speed cache can needs for example 170ps or cache accessing time still less, can be ready at the CPU terminal after the clock period after sending the cpu data request from the data that high-speed cache is read guaranteeing.

Variable delay circuit can be introduced in crucial timing and/or the signal path, changes the loss of yield that (for example parameter drift) causes with optimize performance and during minimizing manufacturing because of the parameter during the product operation in parameter variation and the scene between each batch.Have the ON state that can be in, OFF state, and the latch circuit of the Nonvolatile nanotube switch (NV NT switch) of the state that between ON and OFF, switches be used to the crucial timing path of optimization.

Figure 14 A illustrate use two non-overlapping clock CLK1 and CLK2 through (pipelined) of pipelined synchronous logic function 1400, comprise the asynchronous logic level 1410 and 1414 (with other not shown person) of being separated of operating and be designed for the high speed operation of present technical level (state-of-the-art) with synchronous mode by register file 1407,1412,1418 (with other not shown person).Exemplary register 1412 is formed by master (L1) breech lock 1420M with from (L2) breech lock 1420S.Main (L1) breech lock 1420M is formed and is made up of register cell 1 '-n ' from (L2) breech lock 1420S by register cell 1-n.To forming, for example be made up of the register cell k and the k ' of correspondence by register stage 1416 by corresponding register cell for register stage.Importantly, it should be noted that logic level 1410 and 1414 can be made up of asynchronous random logic level, maybe can be high-speed cache on the synchronous plate (for example high-speed synchronous SRAM L1 high-speed cache).When being activated by clock CLK1, main (L1) breech lock (such as like main (L1) breech lock 1420M) receives data, the seizure from previous logic level 1410 and keeps the input data.When being activated by clock CLK2, from (L2) breech lock (for example from (L2) breech lock 1420S) receive self-corresponding master (L1) breech lock 1420M information, this information is sent to next logic level 1414, the then information that finishes near the CLK2 clock period of breech lock.The example of register (breech lock) design is at list of references H.B.Bakoglu, " Circuits, Interconnections; and Packaging for VLSI ", Addison-Wesley PublishingCompany, Inc; Illustration among the pp.338-349, its full content is incorporated into this by reference.

Cause the variation of technological parameter of variation and the interconnection line resistance and the electric capacity of transistor electrical specification can cause causing logic contest (race) situation of logic error.For example, the logical one of Figure 14 A can comprise one or more relative logical paths than the long delay time that have, and it prevents to change the logical one state completion logic operation before that causes by master (L1) breech lock 1420M sampling at CLK1.The too early sampling of logical one state causes the breech lock and the transmission of incorrect logic state.This contest situation problem only can take place in a responsive especially logical circuit, the logical one in this example for example, or in several logical circuit paths, take place.Parameter is changed the result that responsive key Design path is known as logical simulation usually.In clock CLK1 and CLK2 sequential, make tolerance, to avoid this contest situation problem.Yet when the clock frequency increases to 2Gb to greater than 5Gb from 1Gb, become more key and loss of yield of best performanceization can take place at high clock frequency.

Figure 14 B illustrates performance through optimized synchronous logic function 1400 ' through pipelined.Controllable delay circuit 1425 and 1425 ' is added to respectively in CLK1 and the CLK2 clock signal path; So that postpone the transformation of the logic state of main (L1) breech lock 1420M sampling logical one circuit, and postpone fringe time from (L2) breech lock 1420S about master (L1) breech lock 1420M.Controllable delay circuit element can be added to one or more sequential key (or responsive) signal path or all signal paths.The clock signal delay of being introduced by controllable delay circuit 1425 and 1425 ' examples of circuits further specifies hereinafter.

Figure 15 A illustrates synchronous CPU and the cache systems 1500 that comprises CPU 1510 and high-speed cache 1515, and its CPU and high-speed cache are synchronous through clock signal clk.Memory address locations and control signal are provided to high-speed cache 1515 through CPU 1510; And data can use write operation to be stored in high-speed cache 1515 through CPU1510, and perhaps data can use read operation to be sent to CPU 1510 from high-speed cache 1515.Figure 15 B illustrates the sequential chart 1525 that is used for the high-performance cache read, and wherein the clock circulation of cached data after request of data can be used CPU 1510.Clock 1530 is converted to high voltage in the request of data time from low-voltage.When the request of data clock changed, the operation that control signal identification is desired was a read operation in this figure.Equally, the address is effective.High-speed cache 1515 is accomplished read operation and is made data output V in a clock period _DATAIn data window 1535 (be commonly referred to " data eye (data eye) ") for effectively.The transformation of clock 1530 data capture CPU 1510 (one-period after clock 1530 requests change) quilt is regularly to take place in the middle of data window 1535.Figure 15 A self-reference document K.Itoh, " VLSI Memory ChipDesign ", Springer, 2001, the pp.358-363 reorganization, its full content is incorporated into this by reference.

Output driver 1520 receives signal V through data routing on high-speed cache 1515 chips _SIGOutput driver 1520 is shown as three-state driver; Yet, can use non-three-state in some applications.Three-state driver in the industry cycle is well-known, referring to for example R.J.Baker, " CMOS:CircuitDesign, Layout, and Simulation, IEEE Press, 1598, p.226 ", its full content is incorporated into this by reference.Output phase inverter (driver) uses NFET transistor T 1 and PFET transistor T 2 to form, and corresponding T1 is electrically connected to public phase inverter input 1522 with the T2 grid, and the T2 drain electrode drains with T1 and is electrically connected to public output 1523.The drain electrode of ternary PFET T4 is connected to the source electrode of T2, and the source electrode of T4 is connected to power supply (V for example _DD), and the grid of T4 is connected to the output of phase inverter INV, the input of this phase inverter INV is connected to public ternary input 1524.The drain electrode of ternary NFET T3 is connected to the source electrode of T1, and the source electrode of T3 is connected to ground connection, and the grid of T3 is connected to public ternary input 1524.

When operation, if three-state driver 1520 activates tri-state mode, then V _TRI-STATE(V _Ternary)=0 volt, and T4 and T3 are in the OFF state.For signal V _SIGAny value, output node 1523 can't be connected to power supply V _DDOr ground connection.Therefore, node 1523 voltages can't help 1520 qualifications of three-state driver, but can replace setting by the three-state driver (not shown) of other shared node 1523.When high-speed cache 1515 is activated by requests for data (shown in Figure 15 B), director cache makes V _TRI-STATEBe transformed into positive voltage from zero, it makes T3 and T4 transistor become the ON state.In ternary shutdown mode, transistor T 2 drain electrodes are connected to V via transistor T 4 _DDAnd transistor T 1 source electrode is connected to ground connection via transistor T 3, and V _SIGV on the Control Node 1523 _DATAThe output signal.In response to 1510 request of data of the CPU shown in Figure 15 B, inverter drive signal V _SIGProvide by data routing on high-speed cache 1515 chips (it can comprise pre-driver level (not shown)).

When operation, because the caused transistor parameter variation of operating period parameter drift in time can cause the changeability of the position of valid data window 1535 in manufacturing and the scene.Figure 15 D waveform 1540 illustrates fast data routing valid data window 1545, wherein output data V _DATAIn clock 1530 circulations is available in early days.Clock 1530 reading of data change the trailing edge that betides valid data window 1545, and wherein data possibly have shortcoming, shown in Figure 15 D.Figure 15 E waveform 1540 ' illustrates slow data routing valid data window 1550, wherein output data V _DATAIn the 1530 circulation later stages of clock is available.Clock 1530 reading of data change the leading edge that betides valid data window 1550, and wherein data possibly have shortcoming, shown in Figure 15 E.Therefore needing a kind of mode to minimize the valid data window changes with optimize system performance, productive rate and reliability.

Figure 15 F illustrates synchronous CPU and cache systems 1500 ', and wherein the high-speed cache 1515 of CPU and cache systems 1500 is modified through adding controllable delay circuit element synchronously, so that high-speed cache 1515 ' data are exported V _DATAOptimization valid data window.Controllable delay circuit element (or more than a controllable delay circuit element) can be added to and read/high-speed cache 1515 ' data routing between latch circuit and the output driver.

Figure 15 G illustrates a mode, and wherein controllable delay circuit 1560 has the data-signal of being connected to V _SIGControllable delay circuit 1560 input and be connected to controllable delay circuit 1560 outputs of the public phase inverter input 1522 ' of output driver 1520 '.Controllable delay circuit 1560 further specifies hereinafter.The V of public phase inverter input 1522 ' _SIGThe controllable time quantum of input delay, it is set by controllable delay circuit 1560.Outputting data signals V on public output 1523 ' _DATADelay is corresponding to the V that is set by controllable delay circuit 1560 _SIGThe time of time.Except adding controllable delay circuit 1560, the interconnection of circuit component, element and the operation of output driver 1520 ' are corresponding to the explanation of output driver 1520.If needs are arranged, V _TRI-STATESequential can by the adjustment (not shown).

In when operation since make and the scene in operating period the caused transistor parameter of parameter drift in time variation can cause the changeability in the position of valid data window to be eliminated, like Figure 15 H waveform 1540 " shown in.Waveform 1540 " the waveform V that CLK 1930 data captures that have in the middle of valid data window 1555 change is shown _DATA

Figure 16 illustrates controllable delay circuit 1600, and it is designed to be adapted to select one of four delay path 1-4.For example, clock CLK can be postponed, and produces CLK _DEL(CLK _Postpone), or signal VSIG can be postponed generation signal V _SIG-DEL(V _Signal-delay).Chip can comprise a plurality of controllable delay circuits 1600.

In an example, controllable clock delay can be introduced in shown in Figure 14 B in the synchronous logic function 1400 ' of pipelined, wherein controllable delay circuit 1600 can be used as controllable delay circuit 1425 and 1425 '.

In another example, controllable clock delay can be introduced among the synchronous CPU and cache systems 1500 ' shown in Figure 15, and wherein controllable delay circuit 1600 can be used as controllable delay circuit 1560.CPU 1510 can operate in the clock frequency of 2GHz, and the 1515 ' access time of high-speed cache of a clock period is 170ps.Therefore, be available as 170ps from CPU 1510 request of data to high speed buffer memory 1515 '.Suppose that the valid data window is 150ps, then delay path 1-4 can set as follows: path 1 is about zero; Path 2 is about 30ps; Path 3 is about 80ps; Path 4 is about 150ps.Controllable circuit delay 1600 is selected one of data routing 1-4, with the interfix of valid data window 1555 or near the 1530 transformation of data times of clock, like waveform 1540 among Figure 15 H " shown in.

Figure 16 comprises the delay circuit 1605 with four delay path 1-4, though can comprise the delay path (or option) of more or less quantity.The input of delay circuit 1605 is to postpone the clock CLK of controlled quatity or signal V _SIGWaveform.Through selecting one of four (in this example) delay path 1-4, corresponding delayed clock CLKDEL or the delayed signal V of piece 1610 outputs in logical delay _SIG-DELWaveform.Postpone to select logical one 615 to provide in order to select delay selection signal S1, S2, S3, the S4 of one of four CMOS switching device TD1, TD2, TD3 or TD4.Corresponding phase inverter IS-1, IS-2, IS-3, IS-4 produce complementary S1, S2, S3, S4 logical signal respectively, with at each CMOS switching device TD1 ... TD4 is last to be launched true and complementation selection signal.

Postpone to select logical one 615 input V _OUT-1(V _Output-1) and V _OUT-2(V _Output-2) be used to select four to select signal S1 ... One of S4.V _OUT-1And V _OUT-2Be respectively the output of NT switch breech lock 1620 and NT switch breech lock 1620 '.NT switch breech lock 1620 and 1620 ' is corresponding to latch circuit shown in Figure 8 82, and it comprises that use is through the nanotube fuse (nt fuse) of convergent-divergent and can be programmed and wipe Nonvolatile nanotube switch 83 repeatedly.Above-described term is used.For example, in latch circuit is used, be converted to the OFF state from ON and be called as programming (NV NT switch then for wiping) and OFF to ON and be called as wipe (then being to programme) in NV NT switch.Input signal V _PRECHARGE(V _Precharge), V _STROBE(V _Gating), V _BIAS(V _Biasing), V _PE, V _SOURCE(V _{The source}) further specify about breech lock 82 above.These input signals are by delay controller 1625 supplies.Through allow with each NT switch breech lock 1620 and 1620 ' be programmed for that VOUT-1 is in high-voltage state or low-voltage state and VOUT-2 be in high-voltage state or low-voltage state through programming state or erase status (further specifying ground about breech lock 82) as above, the input of the logic of delay controller 1625 is used to select one of four delay path 1-4.Drive circuit 1630 and 1630 ' produces V _SOURCEThe signal input, as be discussed in further detail below.The logic input of delay controller 1625 can be supplied via the logic (not shown) through tester at the manufacturer place, and/or through (BIST) testing engine (not shown) supply of testing oneself on the plate, to carry out the on-the-spot best performanceization of upgrading.

About delay circuit shown in Figure 16 1605, delay path 1 is about zero; Delay path 2 can be set as 30ps (if phase inverter I2-1 and I2-2 respectively are designed to 15ps); Delay path 3 can be set as 80ps (postponing if phase inverter I3-1, I3-2, I3-3, I3-4 respectively are designed to 20ps); Delay path 4 can be set as 150ps (postponing if phase inverter I4-1, I4-2, I4-3, I4-4, I4-5, I4-6 respectively are designed to 25ps).The CMOS inverter design meets known industry practice.About the waveform 1540 shown in Figure 15 H ", for the valid data window 1555 of 150ps, select for a moment clock 1530 data time sequences being changed of delay path 1-4 to be placed on or near the mid point of valid data window 1555.Circuit 1605 can be designed to have the combination of more data routing or data routing, for more accurate signal delay control increase.

When changing the state of NV NT switch (the NV NT switch 83 in the latch circuit 82 for example shown in Figure 8), drive circuit 1630 and 1630 ' is activated, and wherein latch circuit 82 operations are corresponding to non-volatile NT switch breech lock 1620 and 1620 ', as stated.Three drive circuits 1630 and 1630 ' example provide in Figure 17.First drive circuit, 1700 working voltage change-over circuits shown in Figure 17 A are to provide output source voltage V _SOURCE(corresponding to V shown in Figure 16 _SOURCE-1And V _SOURCE-2) and do not need Current Control.Second drive circuit, 1700 ' working voltage converter shown in Figure 17 B provides output voltage V _OUT, and use the voltage V that is applied to a succession of transistorized grid _I-CONTROL(V _{Current Control}) control output current I means to limit electric current as required.The 3rd drive circuit 1700 shown in Figure 17 C " the working voltage converter is to provide output voltage to current mirror, and it transfers the output current I that control is associated with V output.

Drive circuit 1630 and 1630 ' (it can use

drive circuit

1400,1700 ' or 1700 ") can change the state of the NV NT breech lock in each NV switch breech lock 1620 and 1620 ', and therefore confirm V _OUT-1And V _OUT-2State (high or low voltage), as shown in table 3.High voltage (high V) output is corresponding to the NV NT switch of ON position, and low-voltage (low V) output is corresponding to the NV NT switch of OFF position, as above latch circuit 82 about Fig. 8 the above.NV NT switch circulation result 16 shown in Fig. 1 C illustrates the ON resistance R with about 10 kilo-ohms to 50 kilo-ohms scope _ON(R _Lead _Logical) and have the OFF resistance R greater than 10G Europe _OFF(R _End) NV NT switching manipulation scope.

V _OUT-1	V _OUT-2	S1	S2	S3	S4
						High V	High V	X
High V	Low V		X
						Low V	High V		X
Low V	Low V				X

Table 3

Figure 17 illustrates and can be used to be limited in supply V _SOURCETo NT switch breech lock shown in Figure 16 or such as U.S. Patent application No.11/280; In 786 and 11/280,599 the circuit of the electric current during the Nonvolatile nanotube switch change state during NT switch breech lock of nram memory array bitline of illustrative nram memory array bitline.The electric current restriction is the most useful during (being commonly referred to programming NV NT switching manipulation) from OFF-to-ON state-transition, and do not use to-OFF state-transition (be commonly referred to and wipe NV NT switching manipulation) at ON-usually.NV NT switch ON shown in Fig. 1 C and OFF resistance circulation result 16 are activated by the laboratory able to programme voltage source of belt current restriction during from OFF-to-ON state-transition (from greater than 10G Europe to 10 kilo-ohm ON resistance range to 50 kilo-ohms).

Drive circuit 1700 shown in Figure 17 A comprises driver 1705, phase inverter INV-1, electric pressure converter 1710.Driver 1705 has the input 1707 of being supplied by delay controller (for example delay controller 1625).The input of the phase inverter INV-1 of the grid of the grid of the output 1709 driving N FET T20 of drive circuit 1700 and its output driving transistors T10.

Electric pressure converter 1710 comprises NFET T10 and T20, and its source electrode is connected to ground connection, and drain electrode is connected to the drain electrode of PFETs T30 and T40 respectively.The source electrode of PFET T30 and T40 all is connected to voltage source V _HIGHThe channel length that depends on the NV NT switch of the latch circuit 1620 shown in the curve 100 that is used for Figure 10 A and 1620 ', V _HIGHUsually can be in from 8 volts to scope less than 5 volts.The grid of PFET T30 and T40 is by cross-couplings.Output voltage source V on electric pressure converter 1710 lead-out terminals 1730 _HIGHControl output voltage under the situation that does not have the extra current control circuit.Terminal 1730 is connected to a terminal of the NV NT switch in the latch circuit, the terminal of latch circuit 82 for example shown in Figure 8.

When operation, if driver 1705 is output as positive voltage (for example 2.5 volts), then NFETT20 is that ON and NFET T10 are OFF.Lead-out terminal 1730 ground connection make PFET T30ON, and it is urged to V with terminal 1730 ' _HIGH, make PFET T40OFF.Yet if driver 1705 is in zero volt, NFET T20 is that OFF and NFET T10 are ON.Terminal 1730 ' is in zero volt, makes PFET T40ON, and it is urged to V with terminal 1730 _HIGH, make PFET T30OFF.V _SOURCEBe in voltage V _HIGH, it can be in from for example 5 to 8 volts scope usually, and the state of the NV NT switch (the NV NT switch 83 in the breech lock 82 for example shown in Figure 8, its terminal 1730 is connected to terminal 84) that causes being connected changes.

When driving N V NT switch (switch 83 as shown in Figure 8), the interpolation of current limit circuit can promote to become the OFF state or become the ON state from the OFF state-transition from the ON state-transition.Driver 1700 ' is identical with driver 1700, and except the output node 1730 of electric pressure converter 1710 is connected to the first terminal of switching device 1715, its grid (second terminal) is by V _I-CONTROLControl, and the 3rd terminal provides the output voltage V of electric current I _SOURCEElectric current I is by voltage V _I-CONTROLVoltage on input voltage and terminal 1730 and 1735 is confirmed.Switching device 1715 can be operated in the range of linearity or current saturation zone.Drive circuit 1700 provides V on lead-out terminal 1735 _SOURCEWith electric current restriction I.V _SOURCEBe in voltage V _HIGH, it usually can be in 5 to 8 volts scope for example, thus the change of the state of the NV NT switch (the NV NT switch 83 in the breech lock 82 for example shown in Figure 8, its terminal 1735 is connected to terminal 84) that causes being connected.Electric current I can be controlled in 1 to 50 μ A scope usually.

When operation, driver 1700 ' is similar to the operation of above-described driver 1700; Except supplying output voltage V _SOURCEThe time electric current be restricted to electric current I.

When driving the NV NT switch of switch 83 shown in Figure 8, use the interpolation of the current limit circuit of conversion grid (the for example conversion grid 1715 shown in Figure 17 B) enough Current Control can be provided.Driver 1700 shown in Figure 17 C " introduce current mirror 1720 with Control current I ' more accurately.Electric current I ' (its grid is connected to drain electrode, and source electrode is connected to V by series connection NFET T50 _SS) resistor R confirm.NFET T55 also makes source electrode be connected to V _SS, grid is connected to the grid of NFET T50, drain electrode is connected to the drain electrode of PFET T60.The source electrode of PFET T60 is connected to the output 1730 of electric pressure converter 1710, and the grid of PFET T60 is connected with drain electrode.Output PFET T65 makes grid be connected to the grid of PFETT60, and the source electrode of PFET T65 is connected to terminal 1730, the drain drives output 1740 of PFET T65, and output 1740 is connected to a terminal of NV NT switch.PFET T65 device supply V _SOURCE, and electric current is limited to I '.Drive circuit 1700 " on lead-out terminal 1740, V is provided _SOURCEWith the electric current that is limited to I '.V _SOURCEBe in voltage V _HIGH, it can be in from for example 5 to 8 volts scope usually, thus the change of the state of the NV NT switch (the NV NT switch 83 in the breech lock 82 for example shown in Figure 8, its terminal 1740 is connected to terminal 84) that causes being connected.Electric current I ' can be controlled in 1 to 50 μ A scope usually.

In when operation, driver 1700 " be similar to the operation of above-described driver 1700 '; Except supplying output voltage V _SOURCEThe time, electric current is restricted to electric current I through using current mirror '.Current mirror 1720 provides the preferable control of output current.Current mirror operates in list of references R.J.Baker, and " CMOS:Circuit Design, Layout, and Simulation ", IEEE Press, 1998, describe among the pp.427-433.

NV NT switch circulation result 16 shown in Fig. 1 C shows to have about 10 kilo-ohms of ON resistance R to 50 kilo-ohms of scopes _ONWith the OFF resistance R that has greater than 10G Europe _OFFOpereating specification.The repeatedly adjustment that this ON of NV NT switch resistance value and OFF scope can be used to delay circuit, with during fabrication and with the scene in product operation during (as stated) be used for the sequential optimization.

NV NT switch R _ONAnd R _OFFValue (is in the ON state) and after circulation, measures when processing.Some NV NT switches show similar value and the round-robin R when processing _ONValue.R when other NV NT switch shows lower processing _ONValue and higher circulation R _ONValue, in some situations, round-robin R _ONValue can be and is higher than for example 10 times.R _OFFValue is in 1G Europe and higher scope usually.

Nonvolatile nanotube switch ON-resistance control circuit and integrated in nram memory

NV NT switch resistance by SWNT-to-SWNT, MWNT-to-MWNT and SWNT-be combined to form to the series connection/parallel connection of-MWNT combination, it forms continuous power path (like the NV NT switch 90 of Fig. 9 C ") between two terminals.NV NT switch OFF resistance value is generally 100 megaohms and Geng Gao and usually greater than 10G Europe, and usually greater than ON electricity class value several orders of magnitude.NV NT switch ON resistance value can from for example 1 kilo-ohm to 1 megaohm.NV NT switch ON shown in Fig. 1 C and OFF resistance circulation result 16 programming OFF-to-ON state from be converted to greater than 10G Europe 10 kilo-ohms to 50 kilo-ohms the ON resistance range during, use the laboratory able to programme voltage source of belt current restriction.For application-specific, U.S. Patent application No.11/280 for example, the NRAM array described in 786 and 11/280,599, expectation realizes ON distribution of resistance more closely, the resistance range that for example is not more than 2 times changes.Resistance control circuit in order to programming NV NT circuit further specifies as follows.

Figure 17 D illustrates NRAM array element 1760 is driven to being in the Nonvolatile nanotube switch resistance control circuit 1755 of selected state, and wherein NV NT switch resistance control circuit 1755 is used to the Nonvolatile nanotube switch SW resistance value R that produced during the control programming operation (NV NT switch OFF-to-ON change) _SWSuppose Nonvolatile nanotube switch SW resistance value R _SW, program cycles is in the high resistance state of having wiped (for example 100M Ω to 1G Ω or higher) when beginning.Word line WL becomes high voltage, and it is with resistance in series R _ONMake and select transistor T SELON, thereby in NRAM array element 1760, select the Nonvolatile nanotube switch SW.Other selection transistor along bit line BL remains on the OFF state, makes to be selected for programming along other Nonvolatile nanotube switch of bit line BL.

Nonvolatile nanotube switch resistance control circuit 1755 shown in Figure 17 D comprises differential amplifier 1745 on the modified chip, bit line driver 1750, resistor R 1 and R2 and output PFET T6.Differential amplifier design, operation and simulation are people's such as R.Baker " CMOS:Circuit Design, Layout, and Simulation "; IEEE Press, 1998, describe among the pp.579-595; And drive circuit designs and operates in H.B.Bakoglu " Circuits, Interconnections, and Packagingfor VLSI "; Addison-Wesley Publishing Company, Inc, 1990; Describe among the pp.171-178, its full content is incorporated into this by reference.The resistor R 1 and the R2 of series connection (have voltage V _ANode A, and electric current is I) be added to differential amplifier 1745 first the input in, it still is the grid of the NFET T2 shown in Figure 17 D.Figure 17 D also comprises output (PMOS) device T6, has big width W and channel length L (W/L) ratio, for example 10/1 to 100/1 or bigger, and the source electrode of T6 is connected to voltage bit line driver 1750 output V _DR, and the drain electrode of T6 is connected to the voltage V that is in NV NT switch resistance control circuit 1755 _BCommon node B.The grid of PFET T6 is connected to differential amplifier 1745 output D.NV NT switch resistance control circuit 1755 output node B also are connected to second input of differential amplifier 1745, and it still is the grid of NFET T3, and is connected to the bit line BL of NRAM array element 1760.Bit line driver 1750 output voltage V _DRBe provided to a terminal of resistor R 1, the source electrode of PFET T6 and the cell voltage of differential amplifier 1745.Resistor network is formed channel resistance and the R that comprises R1, R2, PFET T3 _SW, R wherein _SWBe the resistance of Nonvolatile nanotube switch SW in the NRAM array element 1760, be used to the resistance value R of CS SW through programming _SW, shown in Figure 17 D.When operation, as mentioned below, program voltage V _B=V _PROGAnd electric current I _BLCause the transformation of switch SW from OFF-to-ON state, and as voltage V _BApproximate voltage V _AThe time, electric current is reduced to below the program current value.The program current value can be like U.S. Patent application No.11/280, in 786 described 1 μ A to the 50 μ A scopes.

When operation, transistor T 1, T2, T4 are in the ON state usually.Transistor T 2 is in the range of linearity, is controlled with R2 by resistor R 1.Voltage on the grid of PFET T5 is controlled by common node C.The level of transistor T 3 control common node D.At R _SWBetween the initial tour from high resistance OFF state to lower resistance ON state, PFET T6 is in ON state (range of linearity).The W/L of FET is than using the FET that is in given technology node and being that known simulation technology (for example referring to people such as above-mentioned list of references Baker .) comes optimization to the corresponding Nonvolatile nanotube switch SW of selected channel length and width in the NV NT switch resistance control circuit 1755; Make when the RSW of NV NT switch SW is in predetermined ON resistance value; NV NT switch resistance control circuit 1755 makes transistor T 3OFF; This causes node D to rise and makes PFET T6OFF, therefore finishes program cycles in NV NT switch SW ON resistance value R _SWThe ON resistance value of NV NT switch SW can be programmed to predetermined resistance value, and for example 1 kilo-ohm to 1 megaohm scope, and it is at V _BApproximate V greatly _AShi Fasheng.

Work as V _DRNear program voltage value V _PROGThe time (usually for example 3.5 to 8 volts of scopes in), R _SWBe programmed and R _SWBe converted to the ON state.During programming, work as R _SWValue do not use circuit (for example NV NT switch resistance control circuit 1755) when directly controlling, R _SWProgramming after the ON resistance value can for example 10 kilo-ohms to 1 megaohm scope, the function of the quantity in the activation series connection/parallelly connected path of the ON state that is in of Nonvolatile nanotube switch SW for example.When switch wipe through associating-to-be programmed to wipe-to-programming 1,000,000 circulation times, for identical switch, the value of the ON resistance value of RSW can from for example 10 kilo-ohms to 1 megaohm scope.Switch resistance control circuit 1755 guarantees that the ON resistance of switch SW approximates 10 kilo-ohms of values to 1 megaohm scope, for example can select 25 kilo-ohms.

Figure 17 E illustrates the controlled NV NT switch storage subsystem 1765 of resistance, it comprises NRAM array element 1760, be used for controlled NV NT switch ON resistance programming and the NV NT switch resistance control circuit 1755, controller, data I/O impact damper, sensor amplifier and Figure 17 E that wipe, read shown in other circuit (will further detail hereinafter).

Controller 1770 with input INP1 to INPN is used to provide logic function and timing control signal.PFET T10 is used in other operation (for example wipe and read) period interval from NV NT switch resistance control circuit 1755 and bit line BL.The W/L of PFET T10 is bigger than enough, and the ON resistance of PFET T10 can be ignored compared to the ON resistance of transistor T 6.

When programming operation, controller 1770 activation data I/O impact dampers 1785, it receives the input data from the I/O signal node.Controller 1770 makes PFET T10 ON, thereby is electrically connected NV NT switch resistance control circuit 1755 and bit line BL.Controller 1770 also activates the bit line driver 1750 in the NV NT switch resistance control circuit 1755, and it provides output V _DR(as above said about Figure 17 D) carried out controlled switch resistance programming operation.

Read pre-charge circuit 1775 and comprise phase inverter and the precharge PFET T16 that is constituted by PFET T12 and NFET T14, and be connected to bit line BL, voltage source V _READ(V _Read) and controller 1770.Bit line BL also is connected to sensor amplifier/breech lock 1780 through isolated transistor T18, and it is ON during read operation.It can be 1 to 5 volt voltage source V for example that sensor amplifier breech lock 1780 also is connected to data I/O impact damper 1785 _SENSE(V _Read), can be 1 to 2 volt V for example _REF, and controller 1770.

When read operation, control signal is with precharge activation signal V _PCBe applied to pre-charge circuit 1775, BL is precharged to V with equipotential line _READ, for example 1 to 2 volt.Controller 1770 also activates isolated transistor T18, sensor amplifier activation signal V is provided _SPAnd V _SN, and setting data I/O impact damper 1785 read the output signal and the logic output signal of correspondence be applied to the I/O signal node to receive from sensor amplifier/breech lock 1780.Controller 1770 stop using programmed circuit NV NT switch resistance control circuits 1755, isolate PFET T10 and wipe driver 1790.

Wipe driver 1790 and be connected to bit line BL, erase voltage source V _ERASE(V _Wipe) and controller 1770.V _ERASEUsually in 5 to 12 volts of scopes for example.

When erase operation, NRAM array element 1760 is through making T _SELTransistor is that ON is activated.Wipe driver 1790 output voltages then from the V of rising to above freezing _ERASEIf switch S E is in the ON state, then switch SW is converted to the OFF state.If switch S E is in the OFF state, then it remains in the OFF state.After switch SW is wiped free of, then wipes driver 1790 output voltages and be converted to zero volt.Be in the high impedance that driver 1790 represents pairs of bit line BL of wiping of OFF state.Controller 1770 inactive programmed circuit NV NT switch resistance control circuits 1755, pre-charge circuit 1775, sensor amplifier 1780 and isolation NFET T18.

R when Figure 18 A is illustrated in processing of 11 different N V NT switches in 80 kilo-ohms to 700 kilo-ohms the scope _ONResistance value 1800.Figure 18 B illustrates 11 Rs of different N V NT switch after 50 circulations _ONAnd R _OFFDistribution of resistance 1800 '.R after the circulation _ONBe distributed in 700 kilo-ohms to the scope of 8 megaohms.The R of all 11 different N V NT switches _ONResistance after the circulation too high and repeatedly the circulation in loseing interest in.Yet the OTP that is optimised for sequential before transport from manufacturer uses, in 11 switches have processing in 80 kilo-ohms to 200 kilo-ohms scope the time R _ON9 of resistance value is interested, because R when processing _ONResistance is for height and need low current to switch to the OFF state from the ON state.Latch circuit resistance interruption point rises to up to 400 kilo-ohms to 500 kilo-ohms, RON resistance when adapting to higher relatively processing.The resistance interruption point is adjusted at above about Fig. 7 and 8 detailed descriptions.

Use the multistage reservoir of Nonvolatile nanotube switch of Nonvolatile nanotube switch resistance control

NV NT resistance can be through single nanotube and contact terminal (such as the first terminal-to-SWNT-to-SWNT-to-s second terminal resistance; The first terminal-to-SWNT-to-MWNT-to-s second terminal resistance; The first terminal-to-MWNT-to-SWNT-to-s second terminal resistance; Series connection/the parallel connection of path (or network) resistance/impedance and other combination) combines to form.Through erase operation (it also can be described as and writes 0 operation), the NV NT switch resistance between first contact and second contact can be switched to high resistance state R _OFF(for example 100 megaohms are to 1G Europe and Geng Gao, for example 10G Europe).The voltage-contrast SEM figure of NV NT switch in denomination of invention is " Nonvolatile Nanotube Diodes andNonvolatile Nanotube Blocks and System Using Same and Methods of MakingSame "; Shown in the patent application of applying for simultaneously with this case (case number wait to specify), and to R _OFFBetween first contact and second contact, show discontinuous electrical path (network).Alternatively, through programming operation (it also can be described as and writes 1 operation), the NV NT switch resistance between first contact and second contact can be switched to low resistance state R _ON(for example 1 kilo-ohm between 1 megaohm).The voltage-contrast SEM of identical NV NT switch figure is as stated and to R _ONBetween first contact and second contact, show continuous electrical path (network).Nram memory array processing (for example wipe (writing 0), programming (writing 1), read) defines in the open No.2006/0250856 of United States Patent (USP), and its full content is incorporated into this by reference.

Through using feedback system, at the NV NT switch resistance value R of the NV NT switch SW shown in the NRAM array element 1760 by the NRAM NV NT switch storage system shown in Figure 17 E 1765 _SWCan be set to predetermined value.Figure 17 E illustrates resistance control circuit 1755, and it is a differential amplifier basically, by supplying power via the transistor T 6 and the bit line driver of T10 supply voltage and current to NRAM array element 1760.Transistor T 6, T10 and T _SELFET raceway groove ON resistance much littler than NV NT switch resistance RSW usually, so nearly all bit line driver 1750 voltage V _DRAll be presented at NV NT switch SW two ends.The pulse V that controller 1770 causes amplitudes that bit line driver 1750 will rise or a plurality of to increase _DRBe supplied to bit line BL, it is then via selecting transistor T _SELAnd be provided to NV NT switch SW.Suppose NV NT switch SW in the NRAM array element 1760 be in wiped or R _OFFState, the pulse V that the rising that is then applied or a plurality of amplitude increase _DRThe electric resistance changing that causes NV NT switch SW is to ON state R _ONV _DRContinuing increases up to R _SW≈ R2, in this point, resistance control circuit 1755 (differential amplifier) "off" transistor T6 and programming operation (writing 1) are to the R of expectation _ONValue is accomplished.Therefore, NV NT switch SW R _ON(corresponding to R _SW) value approximates R2.R2 can change on a large scale, thereby causes covering the large-scale R that is in kilo-ohm scope _ONThe R of resistance value _ON(R _SW) value.R _ONAnd R _OFFBe non-volatile resistance states, it is remained unchanged under the situation that does not apply voltage.The description of differential amplifier (differential amplifier that for example is used for resistance control circuit 1755) sees also people's such as Baker, " CMOS Circuit Design, Layout, and Simulation ", IEEE Press, pp.579-591 (1998).

R in resistance control circuit 1755 is used to programme the NV NT switch SW of NRAM array element 1760 _ONDuring resistance value (example of the switch storage of NV NT shown in Figure 17 E subsystem 1765), controller 1770 and sensor amplifier/breech lock 1780 can be used to realize R _ONResistance value control, and need not resistance control circuit 1755.Ground as mentioned below, corresponding to open described nram memory array of No.2006/0250856 of United States Patent (USP) and corresponding NV NT switch storage subsystem 1765 (but not having resistance control circuit 1755) to process the 8Kb nram memory to be tested and show that resistance changes (from surpassing the high resistance R of 100 megaohms _OFFState (most of NV NT switch resistance value surpasses 1G Europe) is to a plurality of low non-volatile R _ONResistance states (being programmed into about 50 kilo-ohms of resistance ranges)) to 1 megaohm.Through voltage modulated a plurality of non-volatile R that programme _ONResistance states is by applying a plurality of increase bit-line voltage programming pulses and realization is read in the included unit by NV NT switch resistance state after each potential pulse.Nram memory array described in the open No.2006/0250856 of United States Patent (USP) comprises nonvolatile storage unit C00 to Cnm matrix.The nram memory array also comprises to be wiped (writing 0), programming (writing 1) and reads word line (WL0, WL1, to WLn); Wipe (writing 0), programming (writing 1) and read word line (WWL0, WWL1, to WWLn); And and wipe (writing 0), programming (writing 1) and reading bit line (BL0, BL1, to BLm).Word-line signal generator (not shown) provides word-line signal to storage unit.Auxiliary word lines signal generator (not shown) provides the auxiliary word lines signal to storage unit.In some applications, auxiliary word lines all is connected to reference voltage (for example ground connection).Bit line generator (not shown) provides bit line signal to storage unit.Made 8Kb nram memory comprises that but the voltage of selected option is read (being similar to sensor amplifier/breech lock 1780) or electric current is read.Electric current is read and can be comprised any known current read circuit; The current-differencing sensor amplifier of Figure 27 and corresponding for example people's such as Baker " CMOS Circuit Design, Layout, and Simulation "; IEEEPress, the description among the pp.607-608 (1998).

Through non-volatile R _ONThe programming of the current-modulation of resistance states also uses made 8KbNRAM memory array (as stated) to measure, and it is through applying a plurality of increase bit-line voltage programming pulses and realization is read in the included unit by NV NT switch resistance state after each potential pulse.Non-volatile R _ONThe current-modulation of resistance is specified as follows.

NV NT switch can programmed on the resistance states on a large scale, as is discussed in further detail below.Multistage reservoir (in the context as the NV NT switch of magazine member) relates to a plurality of resistance states on each NV NT switch, and corresponding to the storage of a plurality of logic states on the same NV NT switch.Therefore for example, two resistance states (R for example _OFFAnd R _ON) corresponding to a logic state of each NV NT switch or the storage of an information bit.Yet, R _OFFWith three R _ONResistance states (value) is corresponding to two logic states or two information bits of each NV NT switch.Because multistage storage or state relate to a plurality of NV NT switch resistance states, other term (for example polymorphic reservoir, many resistance states, and other variant) can use hereinafter.

Use the program voltage of Nonvolatile nanotube switch resistance to modulate a plurality of NRAM cell resistance states of programming

Memory tester is used to control made 8Kb nram memory (as stated).Memory tester provides address, data, sequential and other function to the 8Kb nram memory operation of processing.Sequential is in wafer layer and some sequential are in module layer.In alternate embodiment, can use other testing mechanism.In this example, the 1Kb NRAM subclass of 8Kb nram memory is to be tested, and its auxiliary word lines ground connection and nram memory array element use word line and bit line access.Wiping (writing 0) operation is performed and surpasses the OFF resistance (R that 1000 positions are switched at least 100 megaohms _OFF) state.Then, for the word line that activates, the bit-line voltage pulse is via selecting the FET device to be provided to corresponding NV NT switch.The bit line program potential pulse that is applied starts from 2.4 volts and increase to 7 volts with the stride of 200mV (0.2V).After each pulse, carry out tester and read, what are arranged with the electric current of at least 1 μ A switch on (about 1V applies read-out voltage, and use has the electric current sensor amplifier/breech lock of the current detecting level of about 1 μ A) to define 1000+ position.In addition, the actual cell current measurement value is by the memory tester record.The NV NT switch of switching on the electric current of at least 1 μ A is in a plurality of non-volatile R _ONResistance states.Figure 19 provides the result's of this test sample various diagrams.

Figure 19 A illustrates the quantity and the program voltage V that is applied to bit line of the position that switches on the electric current of at least 1 μ A with the read-out voltage of 1V _PPThe diagrammatic sketch 1900 of function.When applying the potential pulse V that more amplitudes increase _PPThe time, more switches are arranged from OFF high resistance state (R _OFF＞100 megaohms) be converted to many R _ONResistance states.Figure 19 B illustrates the diagrammatic sketch 1910 of function of quantity and the measured cell current of position (unit).Because NV NT switch resistance is more much bigger than selecting the FET channel resistance, so 1 volt of nearly all read-out voltage all is presented at NV NT switch ends.NV NT switch resistance can be through calculating 1 volt of read-out voltage, because the NFET resistance in series is much littler than the NVNT switch resistance divided by the corresponding cells read current.Figure 19 C illustrate the quantity of position with greater than many R of 1000 switches _ONThe diagrammatic sketch 1920 of the function of resistance states.R _ONThe scope of resistance states value be from 50 kilo-ohms to 1 megaohm, and the scope of corresponding cells electric current is to about 20 μ A from approximately zero (in this example, 2 positions are not switched and can not be operated, and replace adjusting through redundant digit usually).R _OFFResistance states surpasses 100 megaohms, and its current ratio 10nA is much little.

The many resistance states of NV NT switch are grounded into three R _ONScope and a R _OFFScope is shown in diagrammatic sketch 1920.About 10% position (switch) has the R less than 150 kilo-ohms _ONWith for the read-out voltage of 1V corresponding unit read current greater than 7 μ A; About 30% position (switch) has at 150 kilo-ohms of R to 250 kilo-ohms of scopes _ONWith for the read-out voltage of 1V corresponding unit read current at 6 μ A to 4 μ A; About 60% position (switch) has at 250 kilo-ohms of R to 1 megaohm scope _ONIn this example, we select to programme all 1000+.The position of not programmed has the R greater than 100 megaohm scopes _OFFWith for the read-out voltage of 1V usually less than the corresponding unit read current of 10nA.In other example, can use different resistance ranges.

The test result of 1000+ seat collection of the 8Kb nram memory shown in the diagrammatic sketch 1920 shows four read current scopes that the resistance states scope is corresponding with four.The people's such as Baker of electric current sensor amplifier shown in the current-differencing sensor amplifier of Figure 27 and correspondence " CMOS CircuitDesign; Layout; and Simulation "; IEEE Press, the description among the PP.607-608 (1998) can detect a plurality of range of current through using multiple current sensor amplifier reference value.In this example, four resistance ranges can be to having three R _ONResistance states and a R _OFFThe same NV NT switch of resistance states limits.These four resistance states can convert corresponding logic state 00,01,10,11 to by electric current sensor amplifier/breech lock.If each position is made up of 1 and 0 value, but each NV NT switch store two bits then.The quantity of resistance states is not limited to four and in fact can be much bigger, thereby on each NV NT switch, can store four logic states or two more than the position.

It should be noted, as a plurality of R _ONResistance states through apply a plurality of programmings (writing 1) pulse to nram memory array element with resistance from R _OFFState is reduced to the R of expectation _ONValue (as stated) and when reaching, test also being performed (result is not shown) is to show that a plurality of wiping (writing 0) potential pulse that amplitude increases is with R _ONResistance increases to the R that uprises gradually _ONValue and increase to high resistance state R _OFFTherefore, the multivoltage pulse can be used to use programming and erase operation to reach the NV NT switch resistance value of expectation.

Use the program current of Nonvolatile nanotube switch resistance to modulate a plurality of NRAM cell resistance states of programming

Above-mentioned made 8Kb nram memory (in present example) is designed to potential pulse is applied to the nram memory array bitline.In order to assess current impulse a plurality of R that programme _ONThe use of resistance states, above-mentioned method of testing is modified.In memory tester operating period, the 8Kb nram memory array element of selected piece is erased to high resistance R _OFFState.Then, selected auxiliary word lines is pulsed to 6.7 volts program voltage, and bit line is grounded, and in each unit, selected word line is used to modulation and selects transistorized grid voltage, thereby control is flowed through to the electric current of inductive switch.Behind each 3.7 volts of programming pulse, selected auxiliary word lines is grounded, and 1 volt read-out voltage is applied to selected bit line, and selected word line is activated, and cell current reads measurement and carry out through memory tester, as stated.

In this example, 6.7 volts of the auxiliary word lines voltages that is applied are more much bigger with the word line voltage that forms corresponding FET conducting channel than being applied to selection FET transistor gate, so this FET is in the zone of saturation of its operation.FET saturation current ISAT also flow through the series connection FET NV NT switch.The scope that table 1930 among Figure 19 D illustrates the word line voltage (VWL0) that applies is from 0.9 volt to 1.4 volts, and the corresponding saturation current I through calculating is shown _SATI _SATDirectly measured, but according to the electric current I of during the unit read operation of carrying out after each program cycles, measuring that reads _READCalculate.Intermediate value) unit read current I _READMeasure and be recorded in Figure 19 D with 1 volt bit-line voltage.Intermediate value I _READCurrent value is corresponding to surpassing 15,000 current values.

Programming (writing 1) operating period, the FET channel resistance is much littler than NV NT switch resistance value.Therefore, nearly all 6.7 volts of being applied to selected auxiliary word lines all are presented at the NV NT switch ends of correspondence.By the saturation current I that selects the FET transistor to be controlled _SATThe corresponding NV NT switch of flowing through causes through switch I _SATX R _SW(I _SATX R _ON) voltage drop.Because the voltage of NV NT switch ends is about 6.7 volts, resistance value R then through programming _ON≈ 6.7/I _SATI _SATBe not directly to measure.Yet, because R _ONBe non-volatile resistance value, and 1 volt read-out voltage is too low and can't upset non-volatile resistance states, so R between reading duration _ONValue and programming (writing 1) operation after identical.Therefore, I _READX R _ON=1 volt and I _SAT≈ I _READX 6.7/1.Therefore, the I shown in Figure 19 D _SATValue is the saturated current value of intermediate value, and it is through intermediate value I _READCurrent value multiply by 6.7 times of calculating.Intermediate value R _ONResistance value is corresponding to intermediate value I _SATValue and can pass through I _SATDivided by 6.7 volts of calculating.

Figure 19 E illustrates intermediate value saturation current I _SATWith intermediate value switch resistance R _ONThe diagrammatic sketch 1940 of relation.Diagrammatic sketch 1940 shows the current programmed pulse I that uses a plurality of current impulses with increase current amplitude (from about 3.5 μ A to 8 μ A) to be applied to NV NT switch _SAT, cause intermediate value R _ONThe scope of resistance is from about 1.9 megaohms to 830 kilo-ohm.Therefore, many resistance states R _ONProgramming can use current programmed and above-mentioned voltage-programming to reach.

Through testing made 8kb nram memory piece (a large amount of behavior is shown), Figure 19 illustrates and is in non-volatile resistance states R _OFFWith non-volatile a plurality of ON resistance states R _ONA large amount of NV NT switches.Above-mentioned wipe, programme and read method is used.These test results show: can be wiped free of or programme at the single NV NT switch of being selected by a succession of FET transistor and be used as in the NRAM storage unit of nonvolatile storage node, to store a plurality of non-volatile resistance states.These a plurality of non-volatile resistance states can be used to a plurality of logic states are stored in each NV NT switch of each NRAM storage unit.Programmed method comprises the potential pulse of amplitude increase and the current impulse that amplitude increases, and it reduces R _ONValue.A plurality of erasing voltage pulses can be used to increase R _ONValue is from being low to moderate higher R _ONThe value or to high resistance state R _OFFIn application-specific, also can use other programmed method.

Be used for forming the realization of Nonvolatile nanotube flash memory (NFlash) storer of the non-volatile impedance network that comprises polymorphic storage and Reprogrammable

Nram memory stored logic state is (according to R _OFFWith a R _ONState), or many level storage (comprise R _OFFWith a plurality of R _ONValue) as above said about the nram memory array element of selection FET with series connection and NV NT switch.Yet, also possibly form and can also store R _OFFWith a R _ONSelection FET and NV NT switch or comprise R _OFFWith a plurality of R _ONMany level (many resistance) of value store the parallel connection combination of (using said about nram memory as above).Parallel connection FET and NV NT switch combination cause the diversity of new memory, logic and simulation application; Because system of selection is different; And, occupy less area thereby compare with tandem compound because parallelly connected FET/NV NT switch can be with placing the NV NT switch of FET on transistorized to form.NV NT electrical specification and polarity of voltage and direction of current are irrelevant.

Figure 20 illustrates the series circuit 2000 that comprises the FET transistor 2010 and the tandem compound of the NV NT switch 2030 that is connected at common node 2040, and above about nram memory array element illustration.FET 2010 has grid G (the channel region conduction of its control FET), drain electrode 2050 (being connected to terminal T1) and FET 2010 source electrodes (being connected in common node 2040 with a terminal of NV NT switch 2030).The 2nd NV NT switch 2030 terminals 2060 are connected to terminal T2.FET 2010 is a symmetrical device, so drain electrode and the interchangeable use of source electrode.The ON channel resistance of FET 2010 is than a plurality of resistance values of NV NT switch 2030 any much lower (for example hanging down 10 times) at least.

Figure 21 illustrates the parallel circuit 2100 of the parallel connection combination that comprises FET 2120 and NV NT switch 2130.FET 2120 has grid G ', its control FET channel region conduction.FET 2120 drain electrodes are connected to one of NV NT switch 2130 terminals (it also is connected to terminal T1) at common node 2140, and FET 2120 source electrodes are connected to another terminal (it also is connected to terminal T2) of NV NT switch 2130 at common node 2145.Various manufacturing approaches can be used to NV NT switch 2130 is placed on the FET 2120, to obtain preferable closeness.The ON channel resistance of FET 2120 is much littler than any of a plurality of resistance values of NVNT switch 2130.But the highest resistance Be Controlled of NV NT switch 2130, thus can not be higher than the OFF resistance value of FET 2120 in fact, to guarantee for parallel circuit 2100, between ON and OFF conduction state enough Current Control being arranged.For example, NV NT switch 2130 can be programmed to 1 megaohm resistance range at about 50 kilo-ohms, shown in diagrammatic sketch 1920 among Figure 19 C.

Figure 22 illustrates the series connection/parallel circuit 2200 of the series connection/parallel connection combination that comprises FET 2210, FET 2220 and NV NT switch 2230.FET 2220 has grid G ', its control FET channel region conduction.FET 2220 drain electrodes are connected to one of NV NT switch 2230 terminals (it also is connected to FET 2210 source electrodes) at common node 2240.FET 2210 channel regions conductions is controlled by grid, and drains and 2250 be connected to terminal T1.FET 2220 source electrodes are connected to another terminal (it also is connected to terminal T2) of NVNT switch 2230 at common node 2245.Various manufacturing approaches can be used to NV NT switch 2230 is placed on the FET 2220, to obtain preferable closeness.The ON channel resistance of FET 2220 than any of a plurality of resistance values of NV NT switch 2230 little many (for example at least less than 10 times), as above said about parallel circuit 2100.Series connection FET 2210ON channel resistance is also less than any (for example at least less than 10 times) of a plurality of resistance values of NV NT switch 2230, as above said about series circuit 2000.

A plurality of combinations of parallel circuit 2100 shown in Figure 21 can be used to memory application, to form the intensive non-volatile flash memory based on nanotube (this is called the NFlash storer in using, and will further specify following).A plurality of series connection of parallel circuit 2100 and series connection/parallel circuit 2200 and series connection/parallelly connected combination can be used to form the impedance network of Nonvolatile programmable, and for example resistance and capacitance simulation network will further specify following.

Comprise Nonvolatile nanotube flash memory (NFlash) storer that many level (many resistance) state stores)

Flash memory nand memory array with the non-volatile FET of series connection is used to promote density of memory arrays, like K.Itoh, " VLSI Memory Chip Design ", Springer, 2001, described in the pp.41-44 and shown in the accompanying drawing 1.35 and 1.36.The flash memory nand memory is the electric charge on floating boom (FG) the FET transistor of series connection with information storage, thereby controls the threshold voltage of each series connection FG FET device, and is of the Itoh list of references.These systems of selection of connecting FGFET that are used for the memory array of NAND configuration are different from the flash memory system of selection of the described random access NOR configuration of Itoh list of references 38-41 page or leaf.(NOR-flash) system of selection of NOR-flash memory and aforesaid nram memory similar.When reading the state of the FG FET device of for example connecting with other FG FET, the FG FET of all series connection selects (conducting is ON) with high word line voltage, except that FG FET device to be read.FG FET device to be read has the zero word line voltage that is applied to grid.If selected FG FET device has been programmed to be in the ON state, then electric current will flow into series circuit, thereby make bit line discharges.If selected FG FET device has been programmed to be in the OFF state, then do not have electric current can flow into series circuit, and bit line will remain on high-voltage level.

Parallel circuit 2100 can replace the FG FET transistor shown in the accompanying drawing 1.35 and 1.36 in the Itoh list of references, forming the Nonvolatile nanotube flash memory, should with in be called the NFlash storer.The operation of NFlash storer is that ON implements through the NFlash memory array cell of series connection FET type in the conducting parallel circuit 2100 also, except the FET with NV NT switch in parallel that waits to programme, wipe or read is in the OFF state.Then, can use to be similar to and wipe, programme or read operation about aforementioned nram memory is described.

Figure 23 A illustrates NFlash storer sketch 2300, and it has nanotube types NAND subarray 2310 and 2320.The incompatible formation of series that each subarray uses that parallel circuit shown in Figure 21 2100 forms based on the unit of NV NT switch.Each subarray 2310 and 2320 shows four series connection non-volatile cells based on NV NT switch.Subarray 2310 comprises NV NT switch SW 1 and parallelly connected FET TR1, NV NT switch SW 2 and FET TR2, NV NT switch SW 3 and FET TR3, NV NT switch SW 4 and FET TR4.First selects FET TRS1 that common node 2330 is connected to bit line BL1, and the second selection FET TRS2 is connected to reference line REF with common node 2340.Subarray 2320 comprises NV NT switch SW 5 and parallelly connected FET TR5, NV NT switch SW 6 and FET TR6, NV NT switch SW 7 and FET TR7, NV NT switch SW 8 and FET TR8.First selects FET TRS1X that common node 2350 is connected to bit line BL2, and the second selection FET TRS2X is connected to reference line REF with common node 2360.Selection wire SL1 is connected to the grid of FETsTRS1 and TRS1X; Selection wire SL2 is connected to the grid of FET TRS2 and TRS2X; Word line WL1 is connected to the grid of FET TR1 and TR5, and word line WL2 is connected to the grid of FET TR21 and TR6, and word line WL3 is connected to the grid of FET TR3 and TR7; Word line WL4 is connected to the grid of FET TR4 and TR8, thereby forms schematic NFlash storer 2300.When schematic NFlash storer 2300 illustrations 8 bit flash memories, a plurality of resistance values can be stored in each NV NT switch so that the quantity of position doubles, three times become 16,32 etc.Equally, use the hundreds of individual even thousands of unit of parallel circuit 2100 can form the logic state that each unit can store a plurality of resistance values and correspondence based on NV NT switch.

It should be noted, when schematic NFlash storer 2300 shows two selection FET in each

NAND subarray

2310 and 2320, select FET just enough for one the NFlash storage operation.Figure 23 B illustrates schematic NFlash storer 2350, and it is with schematically NFlash storer 2300 is identical, except NAND subarray 2360 only uses one to select FET TRS1 and NAND subarray 2370 only to use one to select FET TRS1X.The NFlash storer can use schematic nram memory 2300 2350 or its variant form.

In when operation, can be selected being used to based on any unit of NV NT switch and to read, to wipe or programming operation.The schematic example of NFlash storer 2300 as a reference, if read the state of representative switch SW 3, then the series connection of all between bit line BL1 and reference line REF FET device is switched on and is ON, except FET TR3 still remains on OFF (not being chosen) state.Bit line BL1 is precharged to for example 1 volt voltage.If SW3 is in the ON state, then BL1 is discharged.Yet if SW3 is in the OFF state, BL1 is not discharged.SW3 can be in various ON resistance states, so a plurality of resistance states can be read.Read operation is similar to above about the described read operation of many level nram memory (it is stored in each NV NT switch with a plurality of resistance states).

When operation; The schematic example of NFlash storer 2300 as a reference; The state of representative switch SW 3 if programme, then all between bit line BL1 and reference line REF series connection FET device is switched on and is ON, except FET TR3 maintenance place OFF (not being chosen) state still.Bit line BL1 imposes pulse with for example from 2.4 to 7 volts increase voltage level.If SW3 is in the OFF state and BL1 is imposed pulse, then NV NT open relation is programmed to one of several ON resistance R ON state, so a plurality of resistance states can read in NV NT switch SW 3.Programming operation is similar to above about the described programming operation of many level nram memory (it is stored in each NV NT switch with a plurality of resistance states).

When operation; The schematic example of NFlash storer 2300 as a reference; If wipe the state of representative switch SW 3, then the series connection of all between bit line BL1 and reference line REF FET device is switched on and is ON, except FET TR3 still keeps being in OFF (not being chosen) state.Bit line BL1 such as abovely impose pulse to increase voltage level about the nram memory array is said.If SW3 is in the ON state and BL1 is imposed pulse, then NV NT switch is erased to higher ON resistance R _ONState value or to OFF state R _OFFErase operation is similar to above about the described erase operation of many level nram memory (it is stored in each NV NT switch with a plurality of resistance states).

Figure 24 illustrates the planimetric map 2400 corresponding to schematic NFlash storer 2300; The planimetric map of its NAND subarray 2410 schematically shows corresponding to NAND subarray 2310, and the planimetric map of NAND subarray 2420 schematically showing corresponding to NAND subarray 2320.Figure 24 comprises patterned nanostructured 12440, patterned nanostructured 22441, sidewall spacer 2442, polysilicon or metal WL and area of grid 2444, contact 2446, polysilicon or metallic region 2448 and contact 2450.Figure 25 illustrates the sectional view 2500 of NAND subarray 2410.The patterned nanostructured 12540 of column bolt throughhole (stud via) 2510 is connected to corresponding FET diffusion and limits NV NT switch length (width is limited etching operation) with the zone of patterned nanostructured 22541 with each nanostructured.In a particular embodiment, NAND subarray 2410 is deposited on the p substrate 2520.Can use various manufacturing approaches NV NT switch is formed on the corresponding FET.

As an example, the SW3 and the TR3 of parallel connection form representational unit based on NV NT switch, and it is corresponding to parallel circuit shown in Figure 21 2100.One coupled columns bolt throughhole 2510 (unit based on the NV switch that is close to is shared) limits NV NT switch length size and is used for the contact area of Dai Xingbiao switch SW 3, and is formed up to the electrical connection of the corresponding N+ diffusion of following FET TR3.

The NFlash storer is wiped free of, programmes and read in the operation corresponding to nram memory.In case constituting all serial transistors in bit line to NV NT switch and NV NT switch to reference line path is formed; And the FET of the selected NV NT switch of parallel connection is by by being OFF, then wipe, programme and read operation corresponding to the operation of the NV NT switch among the NRAM as stated of being used for programming.

The Nonvolatile nanotube programmable resistance network that comprises resistor and capacitor

Allow electronically controlled (tuning) analog network of resistor and capacitor to form at the many resistance states series connection/parallel circuits 2200 of many resistance states of programmable nonvolatile parallel circuit shown in Figure 21 and Figure 22 2100 and programmable nonvolatile respectively.In operation, the state class of for the NFlash storage operation, wiping, programme and read the single NV NT switch that is used for forming these electronically controlled (tuning) impedance networks is similar to about Figure 23,24,25 described.

Figure 26 A illustrates electronically controlled resistance in series network 2600, and wherein nanotube resistors in series network 2620 uses to be similar to and abovely is programmed (or wiping) about NAND subarray shown in Figure 23 A 2310 and the 2320 described operations of NAND subarray.The resistance value of NV NT switch SW 1, SW2, SW3, SW4 use above about the described programming of Figure 23, wipe and the method for read operation is set and use resistor to set and operator scheme controller 2610 is controlled.During NV NT switch resistance setting operation (for example programme and wipe), the FETTRS1A that terminal RT1 and common node are 2630 is by by being OFF, so that can't interference can be connected to the circuit of terminal RT1.Equally, FET TRS2A that terminal RT2 and common node are 2640 is by by being OFF, so that can't interference can be connected to the circuit of terminal RT2.Then, FET TRS1B and TRS2B are switched on and are ON.FET TRS1B and TRS2B correspond respectively to FET TRS1 and the TRS2 of Figure 23 A.Resistor is set and operator scheme controller 2610 then applies potential pulse and reference line voltage REF corresponding to bit line BL1 pulse, as above about the described operation of Figure 23 A.Single NV NT switch (for example representation switch S3) is selected, as above about the described operation of Figure 23 A.After each the resistance states of NV NT switch SW 1, SW2, SW3, SW4 was set, then resistor was set with operator scheme controller 2610 FET TRS1B, TRS2B, TR1, TR2, TR3, TR4 by the FETTRS1A and the TRS1B that respectively terminal RT1 and RT2 are electrically connected to common 2630 and 2640 for OFF and activation (conducting).

Electronically controlled resistance in series network 2600 can be used to set nanotube resistors in series equivalent electrical circuit 2620, with in factory or during manufacture or afterwards or transporting on-the-spot ground, back optimized circuit function, or during electronic component tenure of use, adjusts.Equally, can change or modify feature in any time during the tenure of use of resistive element.

Figure 26 B illustrates resistors in series equivalent electrical circuit 2650, comprises nanotube resistors in series equivalent electrical circuit 2620 ' and the terminal 2630 ' and 2640 ' that corresponds respectively to

public terminal

2630 and 2640 corresponding to nanotube resistors in series equivalent electrical circuit 2620.When operation, in this example, the voltage at single resistor two ends should be no more than 2.5 volts to prevent program disturbance (program-disturb).

Figure 27 illustrates the chip power voltage regulator 2700 based on the electronic tuning of nanotube, and it uses electronically controlled resistance in series network 2705 (to produce reference voltage VREF) and chip power voltage regulator 2750 (with the V on setting and the Control Node 2790 _{ON-CHIP VOLTAGE}(V _{Chip power is pressed}) equal V _REF) form.V _{ON-CHIP VOLTAG}E is used as chip power supply and is assigned to a plurality of on-chip circuitry.Output voltage V _REFThrough using the ratio (V of NV NT switch resistance value _REF=[(V _SW1+ V _SW2)/(V _SW1+ V _SW2+ V _SW3+ V _SW4)]) V _PSReduce supply voltage V _PPAnd produce and can adjust in the voltage on a large scale.The class of operation of the chip power voltage regulator 2700 of electronic tuning and the electronically controlled resistance in series network 2600 shown in Figure 26 A seemingly, its nanotube resistors in series network 2720 corresponding to nanotube resistors in series network 2620 and common 2730 corresponding to common 2630.Yet FET TRS1A and TRS1B are removed; Common node 2730 is connected directly to ground connection.Equally, NFET TRS2A is replaced by PFET TRSX, to prevent in selecting transistor, threshold voltage drop taking place.

Chip power voltage regulator 2750 is similar to employed chip power voltage regulator in the semicon industry.Differential amplifier 2760 operates in people such as above Baker. list of references in describe.Output voltage and electric current on the PFET2780 Control Node 2790, and feedback inverter 2770 greatly provides to use for differential amplifier 2760 control output voltage 2790 and approximates V _REFMeans (as in the industry institute well-known).

Figure 27 illustrates a reference voltage V who is produced by nanotube resistors in series network 2620 _REFYet, also can produce two additional reference voltages through the shared node between tap (tapping) FET TR1 and TR2.In these two additional reference voltages each can be coupled to other chip power voltage regulator (not shown) (being similar to voltage regulator 2750), to produce three different V altogether _ON-CHIP _VOLTAGEValue.

Electronically controlled resistance in series network 2600 and be applied to an example in many analog networks that chip power voltage regulator 2700 based on the electronic tuning of nanotube (respectively about Figure 26 and 27 said) is based on a plurality of NV NT switches that have a plurality of resistance states separately.Can conceive other example based on the network of a plurality of NV NT switches that have a plurality of resistance states separately.Figure 28 A illustrates by the parallel circuit 2100 that shows at Figure 21 and 22 respectively and the formed electronically controlled series connection of the combination/parallel resistance network 2800 of series connection/parallel circuit 2200.Shown in Figure 28 A, series connection and parallelly connected FET need in series connection/parallel network, to isolate single NV NT switch effectively.Resistor is set with operator scheme controller 2810 and is set with the mode of operator scheme controller 2610 and operate to be similar to resistor, except the additional output FET conducting of during programming and erase operation, will connecting is ON and to end be OFF.FET TRS1B and TRS2B supply potential pulse are to wipe, to programme and read operation, as above described about Figure 26 A.In this example, common node 2830 is coupled directly to terminal RT1 ' and common node 2840 is coupled directly to terminal RT2 '.Yet,, can use the FET that decouples that connects, shown in Figure 26 A if other circuit can be influenced during for example programming.

Single NV NT switch in the nanotube series connection/resistors in parallel network 2820 uses to be similar to and abovely is wiped free of, programmes and read about the described method of operating of Figure 26 A.As an example, NV NT switch SW 3 can through with FETTR1, TR3 ' conducting be ON and with FET TR2 ', TR3, TR4 ' by putting on one that is selected and is tuned between

common node

2830 and 2840 in several resistance states for OFF and with potential pulse.As another example, NV NT switch SW 2 can through with FET TR1, TR2 ' conducting be ON and with FET TR2, TR3 ' by putting on one that is selected and is tuned between

common node

2830 and 2840 in several resistance states for OFF and with potential pulse.Employed potential pulse is similar to Figure 26 A, 23A, described in 18.

After the programming of accomplishing single switch or wiping, then when operation, all series connection FET all are switched on and are ON, and all parallelly connected FET are all by by being OFF.

Figure 28 B illustrate comprise corresponding to the nanotube series connection/resistors in parallel equivalent electrical circuit of nanotube series connection/resistors in parallel network 2,820 2820 ' with correspond respectively to the terminal 2830 ' of

public terminal

2830 and 2840 and 2840 ' series connection/resistors in parallel equivalent electrical circuit 2850.When operation, in this example, the voltage at single resistor two ends should be no more than 2.5 volts to prevent program disturbance.

Electronically controlled series connection/parallel resistance network 2800 shown in Figure 28 A can be changed into the electronically controlled resistance device network 2900 shown in Figure 29 A.Shown in Figure 29 A, used by series connection at parallel circuit 2100 shown in Figure 21 and 22 and series connection/parallel circuit 2200 respectively, and capacitor is used by parallel connection.Resistor is set and operator scheme controller 2910 is operated with the mode that is similar to resistor setting and operator scheme controller 2810.FET TRS 1B and TRS2B supply potential pulse are to wipe, to programme and read operation, as above described about Figure 28 A.In this example, common node 2930 is coupled directly to terminal RCT1 and common node 2940 is coupled directly to terminal RCT2.Yet,, can use the FET that decouples that connects, shown in Figure 26 A if other circuit can be influenced during for example programming.

Single NV NT switch in the nanotube series connection/resistors in parallel network 2920 uses to be similar to and abovely is wiped free of, programmes and read about Figure 26 A and the described method of operating of Figure 28 A.As an example, NV NT switch SW 2 can through with FET TR1, TR2 ' conducting be ON and with FET TR2 by putting on one that is selected and is tuned between

common node

2830 and 2840 in several resistance states for OFF and with potential pulse.Employed potential pulse is similar to Figure 28 A, 26A, 23A, described in 18.

Figure 29 B illustrate comprise corresponding to the nanotube series connection/resistors in parallel equivalent electrical circuit of nanotube series connection/resistors in parallel network 2,920 2920 ' with correspond respectively to the terminal 2930 ' of

public terminal

2930 and 2940 and series connection/resistors in parallel of 2940 '/capacitor equivalent electrical circuit 2950.When operation, in this example, the voltage at single resistor two ends should be no more than 2.5 volts to prevent program disturbance.

Adjustment resistance value R _SW1And R _SW2Cause tuning RC time constant in large-scale value.Equally, if R _SW1And R _SW2Be programmed to relatively low resistance value, then for having the rise and fall times greater than for the waveform of RC time constant, capacitor C1, C2, C3 can be revealed as a capacitor C=C1+C2+C3.Other variant also is possible.

The references of being included in

Following publicly owned patent documentation (being called " references of being included in " here) is described in order to the various technology of making nanotube element (nano tube structure goods and switch) (for example making and the patterning nano tube structure), and all is hereby expressly incorporated by reference:

Electromechanical Memory Array Using Nanotube Ribbons and Methodfor Making Same (U.S. Patent application No.09/915,093, present United States Patent(USP) No. 6,919,592), the applying date is July 25 calendar year 2001;

Electromechanical Memory Having Cell Selection Circuitry ConstructedWith Nanotube Technology (U.S. Patent application No.09/915; 173, present United States Patent(USP) No. 6,643; 165), the applying date is July 25 calendar year 2001;

Hybrid Circuit Having Nanotube Electromechanical Memory (U.S. Patent application No.09/915,095, present United States Patent(USP) No. 6,574,130), the applying date is July 25 calendar year 2001;

Electromechanical Three-Trace Junction Devices (U.S. Patent application No.10/033,323, present United States Patent(USP) No. 6,911,682), the applying date is Dec 28 calendar year 2001;

Methods of Making Electromechanical Three-Trace Junction Devices (U.S. Patent application No.10/033,032, present United States Patent(USP) No. 6,784,028), the applying date is Dec 28 calendar year 2001;

Nanotube Films and Articles (U.S. Patent application No.10/128,118, present United States Patent(USP) No. 6,706,402), the applying date is on April 23rd, 2002;

Methods of Nanotube Films and Articles (U.S. Patent application No.10/128,117, present United States Patent(USP) No. 6,835,591), the applying date is on April 23rd, 2002;

Methods of Making Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements and Articles (U.S. Patent application No.10/341,005), the applying date is on January 13rd, 2003;

Methods of Using Thin Metal Layers to Make Carbon Nanotube Films, Layers, Fabrics; Ribbons; Elements and Articles (U.S. Patent application No.10/341,055), the applying date is on January 13rd, 2003;

Methods of Using Pre-formed Nanotubes to Make Carbon Nanotube Films, Layers, Fabrics; Ribbons; Elements and Articles (U.S. Patent application No.10/341,054), the applying date is on January 13rd, 2003;

Carbon Nanotube Films, Layers, Fabrics, Ribbons, Elements and Articles (U.S. Patent application No.10/341,130), the applying date is on January 13rd, 2003;

Non-volatile Electromechanical Field Effect Devices and Circuits usingSame and Methods ofForming Same (U.S. Patent application No.10/864; 186; The open No.2005/0062035 of United States Patent (USP)), the applying date is on June 9th, 2004;

Devices Having Horizontally-Disposed Nanofabric Articles and Methodsof Making the Same (U.S. Patent application No.10/776,059), the applying date is on February 11st, 2004;

Devices Having Vertically-Disposed Nanofabric Articles and Methods ofMaking the Same (U.S. Patent application No.10/776; 572, present United States Patent(USP) No. 6,924; 538), the applying date is on February 11st, 2004; With

Patterned Nanoscopic Articles and Methods of Making the Same (U.S. Patent application No.10/936,119, the open No.2005/0128788 of United States Patent (USP)).

The present invention can embody with other particular form under the situation that does not depart from its spirit or intrinsic propesties.Present embodiment thereby be regarded as exemplary and nonrestrictive relation.

Claims

1. non-volatile latch circuit comprises:

At least one input end can the input logic state;

Output terminal can the output logic state;

Nanotube switching element; Comprise and be arranged at two nano tube structure goods between the conductive contact; Said nano tube structure goods are electrically connected said two conductive contacts; Wherein said nanotube switching element can be at relatively low resistance states and is switched between the higher-resistivity state relatively, and wherein said nanotube switching element can remain on said relatively low or said relative higher-resistivity state non-volatilely;

The volatibility latch circuit; Comprise at least one semiconductor element that electrically is arranged between said input end and the said nanotube switching element; Said semiconductor element can receive and volatibility ground stored logic state, and said logic state inputs to said input end;

Wherein when said nanotube switching element is in said relatively low resistance states; Said volatibility latch circuit keeps first logic state and exports said first logic state at said output terminal; And wherein when said nanotube switching element is in said relative higher-resistivity state; Said volatibility latch circuit keeps second logic state, and said second logic state is exported at said output terminal.

2. non-volatile latch circuit as claimed in claim 1 is characterized in that, said electronics latch circuit comprises inverter circuit, and said inverter circuit comprises a plurality of field effect transistors.

3. non-volatile latch circuit as claimed in claim 1 is characterized in that, said nanotube switching element can switch between said relatively low resistance states and said relative higher-resistivity state for several times.

4. non-volatile latch circuit as claimed in claim 1; It is characterized in that; Said electronics latch circuit is converted to relative higher voltage level with the said relatively low resistance states of said nanotube switching element; It is corresponding to said first logic state in said output terminal output; And wherein said electronics latch circuit is converted to relatively low voltage level with the said relative higher-resistivity state of said nanotube switching element, and it is corresponding to said second logic state in said output terminal output.

5. non-volatile latch circuit as claimed in claim 1; Further be electrically connected storage unit; Wherein when said non-volatile latch circuit is exported said first logic state; Said storage unit is effectively, and wherein when said non-volatile latch circuit is exported said second logic state, said storage unit is invalid.

6. non-volatile latch circuit as claimed in claim 5 is characterized in that, said non-volatile latch circuit comprises the redundant circuit that is used for said storage unit, and can be in said storage unit said storage unit of bypass when being unavailable.

7. non-volatile latch circuit as claimed in claim 5 is characterized in that, the said storage unit of bypass comprises correct errors.

8. non-volatile latch circuit as claimed in claim 1; Further be electrically connected storage unit; Said storage unit can store first and second memory state; Wherein said first memory state is input to said input end as first logic state; And kept through said non-volatile latch circuit non-volatilely and be output as said first logic state, and wherein said second memory state is input to said input end as second logic state, and kept through said non-volatile latch circuit non-volatilely and be output as said second logic state.

9. non-volatile latch circuit as claimed in claim 8; It is characterized in that; Said non-volatile latch circuit comprises the redundant circuit that is used for said storage unit, and can keep corresponding respectively to said first and said first and second logic state of said second memory state non-volatilely.

10. non-volatile latch circuit as claimed in claim 8 is characterized in that, said storage unit comprises the unit in the NRAM array.

11. non-volatile latch circuit as claimed in claim 9 is characterized in that, keeps one of said first and second logic state to comprise: proofread and correct the mistake in the said storage unit non-volatilely.

12. non-volatile latch circuit as claimed in claim 1; Further be electrically connected memory circuitry; Wherein the electro photoluminescence in said input end input comprises time dependent electro photoluminescence; Wherein the electro photoluminescence in said output terminal output comprises time dependent electro photoluminescence, and wherein through between the said time dependent electro photoluminescence of said input end and said output terminal, producing controllable delay, said non-volatile latch circuit is controlled the operation of said memory circuitry.

13. non-volatile latch circuit as claimed in claim 12 is characterized in that, produces controllable delay and comprises: provide to have selected rise time of essence and the essence essence dual mode signal of selected fall time.

14. non-volatile latch circuit as claimed in claim 1; It is characterized in that; Said nanotube switching element comprises fuse once able to programme, and said fuse once able to programme can only switch to said relative higher-resistivity state from said relatively low resistance states.

15. non-volatile latch circuit as claimed in claim 14 is characterized in that, said fuse once able to programme more comprises the insulating material that is arranged on the said nano tube structure goods.

16. non-volatile latch circuit as claimed in claim 15; It is characterized in that; Said nano tube structure goods are exposed in the part that opening limited in the said insulating material, and wherein said fuse once able to programme can switch to said relative higher-resistivity state from said relatively low resistance states through laser ablation.

17. non-volatile latch circuit as claimed in claim 1 is characterized in that, said nanotube switching element comprises fuse once able to programme, and said fuse once able to programme can switch to conducting state from cut-off state.