CN101539894B - Method and device for accessing external equipment of computer into computer system - Google Patents
Method and device for accessing external equipment of computer into computer system Download PDFInfo
- Publication number
- CN101539894B CN101539894B CN2009101371027A CN200910137102A CN101539894B CN 101539894 B CN101539894 B CN 101539894B CN 2009101371027 A CN2009101371027 A CN 2009101371027A CN 200910137102 A CN200910137102 A CN 200910137102A CN 101539894 B CN101539894 B CN 101539894B
- Authority
- CN
- China
- Prior art keywords
- flash
- data
- particle
- computer peripheral
- flash particle
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Bus Control (AREA)
Abstract
The invention provides a method and a device for accessing external equipment of a computer into a computer system; the method comprises the steps of: converting a command of a high-speed peripheral component interconnecting standard PCI-E protocol of the computer system into a command of the internal format of an external equipment access management device; and converting the command of the internal format of the external equipment access management device into a command for operating the external equipment of the computer, communicating with the external equipment of the computer, and implementing the command for operating the external equipment of the computer. The invention improves the performance of the external equipment of the computer for accessing the computer system, and accelerates the data transmission and processing speed between the computer external equipment and the computer system.
Description
Technical field
The present invention relates to computer realm, relate in particular to a kind of method and apparatus that computer peripheral is inserted computer system.
Background technology
As shown in Figure 1, for the prior art computer peripheral inserts the computer system architecture synoptic diagram, computer system generally is made up of CPU 105, internal memory 106, system bus 104, north bridge 103 and south bridge 102, and computer peripheral 101 inserts this computer system by south bridge 102.North bridge 103 is connecting system bus 104, the main data interaction of being responsible between CPU 105 and the internal memory 106, and control AGP (Accelerated Graphics Port, Accelerated Graphics Port), PCI (Peripheral ComponentInterconnect, peripheral component interconnection) the data transmission of portion within it.The communication that south bridge 102 is responsible between the I/O bus.With respect to north bridge 103, the equipment that south bridge 102 is responsible for articulating or managing generally is slow devices, and data processing amount is less than normal; For example pci bus, USB (Universal Serial BUS, USB (universal serial bus)) bus, ATA (Advanced Technology Attachment, AT attachment), SATA (Serial Advanced Technology Attachment, Serial Advanced Technology Attachment, a kind of serial hardware driver interface), audio frequency control module, Keyboard Control unit etc. based on industry standard.
In realizing process of the present invention, the inventor finds that there are the following problems at least in the prior art: in the existing framework of Fig. 1, computer peripheral 101 (as hard disk etc.) be articulated on the south bridge 102, south bridge 102 carries out data interaction by north bridge 103 and CPU 105, internal memory 106 again.Along with development of computer, computer peripheral 101 (particularly solid state hard disc etc.) fast development has developed into computing machine high speed external unit, and its message transmission rate and capacity have huge lifting.Because south bridge 102 is own towards slow devices, project organization is comparatively simple, and need by north bridge 103 connecting system buses 104, more and more can't satisfy the demand of the computer peripheral after the development, existing framework more and more becomes the important bottleneck that influences computing power.
Summary of the invention
The embodiment of the invention provides a kind of computer peripheral is inserted the method and apparatus of computer system, improves computer peripheral and inserts performance of computer systems.
On the one hand, the embodiment of the invention provides a kind of computer peripheral has been inserted the method for computer system, and described method comprises:
With the command conversion of the high-speed peripheral component interconnection PCI-E agreement of described computer system is the order of external unit access-in management device internal format;
With the command conversion of described external unit access-in management device internal format is to the order of described computer peripheral operation, carries out communication with described computer peripheral, carries out the order to described computer peripheral operation.
On the other hand, the embodiment of the invention provides a kind of external unit access-in management device, is used for computer peripheral is inserted computer system, and described computer system links to each other with external unit access-in management device by the PCI-E bus, and described device comprises:
Interface unit, the command conversion that is used for the PCI-E agreement of described computer system is the order of described device internal format;
Command queue's administrative unit is used for the command conversion of device internal format is the order to the computer peripheral operation;
Control module is used for carrying out communication with computer peripheral, carries out the order to the computer peripheral operation.
Technique scheme has following beneficial effect: the order of computer system PCI-E agreement finally is converted to the order that computer peripheral is operated, and execution is to the technological means of the order of computer peripheral operation, insert performance of computer systems thereby improved computer peripheral, accelerated the data transmission and processing speed between computer peripheral and the computer system.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art below, apparently, accompanying drawing in describing below only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is that the prior art computer peripheral inserts the computer system architecture synoptic diagram;
Fig. 2 is the method flow synoptic diagram that the embodiment of the invention inserts computer peripheral computer system;
Fig. 3 is an embodiment of the invention external unit access-in management apparatus structure synoptic diagram;
Fig. 4 is the configuration diagram that the described device of embodiment of the invention Fig. 3 is realized with FPGA (Field-Programmable GateArray, field programmable gate array);
Fig. 5 is the structural representation of application example FMU of the present invention (FLASH Management Unit, FLASH management of software ic unit);
To be application example FMU of the present invention be articulated in connection diagram on the system bus as autonomous device to Fig. 6;
Fig. 7 is the connection diagram that application example FMU of the present invention is integrated in the north bridge inside of computer system;
Fig. 8 is the connection diagram that application example FMU of the present invention is integrated in the CPU inside of computer system;
Fig. 9 is the structural representation of the FLASH control module of application example FMU of the present invention;
Figure 10 is the configuration diagram that application example FMU of the present invention realizes with FPGA.
Embodiment
Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
Embodiment one:
As shown in Figure 2, be the method flow synoptic diagram that the embodiment of the invention inserts computer peripheral computer system.Described method comprises:
Need to prove that described computer system links to each other with external unit access-in management device by the PCI-E bus; Described external unit access-in management device links to each other with system bus by the CPU or the north bridge of described computer system;
Preferably, described external unit access-in management device is integrated in the north bridge inside or the CPU inside of computer system, perhaps is articulated on the system bus of described computer system as autonomous device;
Need to prove, when described external unit access-in management device is integrated in the north bridge inside of described computer system or CPU when inner, can be the order of PCI-E agreement with the data conversion of system bus by north bridge or CPU, this device be converted into the order of PCI-E agreement the order of this device internal format then.What certainly can understand is, in another embodiment, can be the order of PCI-E agreement with the data conversion of system bus by this device also, and this device is converted into the order of PCI-E agreement the order of this device internal format then.
Need to prove, because in computer system, north bridge directly links to each other with system bus, when described external unit access-in management device is articulated on the system bus of described computer system as autonomous device, in one embodiment, described device can link to each other with north bridge by the PCI-E bus.The data of north bridge receiving system bus are translated into the order of PCI-E agreement at this moment, send this device to, and this device is the order of the internal format of self with command conversion of computer system PCI-E agreement.
Be understandable that, in another embodiment, external unit access-in management device also can directly link to each other with system bus by the PCI-E bus, the data of this device receiving system bus, with the data conversion of system bus is the order of PCI-E agreement, and the command conversion of PCI-E agreement is installed the order of the internal format of self for this.
Described command conversion with computer system PCI-E agreement is the commands steps of external unit access-in management device internal format, can realize by integrated circuit (IC) chip or on-site programmable gate array FPGA.The order support of described external unit access-in management device internal format is the addressing and the data manipulation of unit with the sector, can certainly support with the page or leaf to be the addressing and the data manipulation of unit, can certainly support simultaneously that with sector and page or leaf be the addressing and the data manipulation of unit.
Preferably, described command conversion with external unit access-in management device internal format can realize by FPGA for the commands steps to the computer peripheral operation.The order support of described external unit access-in management device internal format is the addressing and the data manipulation of unit with the sector, can certainly support with the page or leaf to be the addressing and the data manipulation of unit, can certainly support simultaneously that with sector and page or leaf be the addressing and the data manipulation of unit.
Preferably, described computer peripheral is a computing machine high speed external unit, and described computing machine high speed external unit comprises one or more in storage particle, network interface card, the optical fiber, and described storage particle further comprises flash memory FLASH particle.
The above embodiment of the present invention is because adopt the order with computer system PCI-E agreement finally to be converted to the order that computer peripheral is operated, and execution is to the technological means of the order of computer peripheral operation, insert performance of computer systems thereby improved computer peripheral, accelerated the data transmission and processing speed between computer peripheral and the computer system.
As shown in Figure 3, be embodiment of the invention external unit access-in management apparatus structure synoptic diagram, this device is used for computer peripheral is inserted computer system, and described device comprises:
Command queue's administrative unit 302 is used for the command conversion of device internal format is the order to the computer peripheral operation;
Need to prove that described computer system links to each other with external unit access-in management device by the PCI-E bus; Described external unit access-in management device links to each other with system bus by the CPU or the north bridge of described computer system;
Preferably, this device can link to each other with the PCI-E bus of described computer system, can be integrated in the north bridge inside or the CPU inside of described computer system, perhaps can be used as autonomous device and is articulated on the system bus of described computer system; When on the system bus that is articulated in described computer system as autonomous device, described device can also comprise interface conversion unit, be used for the order that command conversion that the system bus with described computer system sends becomes described computer system PCI-E agreement, when this installs when integrated, the function of this interface conversion unit can be realized by north bridge or CPU.Described computer peripheral can be computing machine high speed external unit, and described computing machine high speed external unit can comprise one or more in storage particle, network interface card, the optical fiber, and described storage particle further can comprise flash memory FLASH particle.Described interface unit can be realized by integrated circuit (IC) chip or on-site programmable gate array FPGA; Described command queue administrative unit and described control module can be realized by FPGA.As shown in Figure 4, be the configuration diagram that the described device of embodiment of the invention Fig. 3 is realized with FPGA.The order of described external unit access-in management device internal format can support with the sector to be the addressing and the data manipulation of unit, also can support with the page or leaf to be the addressing and the data manipulation of unit, can certainly support simultaneously that with sector and page or leaf be the addressing and the data manipulation of unit.
The above embodiment of the present invention is because adopt the order with computer system PCI-E agreement finally to be converted to the order that computer peripheral is operated, and execution is to the technological means of the order of computer peripheral operation, insert performance of computer systems thereby improved computer peripheral, accelerated the data transmission and processing speed between computer peripheral and the computer system.
Embodiment two:
In September, 1956, the engineering group of IBM has showed the first cover disk system IBM 350RAMAC (Random Access Method of Accounting and Control) to the world, the total volume of this cover system has only 5MB, having used 50 diameters is 24 inches disk, and magnetic head can move by any storage area on disc.Nineteen sixty-eight, IBM Corporation has proposed " Winchester (Winchester) " promptly so-called " Winchester disk " technology again, and this also is the prototype of modern most hard disks.To eighties of last century nineties, IBM applies to MR (magnetoresistive head) head technology in the hard disk, and gordian techniquies such as magnetic head, motor, interface disc have also had important breakthrough and tremendous development simultaneously.In the time of from this, hard disk begins diversification technological trend development such as little to volume, that capacity is big, rotating speed is fast.
No matter be the personal user, or the enterprise customer, all be endless to the speed of memory device, the pursuit of capacity.The development history in 50 years of hard disk is exactly the speed of hard disk and the development history of capacity; How on original framework, to innovate to some extent, how to break through original framework, constituted the theme of hard disk development history.
Along with the formulation of SATA III standard and perfect, the appearance of solid state hard disc is with fast-developing, hard disk is not traditional slow devices already, and performance has had sizable lifting, existing " hard disk-south bridge-north bridge " structure restriction bottleneck that becomes system performance all the more.
The embodiment of the invention is by increasing FLASH management of software ic unit (FLASH Management Unit FMU), perhaps can be used as autonomous device and is articulated on the system bus of described computer system in that north bridge or CPU being inner.
As shown in Figure 6, being application example FMU of the present invention is articulated in connection diagram on the system bus as autonomous device, certainly in another embodiment, because north bridge directly links to each other with system bus, FMU also can link to each other with north bridge by the PCI-E bus, thereby articulating of realization and system bus, this describes in detail in embodiment one, does not repeat them here;
As shown in Figure 7, be the connection diagram that application example FMU of the present invention is integrated in the north bridge inside of computer system; As shown in Figure 8, be the connection diagram that application example FMU of the present invention is integrated in the CPU inside of computer system.Manage the FLASH particle of outside carry by FMU, realize the function of jumbo external data storage.FMU, it is the control module that CPU is used for managing outside high-capacity and high-speed memory device, simultaneously also have functions such as RAID (Redundant Array of Independent Disk, raid-array) control, wear leveling, power management, as shown in Figure 9.
On the physical structure, FMU can be integrated in north bridge or CPU inside, also can be used as autonomous device and is articulated on the system bus.FMU directly is connected by system bus with CPU, internal memory, can satisfy the bandwidth needs of high speed data transfer.Outside high speed storing equipment such as FLASH particle are by the FMU connecting system.
The FLASH particle generally adopts BGA (Ball Grid Array Package, BGA Package) or TSOP (Thin Small Outline Package, the thin-type small-size encapsulation) packing forms, these two kinds of packing forms all need the FLASH particle is welded on PCB (Printed Circuie Board, the printed wiring board) plate.Concerning External memory equipment, should have the loading of being easy to, dismounting, removable, characteristic such as capacity can be expanded.According to the characteristic requirement, the embodiment of the invention proposes, and one piece or many pieces of FLASH particles are welded on the pcb board, is connected with FMU by SLOT (groove socket) or SOCKET interface shapes such as (sockets); The FMU end provides a plurality of interfaces that can work simultaneously.By aforesaid interface definition, FMU can many pieces of FLASH particles of carry; And the FLASH particle is easy to change, expansion.
For example, as shown in Figure 6, being application example FMU of the present invention is articulated in connection diagram on the system bus as autonomous device; CPU, internal memory and FMU all are articulated on the system bus, and the FLASH particle is by the FMU connecting system.Physically, FMU inserts system bus by the PCI-E bus; FMU and system bus are observed the PCI-E agreement and are carried out communication.
As shown in Figure 5, be the structural representation of application example FMU of the present invention.Interface unit 501 is used for order, data with the PCI-E agreement, is converted to inner order and data layout.After interface unit 501 is received Host Command, be internal command, and order is pushed command queue's administrative unit 502 the PCI-E protocol conversion.Command queue's administrative unit 502 is used for being responsible for the response data read write command, is the order that FLASH is operated with the reading and writing data command conversion.FLASH control module 503 is used for being responsible for carrying out communication with the FLASH array of particles, carries out FLASH read-write, bookkeeping.Need to prove for better corresponding, among Fig. 5 the control module among Fig. 3 303 is replaced by FLASH control module 503 with the title of FMU device.
Interface unit 501 can be realized by the IC chip or the FPGA of special use; Command queue's administrative unit 502 and FLASH control module 503 can be realized by FPGA.As shown in figure 10, be the configuration diagram that application example FMU of the present invention realizes with FPGA.FPGA realizes functions such as the processing of PCI-E interface, order management, FLASH control; Can increase buffer memory and be used for temporal data; The FLASH array of particles is the FLASH array that is used to store data.FPGA is connected with PCI-E bus, FLASH array, is responsible for interface data/order communication, buffer memory control and FLASH control and management.Each management control module is in the inner realization of FPGA.
Reading and writing data with main frame is example explanation:
Main frame issues the read data order, and interface unit 501 receives the PCI-E order, is converted into inner order by interface unit 501, and pushes command queue's administrative unit 502.Command queue's administrative unit 502 is responsible for safeguarding all current command request; When carrying out the read data order, give FLASH control module 503 with it and carry out.The FLASH control module is carried out read operation according to address mapping relation to the FLASH particle; After the FLASH particle was finished, the FLASH control module took out data from the FLASH data register, was carried out data encapsulation according to the PCI-E agreement and was returned by interface.
After main frame issued the write data order, interface unit 501 received the PCI-E order, and interface unit 501 pushes command queue's administrative unit 502 with order.503 couples of FLASH of FLASH control module carry out write operation, and will write execution result and return to interface.Interface unit 501 encapsulates execution result and returns to main frame according to the PCI-E agreement.
For the FMU with complete function, command queue's administrative unit 502, FLASH control module 503 only are to have realized basic reading and writing data function; FMU has functions such as bad block management, ECC (Error Checking and Correcting, bug check and correction), wear leveling, power management simultaneously.These functions are all in the inner realization of FPGA.
As shown in Figure 9, be the structural representation of the FLASH control module 503 of application example FMU of the present invention, described FLASH control module 503 comprises:
Data strip tape handling module 5031 when described FLASH particle is many pieces, is done striping to described FLASH particle and is handled, and the data that need are stored are dispersed on the described many pieces of FLASH particles;
Bad block management module 5032 is used to obtain the bad block message of described FLASH particle, and the valid data that write the bad piece of described FLASH particle are changed in the good piece that is written to described FLASH particle;
Wear leveling module 5033 is used for the erasable number of times of each FLASH particle is added up; When described FLASH particle satisfies when pre-conditioned, the data of described FLASH particle storage are transferred on the less FLASH particle of erasable number of times; Wherein, described FLASH particle satisfies the pre-conditioned erasable number of times of described FLASH particle that comprises and reaches preset times;
Bug check and correction ECC module 5034 were used for before data write described FLASH particle, described data are carried out verification calculate, and the verification information adding after described data, is write described FLASH particle again; After described data read out from described FLASH particle, according to described check information, to described data check with error correction after, described data are returned;
The order support of described device internal format is the addressing and the data manipulation of unit with the sector, also can support with the page or leaf to be the addressing and the data manipulation of unit, can certainly support simultaneously that with sector and page or leaf be the addressing and the data manipulation of unit.
As Fig. 5 and shown in Figure 9, FMU is the center with FLASH control module 503, command queue's administrative unit 502 be as with the front end of main frame interaction response, the ECC module 5034 in the FLASH control module 503 is directly related with the FLASH data of rear end; Simultaneously, FLASH control module 503 also passes through bad block management module 5032, wear leveling module 5033 and power management module 5035 wherein, realizes the control and management to the FLASH chip.
Bad block management module 5032 and wear leveling module 5033, all are the bookkeepings to FLASH, when FLASH was carried out erasable operation, FLASH wiped failure or writes failure if report, this information can be known by the FLASH control module, and transfer to bad block management module 5032 and handle.Bad block management module 5032 chooses piece and replaces bad piece from reserved block.Wear leveling module 5033 realizes balance policy; It adds up the erasable data of FLASH; When needs carry out equilibrium to the FLASH piece, realize the transfer resettlement of data at different FLASH interblocks.
The major function that FMU has is:
A, support control and management to FLASH.FMU built-in FLASH control module by the FLASH control module, carries out drive controlling to the FLASH chip of carry.The FLASH control module can be at the sequential requirement of dissimilar chips, the FLASH chip is carried out reading and writing data, copyback (write-back), piece wipe, read functions such as ID, sheet choosing.
B, support FLASH bad block management.By the FLASH control module, FMU can read the bad block message that dispatches from the factory of FLASH chip; Obtain newly-increased bad block message in the time of can moving in real time.Bad block message is recorded in the built-in storage unit of FMU, or in the retention data piece of FLASH chip.By the bad piece of record and management FLASH chip, can avoid valid data to record in the piece of damage, guaranteed the validity of data.
C, support of the reading and writing data request of CPU, DMA (Direct Memory Access, direct memory access) controller to the FLASH chip.CPU or dma controller are converted to corresponding control command to the reading and writing data request of FLASH storage chip via FMU, and drive the FLASH execution by the FLASH control module; FMU is organized into CPU or the understandable form of dma controller with the result and returns.
D, support ECC (Error Checking and Correcting, bug check and correction) verifying function.When data were imported FMU into, the ECC module of FMU inside was carried out ECC verification calculating to data, again data and ECC information is write FLASH; When reading of data, the ECC module is verified data according to ECC information; When finding that data have damage, the ECC module can be corrected mistake wherein.
E, support data striping function.When many pieces of FLASH chips of FMU carry, FMU can do striping to the FLASH chip and handle, and data are dispersed on the many pieces of FLASH chips, makes full use of the characteristics such as latent period of FLASH chip, improves the throughput rate of data.
F, has the wear leveling function.Storage unit at the FLASH chip has certain erasing and writing life, must carry out wear leveling to the FLASH particle.FMU has FLASH chip wear leveling function.FMU adds up the erasable number of times of FLASH storage unit, and manages according to predefined trigger condition; When storage unit satisfies certain condition, promptly storage unit is carried out equalization operation; The data of its storage are transferred on the less storage unit of erasable number of times (in general, the FLASH particle that a collection of product uses, its erasable number of times all are the same or at an order of magnitude. refer to the actual erasable number of times that has taken place herein).
G, has power management function.The power management module that FMU is built-in can be added up the read-write number of times of recent FLASH chip; According to the read-write active degree of FLASH chip, the device of FLASH chip, FMU is carried out power management.When system did not carry out read-write operation to FLASH in the long period, the part of devices of FMU control FLASH chip, FMU entered standby mode, or does power down process.
H, support multiple access mode.It is the addressing and the data manipulation of unit that FMU supports with the sector, supports with the page or leaf to be the addressing and the data manipulation of unit equally.In the conventional architectures, hard disk is that unit carries out addressing and data manipulation with the sector; For CPU and dma controller, be that unit internally deposits into the line pipe reason with the page or leaf.In FMU inside, sector or page or leaf all are converted into internal unit, transfer to the unified processing in rear end again.It is the data management of unit that FMU supports with the sector or with the page or leaf, for memory device from south bridge northwards bridge migration provide and seamlessly transitted.
CPU or dma controller are by system bus and FMU communication.During the main frame reading of data, after interface is received read command, the address translation of host requests is home address after, request of data is pushed in the command queue.Command queue's administrative unit 502 is responsible for the processing command formation; After current queue is gone to read request, give FLASH control module 503,, data are taken out by its control FLASH particle with read request.After data are taken out from FLASH, carry out data check via the ECC module after, by interface unit 501 it is encapsulated as the intelligible form of main frame and returns.When main frame writes data, after interface unit 501 receives write order, be home address with the address translation of host requests, cache management is in charge of the data of importing into, and write order is pushed in the command queue.Data, write in the FLASH particle behind the adding check information through ECC module 5034.After said process was finished, interface unit 501 returned the information of finishing of writing.
The FLASH particle is under the management of FMU, and the inner RAID of setting up with the data striping, has fully guaranteed the high speed of memory device end.Simultaneously, the FLASH particle directly inserts data bus by FMU, has removed from traditionally via south bridge-north bridge, arrives the step of data bus again, has effectively improved the performance of data path.And, FMU not only supports with the sector to be the addressing and the data manipulation of unit, as can be with LBA (LBA (Logical Block Addressing), logic block address) carries out reading and writing data, can certainly support with the page or leaf to be the reading and writing data request of unit, for CPU, dma controller provide same data management interface, simplified system architecture.What certainly can understand is to support simultaneously that also with sector and page or leaf be the addressing and the data manipulation of unit.
The embodiment of the invention is passed through integrated at north bridge or CPU inside, or independently articulates FMU, by FMU the FLASH particle of outside carry is managed, and realizes that memory device inserts the purpose of computer system.The embodiment of the invention has solved the performance bottleneck that traditional " hard disk-south bridge-north bridge " framework brings, and provide flexibly, solution easily.The embodiment of the invention is easy to expand, manages and uses.For the computing machine of the particular architectures that does not adopt north bridge, south bridge design, when the performance of its external unit and system's access point became the bottleneck of influence integral body, the embodiment of the invention all had positive reference significance.Computer peripheral described herein is a computing machine high speed external unit, described computing machine high speed external unit comprises one or more in storage particle, network interface card, the optical fiber, described storage particle further comprises flash memory FLASH particle etc., and the present invention is not as limit.
One of ordinary skill in the art will appreciate that all or part of step that realizes in the foregoing description method is to instruct related hardware to finish by program, described program can be stored in the computer read/write memory medium, this program is when carrying out, comprise above-mentioned all or part of step, described storage medium, as: ROM/RAM, disk, CD etc.
Above-described embodiment; purpose of the present invention, technical scheme and beneficial effect are further described; institute is understood that; the above only is the specific embodiment of the present invention; and be not intended to limit the scope of the invention; within the spirit and principles in the present invention all, any modification of being made, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (15)
1. one kind is inserted the method for computer system with computer peripheral, it is characterized in that described method comprises:
With the command conversion of the high-speed peripheral component interconnection PCI-E agreement of described computer system is the order of external unit access-in management device internal format;
With the command conversion of described external unit access-in management device internal format is to the order of described computer peripheral operation, carries out communication with described computer peripheral, carries out the order to described computer peripheral operation.
2. method according to claim 1, it is characterized in that, described computer peripheral is a computing machine high speed external unit, and described computing machine high speed external unit comprises one or more in storage particle, network interface card, the optical fiber, and described storage particle comprises flash memory FLASH particle.
3. as method as described in the claim 2, it is characterized in that described and described computer peripheral carries out communication, the order of carrying out described computer peripheral operation comprises:
Obtain the bad block message of described FLASH particle, the valid data that write the bad piece of described FLASH particle are changed in the good piece that is written to described FLASH particle.
4. as method as described in the claim 2, it is characterized in that described and described computer peripheral carries out communication, the order of carrying out described computer peripheral operation comprises:
Erasable number of times to each FLASH particle is added up; When described FLASH particle satisfies when pre-conditioned, the data of described FLASH particle storage are transferred on the less FLASH particle of erasable number of times; Wherein, described FLASH particle satisfies the pre-conditioned erasable number of times of described FLASH particle that comprises and reaches preset times.
5. as method as described in the claim 2, it is characterized in that described and described computer peripheral carries out communication, the order of carrying out described computer peripheral operation comprises:
The data that needs write the FLASH particle are carried out verification calculating, and the verification information adding after described data, is write described FLASH particle again; After described data read out from described FLASH particle, according to described check information, to described data check with error correction after, described data are returned.
6. as method as described in the claim 2, it is characterized in that described and described computer peripheral carries out communication, the order of carrying out described computer peripheral operation comprises:
The long-time not described FLASH particle of operation is carried out standby or powered-down processing.
7. as claim 1-6 method as described in each, it is characterized in that,
The order support of described external unit access-in management device internal format is the addressing and the data manipulation of unit with sector or page or leaf.
8. an external unit access-in management device is used for computer peripheral is inserted computer system, it is characterized in that, described computer system links to each other with external unit access-in management device by the PCI-E bus, states device and comprises:
Interface unit, the command conversion that is used for the PCI-E agreement of described computer system is the order of described device internal format;
Command queue's administrative unit is used for the command conversion of described device internal format is the order to described computer peripheral operation;
Control module carries out communication with described computer peripheral, carries out the order to described computer peripheral operation.
9. as device as described in the claim 8, it is characterized in that described device is integrated in the north bridge inside or the CPU inside of described computer system, perhaps is articulated on the system bus of described computer system as autonomous device.
10. as device as described in the claim 8, it is characterized in that, described computer peripheral is a computing machine high speed external unit, and described computing machine high speed external unit comprises one or more in storage particle, network interface card, the optical fiber, and described storage particle further comprises flash memory FLASH particle.
11., it is characterized in that described control module also comprises as device as described in the claim 10:
Data strip tape handling module when described FLASH particle is many pieces, is done striping to described FLASH particle and is handled, and the data that need are stored are dispersed on the described many pieces of FLASH particles.
12., it is characterized in that described control module also comprises as device as described in the claim 10:
The bad block management module is used to obtain the bad block message of described FLASH particle, and the valid data that write the bad piece of described FLASH particle are changed in the good piece that is written to described FLASH particle.
13., it is characterized in that described control module also comprises as device as described in the claim 10:
The wear leveling module is used for the erasable number of times of each FLASH particle is added up; When described FLASH particle satisfies when pre-conditioned, the data of described FLASH particle storage are transferred on the less FLASH particle of erasable number of times; Wherein, described FLASH particle satisfies the pre-conditioned erasable number of times of described FLASH particle that comprises and reaches preset times.
14., it is characterized in that described control module also comprises as device as described in the claim 10:
Bug check and correction ECC module were used for before data write described FLASH particle, described data are carried out verification calculate, and the verification information adding after described data, is write described FLASH particle again; After described data read out from described FLASH particle, according to described check information, to described data check with error correction after, described data are returned.
15., it is characterized in that described control module also comprises as device as described in the claim 10:
Power management module is used for the long-time not described FLASH particle of operation is carried out standby or powered-down processing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101371027A CN101539894B (en) | 2009-05-04 | 2009-05-04 | Method and device for accessing external equipment of computer into computer system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009101371027A CN101539894B (en) | 2009-05-04 | 2009-05-04 | Method and device for accessing external equipment of computer into computer system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101539894A CN101539894A (en) | 2009-09-23 |
| CN101539894B true CN101539894B (en) | 2011-04-13 |
Family
ID=41123089
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2009101371027A Active CN101539894B (en) | 2009-05-04 | 2009-05-04 | Method and device for accessing external equipment of computer into computer system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101539894B (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102253812A (en) * | 2011-07-08 | 2011-11-23 | 浪潮电子信息产业股份有限公司 | Method for improving soft RAID (redundant array of independent disk) performance based on Loongson processor |
| WO2014094250A1 (en) * | 2012-12-19 | 2014-06-26 | 华为技术有限公司 | Data processing method and device |
| CN105306421A (en) * | 2014-06-30 | 2016-02-03 | 中兴通讯股份有限公司 | PCI-E interface based signal processing method and PCI-E interface based signal processing device |
| CN105161132A (en) * | 2015-08-27 | 2015-12-16 | 浪潮电子信息产业股份有限公司 | NVMe SSD read-only protection method based on FPGA |
| EP3361385A4 (en) * | 2015-12-03 | 2018-11-21 | Huawei Technologies Co., Ltd. | Data migration method applicable to computer system, and device and computer system utilizing same |
-
2009
- 2009-05-04 CN CN2009101371027A patent/CN101539894B/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN101539894A (en) | 2009-09-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10949105B2 (en) | Data storage device and operating method of the data storage device | |
| JP5566650B2 (en) | Memory device for hierarchical memory architecture | |
| US8719495B2 (en) | Concatenating a first raid with a second raid | |
| US11520660B2 (en) | Storage devices hiding parity swapping behavior | |
| US20110035540A1 (en) | Flash blade system architecture and method | |
| TWI432965B (en) | Memory systems with a plurality of structures and methods for operating the same | |
| CN101354906B (en) | Flash memory controller for solid hard disk | |
| US20200218653A1 (en) | Controller, data storage device, and operating method thereof | |
| CN104423888A (en) | Data writing method, memory control circuit unit and memory storage device | |
| CN101539894B (en) | Method and device for accessing external equipment of computer into computer system | |
| WO2021242317A1 (en) | Zns parity swapping to dram | |
| KR20210038753A (en) | Data Storage Apparatus and Operating Method Thereof | |
| CN109240603A (en) | full flash memory server | |
| CN103729148A (en) | SSD with RAID function | |
| US10031689B2 (en) | Stream management for storage devices | |
| EP4320508A1 (en) | Method and apparatus to reduce nand die collisions in a solid state drive | |
| CN102929813A (en) | Method for designing peripheral component interconnect express (PCI-E) interface solid hard disk controller | |
| CA2134016A1 (en) | Data storage device and method of operation | |
| US20150161038A1 (en) | System and Method of Operation for High Capacity Solid-State Drive | |
| CN102160038A (en) | Method and an apparatus to manage non-volatile disl cache | |
| US12045506B2 (en) | Combining operations during reset | |
| US11853571B2 (en) | Storage devices hiding parity swapping behavior | |
| CN114168067B (en) | NVMe simple replication command support using dummy virtual functions | |
| US9009389B2 (en) | Memory management table processing method, memory controller, and memory storage apparatus | |
| US11157401B2 (en) | Data storage device and operating method thereof performing a block scan operation for checking for valid page counts |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: HUAWEI DIGITAL TECHNOLOGY (CHENGDU) CO., LTD. Free format text: FORMER NAME: CHENGDU HUAWEI SYMANTEC TECHNOLOGIES CO., LTD. |
|
| CP01 | Change in the name or title of a patent holder |
Address after: 611731 Chengdu high tech Zone, Sichuan, West Park, Qingshui River Patentee after: HUAWEI DIGITAL TECHNOLOGIES (CHENG DU) Co.,Ltd. Address before: 611731 Chengdu high tech Zone, Sichuan, West Park, Qingshui River Patentee before: CHENGDU HUAWEI SYMANTEC TECHNOLOGIES Co.,Ltd. |
|
| TR01 | Transfer of patent right |
Effective date of registration: 20220804 Address after: 518129 Bantian HUAWEI headquarters office building, Longgang District, Guangdong, Shenzhen Patentee after: HUAWEI TECHNOLOGIES Co.,Ltd. Address before: 611731 Qingshui River District, Chengdu hi tech Zone, Sichuan, China Patentee before: HUAWEI DIGITAL TECHNOLOGIES (CHENG DU) Co.,Ltd. |
|
| TR01 | Transfer of patent right |