WO2014094250A1

WO2014094250A1 - Data processing method and device

Info

Publication number: WO2014094250A1
Application number: PCT/CN2012/086928
Authority: WO
Inventors: 蔡涛; 龚涛
Original assignee: 华为技术有限公司
Priority date: 2012-12-19
Filing date: 2012-12-19
Publication date: 2014-06-26
Also published as: CN103403667A

Abstract

The present invention provides a data processing method and device. The method comprises: a data control chip acquiring first address information from a front-end interface chip, the first address information being used for indicating an address where first data is to be written or an address where second data is to be read; the data control chip obtaining second address information according to the first address information, the second address information being used for indicating a corresponding position of the first address information in a solid state disk (SSD), and the data control chip being in communication connection to the SSD and the front-end interface chip through a PCI-E interface; and the data control chip transmitting the first data or the second data between the front-end interface chip and the SSD corresponding to the second address information through the PCI-E interface, so that the first data received from the front-end interface chip can be written into the SSD, or the second data can be read from the SSD and transmitted to the front-end interface chip. The present invention can meet the performance demand of a disk array composed of SSDs.

Description

TECHNICAL FIELD The present invention relates to storage technologies, and in particular, to a data processing method and apparatus. Background technique

The array controller is used to connect the service server and the disk array, and is responsible for controlling the service data transmission before the service server and the disk array, which is equivalent to the bridge between the service server and the disk array. The array controller usually includes a front-end interface chip, a back-end control chip, and the like. The front-end interface chip is configured to connect to a service server, and send or receive service data with the service server, for example, send service data received from the service server. To the backend control chip, or send the service data received from the backend control chip to the service server. The back-end control chip is used to connect to the disk array, and the service data transmitted from the front-end interface chip can be written to the disk array, or the service data read from the disk array can be transmitted to the front-end interface chip. The disk array is, for example, a storage array composed of a mechanical hard disk.

With the continuous development and maturity of storage media, the disk array connected to the back-end control chip has also changed from a traditional mechanical hard disk to a solid state disk (SSD). The SSD has an improved ability to read/write Operations Per Second (IOPS) per second compared to a mechanical hard disk. For example, a 2.5-inch SSD, IOPS is equivalent to 100 of the same size of a traditional mechanical hard disk. ~300 times, the performance of the disk array has been greatly improved. However, the back-end control chip in the array controller is designed for the traditional mechanical hard disk. The IOPS capability is limited. When there are 2-4 SSDs in the disk array, the SSD can not support the SSD. The performance requirements, which hinder the performance of the entire disk array. SUMMARY OF THE INVENTION The present invention provides a data processing method and apparatus to accommodate the performance requirements of a disk array composed of SSDs.

In a first aspect, a data processing method is provided, including:

The data control chip acquires first address information from the front end interface chip, where the first address information is used Indicates an address at which the first data is to be written or an address at which the second data is to be read;

The data control chip obtains second address information according to the first address information, where the second address information is used to indicate that the first address information is at a location corresponding to a solid state drive SSD, and the data control chip passes PCI Express ( PCI-E) interface is respectively connected to the SSD and the front-end interface chip

Transmitting, by the data control chip, the first data or the second data between the front-end interface chip and the SSD corresponding to the second address information by using the PCI-E interface, so that the front-end interface is to be The first data received by the chip is written to the SSD, or the second data is read from the SSD and transmitted to the front end interface chip.

With reference to the first aspect, in a first possible implementation, the data control chip transmits, by using the PCI-E interface, the SSD between the front-end interface chip and the SSD corresponding to the second address information. The data or the second data includes: the data control chip transmitting the second address information to the front end interface chip, so that the front end interface chip passes the PCI-E interface of the data control chip, Writing the first data or reading the second data to the SSD corresponding to the second address information in a direct memory access DMA manner.

With reference to the first aspect, in a second possible implementation, the data control chip transmits the first interface chip and the SSD corresponding to the second address information by using the PCI-E interface a data or the second data, comprising: the data control chip acquiring the first data from a memory connected to the data control chip, and writing the first data according to the second address information Entering the corresponding SSD, the first data is that the front-end interface chip is transmitted to the memory through the data control chip; or the data control chip is from the corresponding SSD according to the second address information Reading the second data, and transmitting the second data to a memory connected to the data control chip, so that the front-end interface chip reads the first memory from the memory through the data control chip Two data.

With reference to the first aspect, the first possible implementation manner of the first aspect, or the second possible implementation manner of the first aspect, in a third possible implementation manner, the front interface chip and the Transmitting the first data or the second data between the SSDs corresponding to the second address information, including: when the first data written to the SSD is transmitted through the data control chip, the data control chip The data is mirrored and the mirrored data is sent to a mirrored SSD connected to the data control chip. With reference to the first aspect, the first possible implementation manner of the first aspect, or the second possible implementation manner of the first aspect, in the fourth possible implementation manner, the front interface chip and the Transmitting the first data or the second data between the SSDs corresponding to the second address information includes: when the first data written to the SSD is transmitted through the data control chip, the data The control chip performs verification information calculation on the data, and writes the verification information into the verification SSD in the SSD.

In a second aspect, a data control chip is provided, including:

An information receiving unit, configured to acquire first address information from a front-end interface chip, where the first address information is used to indicate an address to be written into the first data or an address to read the second data;

An information processing unit, configured to obtain second address information according to the first address information, where the second address information is used to indicate that the first address information is at a location corresponding to a solid state drive SSD, and the data control chip passes the PCI Express a (PCI-E) interface is respectively connected to the SSD and the front-end interface chip;

a transmission control unit, configured to transmit, by the PCI-E interface, the first data or the second data between the front-end interface chip and an SSD corresponding to the second address information, so as to be from the front end The first data received by the interface chip is written to the SSD, or the second data is read from the SSD and transmitted to the front end interface chip.

With reference to the second aspect, in a first possible implementation, the transmission control unit is specifically configured to send the second address information to the front-end interface chip, so that the front-end interface chip passes the data The PCI-E interface of the control chip writes the first data or reads the second data to the SSD corresponding to the second address information in a direct memory access DMA manner.

With reference to the second aspect, in a second possible implementation, the transmission control unit is specifically configured to acquire the first data from a memory connected to the data control chip, and according to the second address Transmitting, by the information, the first data to the corresponding SSD, where the first data is transmitted by the front-end interface chip to the memory by using the data control chip; or, according to the second address information, corresponding to Reading, by the SSD, the second data, and transmitting the second data to a memory connected to the data control chip, so that the front-end interface chip reads from the memory through the data control chip The second data.

With reference to the second aspect, the first possible implementation manner of the second aspect, or the second possible implementation manner of the second aspect, in a third possible implementation manner, the method further includes: a mirror protection unit, And when the first data to be written into the SSD is transmitted through the data control chip, the data control chip mirrors the data, and sends the mirrored data to the data control A mirrored SSD connected to the chip.

With the second aspect, the first possible implementation of the second aspect, or the second possible implementation of the second aspect, in a fourth possible implementation, the method further includes: a check protection unit, configured to: When the first data written to the SSD is transmitted through the data control chip, the data control chip performs verification information calculation on the data, and writes the verification information into the

Verification SSD in SSD.

In a third aspect, an array controller is provided, including: a front end interface chip, a solid state hard disk SSD, and a data control chip according to the present invention; and the data control chip separately interfaces with the SSD and the front end interface chip through a PCI-E interface Communication connection.

With reference to the third aspect, in a first possible implementation, the method further includes: a mirroring SSD; the data control chip is communicably connected to the mirrored SSD through a PCI-E interface; and the mirrored SSD is configured to use the data The control chip receives the data copied by the image.

With reference to the third aspect, in a second possible implementation, the method further includes: a memory; the data control chip is connected to the memory through a PCI-E interface; and the memory is configured to receive the first interface chip from the front end interface chip. a data, such that the data control chip acquires the first data from the memory and writes the SSD; or receives, from the data control chip, second data read from the SSD, such that the data The front end interface chip acquires the second data from the memory.

The technical effects of the data processing method and device provided by the present invention are: The data control chip is respectively connected to the SSD and the front-end interface chip by using a PCI-E interface, and is transmitted between the two through the PCI-E interface. Data, the PCI-E interface has high IOPS capability and can accommodate the performance requirements of disk arrays composed of SSDs. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a schematic diagram of an application structure of an embodiment of a data processing method according to the present invention;

2 is a schematic flowchart of an embodiment of a data processing method according to the present invention;

3 is a schematic structural diagram of an application of another embodiment of a data processing method according to the present invention;

4 is a schematic diagram of an unprotected process of another embodiment of a data processing method according to the present invention;

FIG. 5 is a schematic diagram of a mirror image protection process according to another embodiment of a data processing method according to the present invention; FIG. FIG. 6 is a schematic diagram of a verification protection process according to another embodiment of a data processing method according to the present invention; FIG. 7 is a schematic flowchart of still another embodiment of a data processing method according to the present invention;

8 is a schematic structural diagram of an embodiment of a data control chip according to the present invention;

FIG. 9 is a schematic structural diagram of another embodiment of a data control chip according to the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS In order to make the objects, technical solutions and advantages of the present invention more comprehensible, the embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

Embodiment 1

FIG. 1 is a schematic diagram of an application structure of an embodiment of a data processing method according to the present invention, and FIG. 2 is a schematic flowchart of an embodiment of a data processing method according to the present invention.

As shown in FIG. 1, the data control chip can be generally applied to a solid-state storage array controller for connecting a service server and a disk array. The disk array of this embodiment is a storage array composed of SSDs, wherein Multiple SSDs can be included. The solid state storage array controller also includes a front end interface chip for connecting to a service server and for data transmission, and a data control chip for connecting to the SSD array.

The solid-state storage array controller is equivalent to the bridge between the service server and the SSD. For example, the service server writes data to the SSD, or the service server reads data from the SSD. The process of writing or reading data is controlled by the array. Control execution. When writing, the data is transmitted to the SSD through the front-end interface chip and the data control chip; when reading, the data is transmitted from the SSD through the data control chip and the front-end interface chip to the service server. In this embodiment, the connection interface between the data control chip and other devices adopts a PCI-E (Peripheral Component Interconnect Express) interface, for example, communicates with the SSD and the front-end interface chip through a PCI-E interface respectively; therefore, the above In the process of writing the first data to the SSD or reading the second data from the SSD, the transmission in the data control chip is actually transmitted through the PCI-E channel (with the PCI-E interface, it is indicated inside the chip) Transmission via PCI-E channel). In addition, the data control chip SSD of the embodiment of the present invention may be, for example, a storage array composed of SSDs of a PCI-E interface.

As shown in FIG. 2, the data processing method in this embodiment mainly describes how the data control chip controls the data transmission before the service server and the SSD;

201. The data control chip acquires first address information from the front end interface chip. The first address information is used to indicate an address to be written into the first data or an address to read the second data, the first data is to be written into the solid state hard disk SSD, and the second data is to be from the SSD The first address information that is read includes: for example, the address and length to be written, or the address and length to be read. The first address information may be that the service server sends the first address information corresponding to the data to the front-end interface chip when the operation is to be written or read, and then transmitted by the front-end interface chip to the data control chip.

It should be noted that the data control chip in this embodiment obtains the first address information from the front-end interface chip, and the data control chip can be directly obtained from the front-end interface chip, and the data control chip and the front-end interface chip are directly connected; Alternatively, the data control chip may be indirectly obtained from the front-end interface chip. At this time, the data control chip and the front-end interface chip are connected by, for example, a PCI-E switch chip. In this case, the first address information is transmitted from the front-end interface chip to the PCI. The -E switch chip is transferred to the data control chip, and the PCI-E switch chip and the data control chip are still connected through the PCI-E interface.

202. The data control chip obtains second address information according to the first address information, where the second address information is used to indicate that the first address information is at a location corresponding to the SSD of the solid state drive;

The data control chip calculates, according to the first address information acquired in 201, which part of the storage area on which the SSD should receive the data to be written, or calculates which part of the storage area on which the SSD is to be provided. Reading the data, and obtaining the second address information corresponding to the SSD and the storage area thereof, the second address information comprising: the address and the length of the SSD to be written or read. Through this step, the data control chip actually obtains which SSDs should be written to the data or from which SSDs to acquire the data to be read.

203. The data control chip transmits the first data or the second data between the front-end interface chip and the SSD corresponding to the second address information by using the PCI-E interface.

The transmitting data includes: transmitting first data to be written from the front-end interface chip to the SSD, and transmitting second data to be read from the SSD to the front-end interface chip.

Moreover, the first data to be written or the second data to be read may include two ways: One way is that the data control chip sends the second address information to the front-end interface chip, and the front-end interface chip The direct memory access DMA mode directly writes the first data to the SSD, or directly reads the second data from the SSD, and the data control chip is equivalent to providing a data transmission channel for the access. Another way is that the data control chip itself writes the first data to the SSD according to the second address information. Or reading the second data from the SSD, the first data or the second data is also transmitted to the front-end interface chip through the data control chip.

It should be noted that, in this embodiment, data transmission between the front-end interface chip and the SSD is performed by the data control chip, if some data processing in the transmission process, such as data mirroring, data verification, and the like, is involved. The processing is also performed by the data control chip. The above data transmission process and the processing of the data protection are performed by the data control chip, thereby reducing the burden of the central processing unit (CPU) in the array controller, so that the CPU can be used for Processing of other advanced features such as snapshots, deduplication, and so on.

The data processing method of the embodiment achieves the performance requirement of adapting the performance of the disk array composed of the SSD is the following principle: the original back-end control chip is designed for the traditional mechanical hard disk, and the transmission interface and the data transmission are followed. The transmission protocol is adapted to the mechanical hard disk, and the IOPS capability is limited, so the higher IOPS capability of the SSD cannot be satisfied; and the data control chip in this embodiment communicates with the SSD and other devices through the PCI-E interface, correspondingly, The transmission protocol followed by data transmission also uses the PCI-E protocol, that is, the data control chip is changed from hardware (PCI-E interface) and software (PCI-E protocol) to PCI-E mode, the PCI-E. The high transmission IOPS capability of the mode can fully meet the high IOPS performance of the SSD, which is beneficial to the full performance of the SSD.

Embodiment 2

The data between the front-end interface chip and the SSD transmitted by the data control chip may be the first data to be written to the SSD, or may be the second data read from the SSD. Moreover, the manner of transmitting data between the front-end interface chip and the SSD is equivalent to the manner in which the front-end interface chip side accesses the SSD, and may be a character device access mode or a block device access mode. The data control chip of the embodiment of the present invention can support the two. The way to access, that is, to support the two ways of data writing or reading.

This embodiment mainly describes the data control chip supporting the access mode of the character device, and details the data transmission process between the front-end interface chip and the SSD in the character device access mode. In the character device access mode, the front-end interface chip can directly access the SSD by using Direct Memory Access (DMA).

FIG. 3 is a schematic diagram of an application structure of another embodiment of a data processing method according to the present invention. The structure is an optional array controller structure. The data control chip of the embodiment of the present invention is disposed in the array controller. The data control chip supports multiple PCI-E interfaces: for example, through a PCI-E interface and CPU Connected as a data interaction channel between the CPU and the data control chip. Connected to the front-end interface chip through one or more PCI-E interfaces, as a channel for business data and management data (business data is to be written to or read from the SSD, and the management data is stored by the CPU, for example, it can be a service The server transmits to the CPU through the data control chip). The data mirroring control chip is connected to the data mirroring control chip through a PCI-E interface, and the data mirroring channel connected to the data mirroring control chip is used to save the data written by the service server to the SSD to multiple arrays. On the controller, to eliminate the single point of failure of the array controller; that is, Figure 3 shows the structure of an array controller that is connected to another array controller and is responsible for routing between the array controllers. The copy of the mirrored copy data is protected by mirrored data. The SSD array consisting of multiple SSDs at the back end is connected through multiple PCI-E interfaces, and the interfaces of these SSDs are all PCI-E interfaces.

Optionally, the data control chip itself can be directly connected to a separate memory, such as the memory connected to the data control chip shown in FIG. 3, such as when the block device access mode is set; and the character device in this embodiment. In the access mode, since the front-end interface chip can directly access the SSD through the DMA method, the memory of the connection data control chip may not be set.

There are many types of SSD arrays composed of SSDs. For example, if they are classified according to data protection, they can be divided into three categories: unprotected, mirrored, and verified. For example, RAID-0 is unprotected; RAID -1, RAID-10 is a mirror protection type, which provides data protection by copying multiple copies of data to different physical media such as different array controllers. RAID-5, RAID-6 is a type of parity protection, that is, data is passed. Check the way to provide data protection. The following describes the data protection chip in the above three types of data protection mode, how the data control chip controls the data transmission between the front-end interface chip and the SSD. The descriptions of 401, 402, etc. are only used to distinguish the processing. The order of execution is not limited.

FIG. 4 is a schematic diagram of an unprotected process according to another embodiment of the data processing method of the present invention. As shown in FIG. 4, the method may include:

401. The front-end interface chip obtains data to be written into the SSD and the corresponding first address information from the service server, and sends the first address information to the data control chip.

Among them, the front-end interface chip and the service server generally use SCSI (Small Computer System Interface, is a kind of interface bus, which has communication with various types of peripherals) protocol for data interaction; front-end interface chip processing After the protocol interaction with the service server is completed, the service data to be written into the SSD is received from the service server, and the data is referred to as the first data; The front-end interface chip further receives first address information corresponding to the service data, where the first address information is used to indicate an address of the service data to be written into the SSD, and the first address information includes, for example, a write The starting address and length, for example, the starting address of the data to be written is 120, and the length is 8; the 120 is the identifier of the sector on the SSD, and the 8 represents 8 sectors, that is, the sector from the identifier 120. Start writing data and write 8 sectors in succession. The front end interface chip sends the first address information to the data control chip.

The data control chip obtains the second address information according to the first address information, where the second address information is used to indicate that the first address information is at a location corresponding to the SSD of the solid state drive;

The data control chip may obtain second address information of the SSD for storing the data corresponding to the first address information according to the first address information; for example, for an SSD array composed of multiple SSDs, The second address information actually indicates which SSD the eight sectors starting from 120 described in the above 401 are located on, and which position is located in the SSD.

Specifically, the data control chip is provided with a striping rule, according to which the storage space of the plurality of SSDs in the SSD array can be divided into several strips, each strip being part of each SSD. Formed in combination, each portion of each SSD included in each strip includes a plurality of sectors. The data control chip can calculate which SSDs the service data to be written should be received according to the obtained first address information and the striping rule, and which sectors of the SSD are received. For example, the above-mentioned data is written from the sector with the identifier of 120 and written continuously for 8 sectors, that is, equivalent to writing in the 8 sectors whose sector identifier is 120 to 127, the data control chip can It is calculated that the eight sectors are the first SSD located in the SSD array, and are located on the first strip in the first SSD, and the location information of the first SSD and the first strip is Called the second address information.

403. The data control chip sends the second address information to the front-end interface chip, where the data control chip acquires second address information corresponding to the SSD for writing service data, such as the foregoing SSD address and SSD. Information such as the specific location on the front side is sent to the front-end interface chip.

404. The front-end interface chip writes the first data to the SSD corresponding to the second address information by using a direct memory access DMA.

In the embodiment, the character device access mode is used. After receiving the second address information sent by the data control chip, the front-end interface chip directly writes the service data to be written into the corresponding SSD. In this case, the data control chip can not set the connected memory. In this embodiment, the front-end interface chip and the SSD are connected through the data control chip, so even if the front-end interface chip directly accesses the SSD, the data transmission still passes through the data control chip; and, the data is transmitted through the data control chip. The PCI-E channel in the chip is transmitted, enters the chip through the PCI-E interface of the data control chip, and is transmitted to the SSD through the PCI-E interface connected to the SSD.

The above steps 401-404 describe the process of writing the first data to the SSD. The following describes the process of reading the second data from the SSD through steps 405-408:

405. The front-end interface chip obtains first address information corresponding to the second data to be read from the SSD from the service server, and sends the first address information to the data control chip.

When the service server reads the service data from the SSD, it notifies the front-end interface chip of the first address information of the data, including the address and length of the data; the front-end interface chip sends the first address information to the data control chip.

406. The data control chip obtains second address information according to the first address information, where the second address information is used to indicate that the first address information is at a location corresponding to the SSD of the solid state drive;

The data control chip may obtain second address information of the SSD for storing the data corresponding to the first address information according to the first address information. Similarly, the data control chip also calculates which SSDs the service data to be read should be provided according to the pre-stored striping rules and the first address information, and obtains the addresses and read positions of the SSDs, which may be referred to as a second. Address information.

407. The data control chip sends the second address information to the front end interface chip.

408. The front-end interface chip reads the second data from the SSD corresponding to the second address information by using a direct memory access DMA mode.

In the embodiment, the character device access mode is used. After receiving the second address information sent by the data control chip, the front-end interface chip reads the service data directly from the corresponding SSD and transmits the service data to the service. server.

In the character device access mode of this embodiment, since the front-end interface chip directly accesses the SSD, the overall 10 path can be greatly reduced, and the IOPS performance of the array controller can also be improved.

FIG. 5 is a schematic diagram of a mirror protection process according to another embodiment of the data processing method of the present invention. FIG. 5 only shows the steps different from the flow of FIG. 4, and the difference between each step and the corresponding step in FIG. 4 respectively. The description is made, and the same steps are not shown in Figure 5; 501, when the first data is to be written into the SSD, the data control chip obtains the corresponding second address information according to the first address information corresponding to the first data to be written;

The difference between the step and the step 402 is that the data control chip does not calculate the image SSD when calculating the second address information of the SSD, that is, the SSD corresponding to the obtained second address information is not a mirrored SSD. The mirrored SSD is an SSD connected to another array controller connected to the data mirroring control chip of FIG.

502. The front-end interface chip writes the first data to the SSD corresponding to the second address information by using a direct memory access DMA mode; and the data control chip mirrors the data, and sends the mirrored data to the mirror. SSD;

The difference between the step and the step 404 is that when the service data to be written into the SSD passes through the data control chip, in order to improve the security and reliability of the data storage, it is ensured that the image data can be recovered from the mirror data when one of the storage data is faulty. The data control chip mirrors the service data according to the pre-stored mirroring rules, that is, copies the data into multiple copies and writes them into the mirrored SSD to implement the image protection function.

503. When the second data is to be read from the SSD, the data control chip obtains the corresponding second address information according to the first address information corresponding to the second data to be read.

The difference between the step and the step 406 is that the data control chip can calculate the image SSD when calculating the second address information of the SSD, that is, the SSD corresponding to the obtained second address information may also be a mirrored SSD. For example, when the SSD connected to the data control chip fails, it may select a certain SSD in the mirrored SSD to provide data according to the mirroring rule. The selected strategy may be to select a relatively idle SSD, or may be random. select.

504. The front-end interface chip reads the second data from the SSD corresponding to the second address information by using a direct memory access DMA mode.

The difference between the step and the step 408 is that if the data control chip returns to the front-end interface chip in 503 is the second address information corresponding to the mirrored SSD, the front-end interface chip in this step is directly from the corresponding DMA mode. Mirror the SSD to read the data.

FIG. 6 is a schematic diagram of a verification protection process according to another embodiment of the data processing method of the present invention, and FIG. 6 only shows steps different from the flow of FIG. 4, and respectively for each step relative to the corresponding step in FIG. The differences are explained, and the same steps are not shown in Figure 6;

601. When the first data is to be written into the SSD, the front-end interface chip accesses the DMA with direct memory. The method writes the data to the SSD corresponding to the second address information; and, the data control chip performs verification information calculation on the data, and writes the verification information into the verification SSD;

The difference between the step and the step 404 is: when the first data written to the SSD is transmitted through the data control chip, the data control chip performs the verification information on the first data to obtain Verifying the information, and writing the verification information to the verification SSD in the SSD; the verification SSD is a device for storing verification information in the SSD array, thereby implementing verification protection of the first data.

In addition, since the data to be written can be divisible by the size of the stripe, there is no write penalty, and it is also possible to directly calculate the checksum, which is also called check information.

602. When the second data is to be read from the SSD, the data control chip obtains the corresponding second address information according to the first address information corresponding to the second data to be read.

The difference between the step and the step 406 is that, for example, when an SSD in the SSD connected to the data control chip fails, if the data control chip finds that the second data to be read is in the failed SSD In this case, the data control chip can recover the second data to be read according to the data or information (for example, the verification information) stored by the remaining SSDs that are still working normally, and store the restored second data in the data. On a normal SSD. The SSD corresponding to the second address information returned by the data control chip to the front-end interface chip is the SSD of the storage recovery data.

Embodiment 3

This embodiment mainly describes the data control chip supporting the access mode of the block device, and illustrates the data transmission process between the front-end interface chip and the SSD in the block device access mode. In this way, the data transmission process can refer to the flow arrow shown in Figure 3 (the write flow is shown in Figure 3). At this time, the data control chip needs to be connected to the memory, used to cache the service data, and the data control. A memory controller can also be embedded in the chip to control the transfer of data to the memory.

FIG. 7 is a schematic flowchart of another embodiment of a data processing method according to the present invention. The processing procedure in the access mode of the block device in the embodiment is the same as the processing flow in the access mode of the character device, and details are not described herein. Steps, including:

701, the front-end interface chip obtains the first data to be written into the SSD and the corresponding first address information from the service server; and the front-end interface chip transmits the acquired first data to the memory connected to the data control chip, and the first The address information is sent to the data control chip;

The front interface chip of the embodiment transmits the first data to and from the DMA. In the memory connected to the data control chip, as shown by the arrow line in FIG. 3, the first data is first transmitted to the data control chip through the PCI-E interface, and then transmitted to the memory after the data control chip.

Optionally, if the image protection is captured, when the first data passes through the data control chip, the data control chip mirrors the first data, and sends the first data copied by the mirror to the adjacent array controller. Mirror SSD.

Optionally, if the check protection is performed, when the first data passes through the data control chip, the data control chip performs check information calculation on the first data to obtain verification information.

702. The data control chip obtains corresponding second address information according to the first address information.

703, the data control chip obtains the first data from the connected memory, and writes the first data to the corresponding SSD according to the second address information;

In this embodiment, the first data is written into the SSD by the data control chip itself, and the data control chip further performs related processing such as stripe splitting on the first data.

Optionally, if the check protection is taken, the data control chip further sends the calculated verification information to the verification SSD in this step.

704. The data control chip deletes the first data cached in the memory.

Wherein, after the data control chip completely writes the first data into the SSD, the data control chip deletes the cached data in the connected memory;

Optionally, if the image protection is captured, in this step, the data control chip may first send a command to the adjacent array controller connected to the data mirror control chip, indicating to delete the first cache in the adjacent array controller. Data, and then delete the cached data in the local direct-attached memory.

705. The front-end interface chip obtains, from the service server, first address information corresponding to the second data to be read from the SSD, and sends the first address information to the data control chip.

706. The data control chip obtains corresponding second address information according to the first address information.

707. The data control chip reads the second data from the corresponding SSD according to the second address information, and transmits the second data to a memory connected to the data control chip.

708. The front-end interface chip reads the second data from the memory by using the data control chip in a direct memory access DMA mode.

Embodiment 4

FIG. 8 is a schematic structural diagram of an embodiment of a data control chip according to the present invention. The data control chip can perform the method of any embodiment of the present invention. As shown in FIG. 8, the data control chip can include: The information receiving unit 81, the information processing unit 82, and the transmission control unit 83; wherein the information receiving unit 81 is configured to acquire first address information from the front end interface chip, where the first address information is used to indicate that the first data is to be written. Address or address to read the second data;

The information processing unit 82 is configured to obtain second address information according to the first address information, where the second address information is used to indicate that the first address information is at a location corresponding to a solid state drive SSD, and the data control chip passes the PCI An Express (PCI-E) interface is respectively connected to the SSD and the front end interface chip;

a transmission control unit 83, configured to transmit, by using the PCI-E interface, the first data or the second data between the front-end interface chip and an SSD corresponding to the second address information, so that The first data received by the front end interface chip is written to the SSD, or the second data is read from the SSD and transmitted to the front end interface chip.

Further, the transmission control unit 83 is specifically configured to send the second address information to the front-end interface chip, so that the front-end interface chip passes the PCI-E interface of the data control chip to directly store The access DMA mode writes the first data or reads the second data to an SSD corresponding to the second address information.

Further, the transmission control unit 83 is specifically configured to acquire the first data from a memory connected to the data control chip, and write the first data into a corresponding one according to the second address information. The SSD, the first data is that the front-end interface chip is transmitted to the memory through the data control chip; or, the second data is read from the corresponding SSD according to the second address information, And transmitting the second data to a memory connected to the data control chip, so that the front end interface chip reads the second data from the memory through the data control chip.

FIG. 9 is a schematic structural diagram of another embodiment of the data control chip of the present invention. As shown in FIG. 9, the data control chip of this embodiment may further include:

The image protection unit 84 is configured to: when the first data written to the SSD is transmitted through the data control chip, the data control chip mirrors the data, and sends the mirrored data to A mirrored SSD connected to the data control chip.

Further, the method further includes: a check protection unit 85, configured to: when the first data written into the SSD is transmitted through the data control chip, the data control chip performs verification information on the data Calculating, and writing the verification information to the verification SSD in the SSD. The data processing method of the embodiment of the present invention and the structure of the data control chip are described above. It can be seen that the data control chip of the embodiment of the present invention integrates the functions of PCI-E switching and RAID data processing, for example, as described above. The data control chip and the front-end interface chip and the SSD are all connected through a PCI-E interface, and the chip can also perform address conversion, data protection, and the like between the first address information and the second address information.

After the above PCI-E switching and RAID data processing functions are integrated in the data control chip, the two functions are mutually supported in the specific implementation; for example, after RAID data processing involves address translation or data mirroring, etc. It is necessary to perform data transmission according to the translated address result or the mirrored data. The function module of the RAID data processing notifies the PCI-E exchange function module of the processing result, and the function module exchanged by the PCI-E is based on the above conversion. The subsequent address result or the mirrored data is transmitted in PCI-E mode.

Moreover, the functions of PCI-E switching and RAID data processing are integrated in the data control chip, which has the following advantages:

For example, since the functional modules of the PCI-E exchange and the functional modules of the RAID data processing are both located inside the data control chip and belong to the internal communication of the chip, the two can communicate and interact through the private transmission protocol, and the communication efficiency is high. Moreover, the way in which the two functional modules are located on two chips does not occupy the PCI-E switching function, so that the PCI-E switching function is all used for data transmission between the front-end interface chip and the SSD, which helps Improve data transmission efficiency (the two functional modules are located in two chips, the two chips must communicate through the PCI-E protocol, which will consume the switching function of the larger part of PCI-E, so that the front-end interface chip and The data transmission efficiency between SSDs is degraded).

For example, the functions of PCI-E switching and RAID data processing are integrated in the data control chip, and some functions or storage units can be shared, for example, a data buffer unit, a data calculation function, a debugging function, etc., that is, in the data control chip. A data cache unit can be set up, which can be used for both cache in PCI-E exchange and cache in RAID data processing. In this way, the data control chip is reduced in cost, hardware layout, power consumption, heat dissipation, and the like.

For example, the functions of PCI-E switching and RAID data processing are integrated in the data control chip, and the function expansion capability of the data control chip is also improved, so that the data control chip may encounter an application of the SSD for the PCI-E interface. The problem provides an opportunity to solve; for example, when the SSD of the PCI-E interface encounters a hot swap, if the data control chip stops abnormally, it can pass The function of RAID data processing has been improved to solve this problem; but if the chip has only PCI-E switching function, the above problem cannot be solved, which seriously affects the normal operation of the storage device.

Embodiment 5

The embodiment provides a solid state storage array controller, including: a front end interface chip, a solid state hard disk SSD, and a data control chip according to any of the present invention; the data control chip respectively communicates with the SSD and the front end through a PCI-E interface Interface chip communication connection.

For example, referring to FIG. 3, an optional solid-state storage array controller structure further includes: a mirrored SSD; the data control chip is communicably connected to the mirrored SSD through a PCI-E interface; A mirrored SSD for receiving mirrored copy data from the data control chip. The solid state storage array controller further includes: a memory; the data control chip is connected to the memory through a PCI-E interface; the memory is configured to receive first data from the front end interface chip, so that the data is controlled The chip acquires the first data from the memory and writes the SSD; or receives the second data read from the SSD from the data control chip, so that the front-end interface chip acquires the memory from the memory The second data is described.

It should be noted that FIG. 3 is only an optional solid-state storage array controller structure, and may be changed in specific implementation. For example, the data control chip shown in FIG. 3 is directly connected to the front-end interface chip, and may also be in data control. A PCI-E switch chip is disposed between the chip and the front-end interface chip, so that the front-end interface chip is connected to the data control chip through the PCI-E switch chip; in addition, the data control chip can also be connected to multiple PCI-E switch chips and the like. .

The solid state storage array controller of the embodiment improves the IOPS capability of the array controller by adapting the data control chip with the PCI-E interface, and adapts to the performance requirements of the SSD array; and, compared with the conventional array control The array controller of the embodiment integrates the PCI-E switching function and the array processing function, such as data protection processing, on one chip, that is, the data control chip, which greatly simplifies the structure of the array controller and simplifies the array controller. cost.

A person skilled in the art can understand that all or part of the steps of implementing the above method embodiments may be completed by using hardware related to program instructions, and the foregoing program may be stored in a computer readable storage medium, and the program is executed when executed. The method includes the steps of the foregoing method embodiments; and the foregoing storage medium includes: a medium that can store program codes, such as a ROM, a RAM, a magnetic disk, or an optical disk.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention, and not The invention is described in detail with reference to the foregoing embodiments, and those skilled in the art should understand that the technical solutions described in the foregoing embodiments may be modified, or some or all of the technical features may be modified. The equivalents are made without departing from the scope of the technical solutions of the embodiments of the present invention.

Claims

claims

1. A data processing method, characterized by including:

The data control chip obtains the first address information from the front-end interface chip, and the first address information is used to indicate the address where the first data is to be written or the address where the second data is to be read;

The data control chip obtains second address information according to the first address information, and the second address information is used to indicate the corresponding position of the first address information in the solid state drive SSD. The data control chip passes PCI Express ( PCI-E) interface is respectively connected to the SSD and front-end interface chip;

The data control chip transmits the first data or the second data between the front-end interface chip and the SSD corresponding to the second address information through the PCI-E interface, so that the data will be transferred from the front-end interface to the SSD corresponding to the second address information. The first data received by the chip is written into the SSD, or the second data is read from the SSD and transmitted to the front-end interface chip.

2. The data processing method according to claim 1, characterized in that the data control chip transmits the data between the front-end interface chip and the SSD corresponding to the second address information through the PCI-E interface. The first data or the second data include:

The data control chip sends the second address information to the front-end interface chip, so that the front-end interface chip uses the direct memory access DMA mode to access the second address through the PCI-E interface of the data control chip. The SSD corresponding to the address information writes the first data or reads the second data.

3. The data processing method according to claim 1, wherein the data control chip transmits the data between the front-end interface chip and the SSD corresponding to the second address information through the PCI-E interface. The first data or the second data include:

The data control chip obtains the first data from the memory connected to the data control chip, and writes the first data to the corresponding SSD according to the second address information. The first Data is transmitted from the front-end interface chip to the memory through the data control chip;

Alternatively, the data control chip reads the second data from the corresponding SSD according to the second address information, and transmits the second data to the memory connected to the data control chip, so that The front-end interface chip reads the second data from the memory through the data control chip.

4. The method according to any one of claims 1 to 3, characterized in that: the front end is connected Transmitting the first data or the second data between the port chip and the SSD corresponding to the second address information includes:

When the first data written to the SSD is transmitted through the data control chip, the data control chip mirrors the data and sends the mirrored data to a computer connected to the data control chip. Connected mirror SSD.

5. The method according to any one of claims 1 to 3, wherein the first data or the second data is transmitted between the front-end interface chip and the SSD corresponding to the second address information. Data, including:

When the first data written into the SSD is transmitted through the data control chip, the data control chip calculates verification information on the data and writes the verification information into the SSD. Checksum SSD.

6. A data control chip, characterized by including:

An information receiving unit, configured to obtain first address information from the front-end interface chip, where the first address information is used to represent the address where the first data is to be written or the address where the second data is to be read;

An information processing unit, configured to obtain second address information based on the first address information. The second address information is used to represent the position corresponding to the first address information in the solid state drive SSD. The data control chip passes PCI Express (PCI-E) interface is communicated with the SSD and front-end interface chip respectively;

A transmission control unit configured to transmit the first data or the second data between the front-end interface chip and the SSD corresponding to the second address information through the PCI-E interface, so that the data will be transmitted from the front-end interface to the SSD corresponding to the second address information. The first data received by the interface chip is written into the SSD, or the second data is read from the SSD and transmitted to the front-end interface chip.

7. The data control chip according to claim 6, characterized in that,

The transmission control unit is specifically configured to send the second address information to the front-end interface chip, so that the front-end interface chip uses a direct memory access DMA mode through the PCI-E interface of the data control chip. The SSD corresponding to the second address information writes the first data or reads the second data.

8. The data control chip according to claim 6, characterized in that,

The transmission control unit is specifically configured to obtain the first data from the memory connected to the data control chip, and write the first data into the corresponding address according to the second address information. SSD, the first data is transmitted by the front-end interface chip to the memory through the data control chip;

Or, read the second data from the corresponding SSD according to the second address information, and transfer the second data to the memory connected to the data control chip, so that the front-end interface chip The second data is read from the memory through the data control chip.

9. The data control chip according to any one of claims 6 to 8, further comprising: a mirror protection unit, configured to transmit the first data written to the SSD through the data control chip At this time, the data control chip mirrors the data and sends the mirrored data to the mirror SSD connected to the data control chip.

10. The data control chip according to any one of claims 6 to 8, further comprising: a verification protection unit, configured to transmit the first data written to the SSD through the data control When the chip is connected, the data control chip calculates verification information on the data, and writes the verification information into the verification SSD in the SSD.

11. A solid-state storage array controller, characterized in that it includes: a front-end interface chip, a solid-state drive SSD, and the data control chip described in any one of claims 6 to 10;

The data control chip communicates with the SSD and front-end interface chip respectively through the PCI-E interface.

12. The solid-state storage array controller according to claim 11, further comprising: a mirror SSD; the data control chip is communicatively connected to the mirror SSD through a PCI-E interface; the mirror SSD is used for Receive mirrored data from the data control chip.

13. The solid-state storage array controller according to claim 11, further comprising: a memory; the data control chip is connected to the memory through a PCI-E interface;

The memory is configured to receive the first data from the front-end interface chip, so that the data control chip obtains the first data from the memory and writes it to the SSD; or, receives the first data from the data control chip. The second data read by the SSD allows the front-end interface chip to obtain the second data from the memory.