CN101534108A - Non-overlapping clock-generating circuit with independently regulated two-phase pulse duration - Google Patents

Abstract

A non-overlapping clock generation circuit that independently adjusts two-phase pulse widths belongs to the field of non-overlapping clock generation circuits, and is characterized in that it contains: there is a delay before CLK2 of the two-phase non-overlapping clock generation circuit that can generate advance clocks Timing unit, its input is connected to the input clock signal, and its output is connected to an input terminal CLK2 of the NAND gate. The delay unit can be used to independently adjust the pulse width of PH1 and PH2. When the parameters satisfy T _D ≤ _{T D1} +T _D2 , the pulse width of the clock PH1 is T/2-T _D2 -T _D , and the pulse width of the clock PH2 is T/2-T _D2 +T _D . The non-overlapping time between PH1 and PH2 is T _D2 . Clock PH1E falls by T _D2 before PH1 , and clock PH2E falls by T _D2 before PH2 . When T _D1 = T _D2 , PH1E and PH1 can be raised at the same time, and PH2E and PH2 can be raised at the same time. The invention has the advantages that the pulse width and non-overlapping time of the two-phase non-overlapping clocks can be adjusted in advance of the rising edge of the clock.

Description

A non-overlapping clock generation circuit that independently adjusts two-phase pulse widths

technical field

The invention belongs to the design of ultra-large-scale integrated circuits in the field of microelectronics and solid-state electronics, and relates to a new type of two-phase non-overlapping clock generation circuit, which can be widely used in ΔΣ modulators, pipeline A/D, filters and other switches Capacitor circuit design.

Background technique

The two-phase non-overlapping clock generation circuit is one of the important unit modules of the analog circuit, and is widely used in various switched capacitor circuits. The two-phase non-overlapping clock is used to control the on-off of the switch in the circuit, so that the node is not driven by two voltage sources at the same time. It also provides an early shutdown clock to reduce the impact of signal-related charge injection effects.

In a switched capacitor circuit, the sampling capacitance is usually reduced step by step, and the load capacitance is not equal in the two-phase clock, and the integral phase will be larger than the sampling phase. The tasks assigned in the two-phase clock are also different, such as the ΔΣ modulator of the feedforward structure, the task of the sampling phase is obviously lighter than that of the integral phase. Non-overlapping clocks with two-phase unequal pulse widths can reasonably allocate the two-phase time to achieve the purpose of optimizing power consumption.

The clock requirements of the switched capacitor circuit are as follows:

1. The clock PH1 does not overlap with the clocks PH2 and PH2E.

2. The clock PH2 does not overlap with the clocks PH1 and PH1E.

3. Clock PH1E falls earlier than clock PH1, and PH1E and PH1 rise simultaneously.

4. Clock PH2E falls earlier than clock PH2, and PH2E and PH2 rise simultaneously.

At present, the simplest two-phase non-overlapping clock structure is shown in FIG. 5 . The pulse width of the clock PH1 is T/2-T _DLY2 , and the pulse width of the clock PH2 is T/2-T _DLY1 . The non-overlapping time from the falling edge of PH2 to the rising edge of PH1 is T _DLY1 , and the non-overlapping time from the falling edge of PH1 to the rising edge of PH2 is T _DLY2 . Although the pulse width is adjustable, it is related to the non-overlapping time, and it cannot generate clocks PH1E and PH2E that meet requirements 3 and 4.

In order to produce clocks PH1E and PH2E that meet requirements 3 and 4, the researchers later proposed a clock generation circuit with the structure shown in Figure 6. It is obtained that the pulse width of PH1 is T/2-T _DLY12 -T _DLY22 +T _DLY11 , and the pulse width of PH2 is T/2-T _DLY11 -T _DLY21 +T _DLY12 . The non-overlapping time from the falling edge of PH2 to the rising edge of PH1 is T _DLY21 , and the non-overlapping time from the falling edge of PH1 to the rising edge of PH2 is T _DLY22 . If T _DLY11 =T _DLY21 , the PH1E can meet the requirement of 3. If T _DLY12 =T _DLY22 , then the PH2E can meet the requirements of 4. But its disadvantage is also that the pulse width is related to the non-overlap time. Increasing the pulse width of the clock PH2 requires increasing T _DLY12 , T _DLY12 =T _DLY22 , which is at the cost of increasing the non-overlap time.

In view of this situation, the present invention provides a non-overlapping clock generation circuit that independently adjusts the two-phase pulse widths.

Contents of the invention

The object of the present invention is to provide a non-overlapping clock generation circuit capable of independently adjusting two-phase pulse widths that overcomes the above disadvantages.

The present invention is characterized in that it contains: 7 inverters B1, B2, B3, B4, B5, B6, B7, 2 NAND gates G1, G2, 2 PMOS transistors M1, M2, 4 NMOS transistors N1, N2, N3, N4 and 5 delay circuits DLY1, DLY2, DLY3, DLY4, DLY5:

The input terminal of the first inverter B1 and the input terminal of the third delay unit DLY3 are connected to the input clock CLK.

The first NAND gate G1 is provided with two input terminals, respectively connected to the output terminal CLK1 of the first inverter B1 and the output terminal of the fifth inverter B5, and is also provided with an output terminal , the output terminal is simultaneously connected to the input terminal of the first delay circuit DLY1, the gate of the first PMOS transistor M1 and the gate of the first NMOS transistor N1,

The second NAND gate G2 is provided with two input terminals, respectively connected to the output terminal CLK2 of the third delay unit DLY3 and the output terminal of the third inverter B3, and is also provided with an output terminal , the output terminal is simultaneously connected to the input terminal of the second delay circuit DLY2, the gate of the second PMOS transistor M2 and the gate of the fourth NMOS transistor N4,

The first delay circuit DLY1 is provided with an output terminal connected to the gate of the second NMOS transistor N2 and also connected to the input terminal of the second inverter B2, the second inverter B2 The output of the first non-overlapping advance clock PH1E,

The second delay circuit DLY2 is provided with an output end connected to the gate of the third NMOS transistor N3 and also connected to the input end of the seventh inverter B7, the seventh inverter B7 The output of the second non-overlapping advance clock PH2E,

The source of the first PMOS transistor M1 is connected to the power supply, the drain is connected to the source of the first NMOS transistor N1 and then connected to the input terminal of the fourth delay circuit DLY4, and the first NMOS transistor N1 The drain of the second NMOS transistor N2 is connected to the source, and the drain of the second NMOS transistor N2 is grounded,

The source of the second PMOS transistor M2 is connected to the power supply, the drain is connected to the source of the fourth NMOS transistor N4 and then connected to the input terminal of the fifth delay circuit DLY5, and the fourth NMOS transistor N4 The drain of the third NMOS transistor N3 is connected to the source, and the drain of the third NMOS transistor N3 is grounded,

The output terminal of the fourth delay circuit DLY4 is connected to the input terminal of the third inverter B3, and the output terminal of the third inverter B3 is connected to the input terminal of the fourth inverter B4, The output terminal of the fourth inverter B4 outputs the first non-overlapping clock PH1,

The output terminal of the fifth delay circuit DLY5 is connected to the input terminal of the fifth inverter B5, and the output terminal of the fifth inverter B5 is connected to the input terminal of the sixth inverter B6, The output terminal of the sixth inverter B6 outputs the second non-overlapping clock PH2,

When the delay T _D of the third delay circuit DLY3, the delay T D1 of the first delay circuit DLY1 or the second delay circuit DLY2, and the delay of the fourth delay circuit _DLY4 or the fifth delay circuit DLY5 When T _D2 satisfies the condition T _D <= T _D1 +T _D2 ,

The pulse width of the two-phase non-overlapping clock PH1 is: T/2-T _D2 -T _D ,

The pulse width of the two-phase non-overlapping clock PH2 is: T/2-T _D2 +T _D ,

The non-overlapping time of the two-phase non-overlapping clocks PH1 and PH2 is: T _D2 ,

The two-phase non-overlapping advance clock PH1E rising edge arrival time - PH1 rising edge arrival time = T _D1 - T _D2 , the PH1E falling edge is earlier than the PH1 falling edge T _D2 ,

The two-phase non-overlapping advance clock PH2E rising edge arrival time - PH2 rising edge arrival time = T _D1 - T _D2 , and the PH2E falling edge is earlier than the PH2 falling edge T _D2 ,

where T is the period of the input 50% duty cycle clock.

The invented non-overlapping clock generating circuit capable of independently adjusting two-phase pulse widths overcomes the disadvantage of changing the non-overlapping time of the two-phase non-overlapping clock generating circuit capable of generating advance clocks by adding a delay unit to adjust the pulse width. The effective working range of the delay parameter setting of the delay unit DLY of this circuit is: T _D <= T _D1 + T _D2 . Assuming that the non-overlapping time is chosen to be 1/20 of the clock period, the PH2 phase clock can borrow up to 20% of the original time of the PH1 phase clock without any impact on other parameters.

Description of drawings

Fig. 1 is a schematic diagram of a non-overlapping clock generating circuit capable of independently adjusting two-phase pulse widths of the present invention.

Fig. 2. The timing diagram of the circuit of the present invention when the parameter T _D <= T _D1 + T _D2 .

Fig. 3. Timing diagram of the circuit of the present invention when parameters T _D1 +T _D2 <T _D <T/2-2*T _D1 -T _D2 .

Fig. 4. The timing diagram of the circuit of the present invention when the parameter T _D >= T/2-2*T _D1 -T _D2 .

Figure 5. The simplest two-phase non-overlapping clock generation circuit.

Figure 6. Schematic diagram of the improved two-phase non-overlapping clock generation circuit that can generate PH1E and PH2E

Detailed ways

Technical solution of the present invention refers to Fig. 1. Figure 1 is a structural diagram of a non-overlapping clock generation circuit that independently adjusts two-phase pulse widths.

When the delay parameter T _D <= T _D1 + T _D2 , the time sequence is shown in Fig. 2 .

The pulse width of the clock PH1 phase is: T/2-T _D2 -T _D .

The pulse width of the PH2 phase of the clock is: T/2-T _D2 +T _D .

The non-overlapping time between the two phases of the clock PH1 and the PH2 phase is: T _D2 .

Arrival time of rising edge of clock PH1E - arrival time of rising edge of PH1 = T _D1 - _{T D2} .

Arrival time of rising edge of clock PH2E - arrival time of rising edge of PH2 = T _D1 - _{T D2} .

The falling edge of clock PH1E arrives at T _D2 before the falling edge of PH1.

The falling edge of clock PH2E arrives at T _D2 before the falling edge of PH2.

where T is the clock period with a 50% duty cycle of the input.

When T _D1 =T _D2 , the clocks PH1E and PH1 can rise simultaneously, and the clocks PH2E and PH2 can rise simultaneously.

When the delay parameter T _D1 +T _D2 <T _D <T/2-2*T _D1 -T _D2 , the time sequence is shown in Figure 3.

The pulse width of clock PH1 is T/2-T _D2 -T _D , the pulse width of clock PH2 is T/2+T _D1 , and the non-overlapping time between PH1 and PH2 is T _D2 and T _D -T _D1 respectively. The increased delay T _D is used to increase the non-overlapping time and shorten the PH1 pulse width, which does not help to extend the PH2 pulse width, so the delay of the DLY unit should not exceed T _D1 + T _D2 .

When the delay parameter T _D >=T/2-2*T _D1 -T _D2 , the time sequence is shown in FIG. 4 .

The increased delay DLY is used to increase the non-overlap time and shorten the pulse width of PH1, which does not help the extension of the pulse width of PH2, and PH1E is no longer turned off earlier than PH1. Therefore, the delay of the DLY unit cannot exceed T/2-2*T _D1 -T _D2 .

Claims (1)

1. the clock generation circuit that do not overlap of an independent regulation two-phase pulsewidth is characterized in that, contains: 7 inverters (B1, B2, B3, B4, B5, B6, B7), 2 NAND gate (G1, G2), 2 PMOS pipes (M1, M2), 4 NMOS pipes (N1, N2, N3, N4) and 5 delay circuits (DLY1, DLY2, DLY3, DLY4, DLY5):

The input of described first inverter (B1) is connected input clock CLK with the input of described the 3rd delay unit (DLY3).

Described first NAND gate (G1), be provided with two inputs, link to each other with the output (CLK1) of described first inverter (B1), the output of described the 5th inverter (B5) respectively, also be provided with an output, this output is connected to the grid of the input of described first delay circuit (DLY1), described PMOS pipe (M1) and the grid of described NMOS pipe (N1) simultaneously

Described second NAND gate (G2), be provided with two inputs, link to each other with the output (CLK2) of described the 3rd delay unit (DLY3), the output of described the 3rd inverter (B3) respectively, also be provided with an output, this output is connected to the grid of the input of described second delay circuit (DLY2), described the 2nd PMOS pipe (M2) and the grid of described the 4th NMOS pipe (N4) simultaneously

Described first delay circuit (DLY1), be provided with an output, be connected to the grid of described the 2nd NMOS pipe (N2), be also connected to the input of described second inverter (B2), the output of this second inverter (B2) is exported first clock (PH1E) in advance that do not overlap

Described second delay circuit (DLY2), be provided with an output, be connected to the grid of described the 3rd NMOS pipe (N3), be also connected to the input of described the 7th inverter (B7), second of the output output of the 7th inverter (B7) does not overlap and shifts to an earlier date clock (PH2E)

Described PMOS pipe (M1), source electrode connects power supply, after being connected, the source electrode that drain electrode and a described NMOS manage (N1) links to each other with the input of described the 4th delay circuit (DLY4) again, and the drain electrode of NMOS pipe (N1) links to each other with the source electrode that described the 2nd NMOS manages (N2), and the grounded drain of the 2nd NMOS pipe (N2)

Described the 2nd PMOS pipe (M2), source electrode connects power supply, after being connected, the source electrode that drain electrode and described the 4th NMOS manage (N4) links to each other with the input of described the 5th delay circuit (DLY5) again, and the drain electrode of the 4th NMOS pipe (N4) links to each other with the source electrode that described the 3rd NMOS manages (N3), and the grounded drain of the 3rd NMOS pipe (N3)

Described the 4th delay circuit (DLY4), output links to each other with the input of described the 3rd inverter (B3), and the output of the 3rd inverter (B3) is connected to the input of described the 4th inverter (B4), and the output of the 4th inverter (B4) is exported first clock (PH1) that do not overlap

Described the 5th delay circuit (DLY5), output links to each other with the input of described the 5th inverter (B5), and the output of the 5th inverter (B5) is connected to the input of described hex inverter (B6), second clock (PH2) that do not overlap of output output of this hex inverter (B6)

Time-delay T when described the 3rd delay circuit (DLY3) _D, first delay circuit (DLY1) or second delay circuit (DLY2) time-delay T _D1, and the time-delay T of the 4th delay circuit (DLY4) or the 5th delay circuit (DLY5) _D2T satisfies condition _D＜=T _D1+ T _D2The time,

The described two-phase clock PH1 pulse duration that do not overlap is: T/2-T _D2-TD,

The described two-phase clock PH2 pulse duration that do not overlap is: T/2-T _D2+ TD,

Described two-phase does not overlap, and the overlapping time is not: T for clock PH1 and PH2 _D2,

Described two-phase clock PH1E rising edge time of advent-PH1 rising edge time=T that arrives that do not overlap in advance _D1-T _D2, the PH1E trailing edge is prior to PH1 trailing edge T _D2,

Described two-phase clock PH2E rising edge time of advent-PH2 rising edge time=T that arrives that do not overlap in advance _D1-T _D2, the PH2E trailing edge is prior to PH2 trailing edge T _D2,

Wherein T is the cycle of input 50% duty cycle clock.

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