CN101534108A - Non-overlapping clock-generating circuit with independently regulated two-phase pulse duration - Google Patents
Non-overlapping clock-generating circuit with independently regulated two-phase pulse duration Download PDFInfo
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Abstract
The invention relates to a non-overlapping clock-generating circuit with independently regulated two-phase pulse duration, belonging to the field of non-overlapping clock-generating circuit. The circuit is characterized in that a time delay unit is provided in front of CLK2 of two-phase non-overlapping clock-generating circuit which can generate advance timing, the input of the time delay unit is connected with clock signals, the output thereof is connected with an input terminal CKL2 of an alternative denial gate; the time delay unit can be used to independently regulate the pulse duration of PH1 and PH2. When parameters meet the condition that TD is less than or equal to TD1+TD2, PH1 pulse duration of the clock is T/2-TD2-TD, PH2 pulse duration of the clock is T/2-TD2+TD; non-overlapping time between PH1 and PH2 is TD2; clock PH1E falls by TD2 earlier than PH1does, clock PH2E falls by TD2 earlier than PH2 does; when TD1 is equal to TD2, PH1E and PH1 can rise simultaneously, so do PH2E AND PH2. The circuit of the invention has the advantage that pulse duration, non-overlapping time and advance timing rising edge of the two-phase non-overlapping clock can be adjusted.
Description
Technical field
The invention belongs to the VLSI (very large scale integrated circuit) designs in Microelectronics and Solid State Electronics field, relate to a kind of novel two-phase clock generation circuit that do not overlap, can be widely used in Δ ∑ modulator, assembly line A/D, the design of switched-capacitor circuits such as filter.
Background technology
The two-phase clock generation circuit that do not overlap is one of significant element module of analog circuit, is widely used in the various switched-capacitor circuits.The two-phase clock that do not overlap is used for the break-make of control circuit switch, makes node not be subjected to the driving of two voltage sources at synchronization.And provide and turn-off clock in advance, reduce influence with the electric charge injection effect of signal correction.
Because sampling capacitance step by step dwindle, load capacitance two phase clock in also unequal, meet than sampling mutually big usually by integration for switched-capacitor circuit.The task of distributing in two phase clock is also inequality, the Δ ∑ modulator of feed forward architecture for example, and the obvious specific volume phase-splitting of task of sampling phase is light.Two-phase does not wait the clock that do not overlap of pulsewidth can the reasonable distribution two-phase time, reaches the purpose of optimizing power consumption.
Switched-capacitor circuit to clock require as follows:
1. clock PH1 and clock PH2, PH2E do not overlap.
2. clock PH2 and clock PH1, PH1E do not overlap.
3. clock PH1E descends in advance than clock PH1, and PH1E and PH1 rise simultaneously.
4. clock PH2E descends in advance than clock PH2, and PH2E and PH2 rise simultaneously.
And the simplest two-phase does not overlap timing topology as shown in Figure 5 at present.The pulse duration of clock PH1 is T/2-T
DLY2, the pulse duration of clock PH2 is T/2-T
DLY1The PH2 trailing edge to the not overlapping time of PH1 rising edge be T
DLY1, the PH1 trailing edge to the not overlapping time of PH2 rising edge be T
DLY2Though pulsewidth is adjustable, relevant with the time that do not overlap, and it can not produce meet the demands 3,4 clock PH1E and PH2E.
Be generation meet the demands 3,4 clock PH1E and PH2E, the researcher had proposed the clock generation circuit of structure shown in Figure 6 again afterwards.The pulsewidth that obtains PH1 is T/2-T
DLY12-T
DLY22+ T
DLY11, the pulsewidth of PH2 is T/2-T
DLY11-T
DLY21+ T
DLY12The PH2 trailing edge to the not overlapping time of PH1 rising edge be T
DLY21, the PH1 trailing edge to the not overlapping time of PH2 rising edge be T
DLY22If T
DLY11=T
DLY21, can make PH1E satisfy 3 requirement.If T
DLY12=T
DLY22, can make PH2E satisfy 4 requirement.But its shortcoming also is the pulsewidth and the time correlation that do not overlap.Increase clock PH2 pulsewidth and need increase T
DLY12, T
DLY12=T
DLY22, overlapping time is cost to increase not for this.
At this situation, the invention provides a kind of clock generation circuit that do not overlap of independent regulation two-phase pulsewidth.
Summary of the invention
The object of the present invention is to provide the clock generation circuit that do not overlap of the independent regulation two-phase pulsewidth that can overcome above-mentioned shortcoming.
The invention is characterized in, contain: 7 inverter B1, B2, B3, B4, B5, B6, B7,2 NAND gate G1, G2,2 PMOS pipes M1, M2,4 NMOS pipes N1, N2, N3, N4 and 5 delay circuit DLY1, DLY2, DLY3, DLY4, DLY5:
The input of the input of the described first inverter B1 and described the 3rd delay unit DLY3 is connected input clock CLK.
The described first NAND gate G1, be provided with two inputs, link to each other with the output CLK1 of the described first inverter B1, the output of described the 5th inverter B5 respectively, also be provided with an output, this output is connected to the grid of the input of the described first delay circuit DLY1, described PMOS pipe M1 and the grid of described NMOS pipe N1 simultaneously
The described second NAND gate G2, be provided with two inputs, link to each other with the output CLK2 of described the 3rd delay unit DLY3, the output of described the 3rd inverter B3 respectively, also be provided with an output, this output is connected to the grid of the input of the described second delay circuit DLY2, described the 2nd PMOS pipe M2 and the grid of described the 4th NMOS pipe N4 simultaneously
The described first delay circuit DLY1 is provided with an output, is connected to the grid of described the 2nd NMOS pipe N2, is also connected to the input of the described second inverter B2, and the output of this second inverter B2 is exported first clock PH1E in advance that do not overlap,
The described second delay circuit DLY2 is provided with an output, is connected to the grid of described the 3rd NMOS pipe N3, is also connected to the input of described the 7th inverter B7, and second of the output output of the 7th inverter B7 does not overlap and shifts to an earlier date clock PH2E,
Described PMOS pipe M1, source electrode connects power supply, drain electrode with link to each other with the input of described the 4th delay circuit DLY4 again after the source electrode of described NMOS pipe N1 is connected, and a NMOS manages the drain electrode of N1 and links to each other with the source electrode that described the 2nd NMOS manages N2, and the grounded drain of the 2nd NMOS pipe N2
Described the 2nd PMOS pipe M2, source electrode connects power supply, drain electrode with link to each other with the input of described the 5th delay circuit DLY5 again after the source electrode of described the 4th NMOS pipe N4 is connected, and the 4th NMOS manages the drain electrode of N4 and links to each other with the source electrode that described the 3rd NMOS manages N3, and the grounded drain of the 3rd NMOS pipe N3
Described the 4th delay circuit DLY4, output links to each other with the input of described the 3rd inverter B3, and the output of the 3rd inverter B3 is connected to the input of described the 4th inverter B4, the output of the 4th inverter B4 is exported first clock PH1 that do not overlap,
Described the 5th delay circuit DLY5, output links to each other with the input of described the 5th inverter B5, and the output of the 5th inverter B5 is connected to the input of described hex inverter B6, second clock PH2 that do not overlap of output output of this hex inverter B6,
Time-delay T as described the 3rd delay circuit DLY3
D, the first delay circuit DLY1 or the second delay circuit DLY2 time-delay T
D1, and the time-delay T of the 4th delay circuit DLY4 or the 5th delay circuit DLY5
D2T satisfies condition
D＜=T
D1+ T
D2The time,
The described two-phase clock PH1 pulse duration that do not overlap is: T/2-T
D2-T
D,
The described two-phase clock PH2 pulse duration that do not overlap is: T/2-T
D2+ T
D,
Described two-phase does not overlap, and the overlapping time is not: T for clock PH1 and PH2
D2,
Described two-phase clock PH1E rising edge time of advent-PH1 rising edge time=T that arrives that do not overlap in advance
D1-T
D2, the PH1E trailing edge is prior to PH1 trailing edge T
D2,
Described two-phase clock PH2E rising edge time of advent-PH2 rising edge time=T that arrives that do not overlap in advance
D1-T
D2, the PH2E trailing edge is prior to PH2 trailing edge T
D2,
Wherein T is the cycle of input 50% duty cycle clock.
But the clock generation circuit that do not overlap of the independent regulation two-phase pulsewidth of invention can produce the clock generation circuit regulating impulse width that do not overlap of the two-phase of clock in advance and need change the shortcoming of the time of not overlapping by adding a delay unit, having overcome.The delay parameter of this circuit delay cells D LY is provided with efficient working range and is: T
D＜=T
D1+ T
D2Suppose to select not that the overlapping time is 1/20 of the clock cycle, then PH2 phase clock maximum can be used 20% of original time of PH1 phase clock, and to other parameters without any influence.
Description of drawings
But Fig. 1. the clock generation circuit schematic diagram that do not overlap of independent regulation two-phase pulsewidth of the present invention.
Fig. 2. circuit of the present invention is at parameter T
D＜=T
D1+ T
D2The time sequential chart.
Fig. 3. circuit of the present invention is at parameter T
D1+ T
D2＜T
D＜T/2-2*T
D1-T
D2The time sequential chart.
Fig. 4. circuit of the present invention is at parameter T
D〉=T/2-2*T
D1-T
D2The time sequential chart.
Fig. 5. the simplest two-phase clock generation circuit that do not overlap.
Fig. 6. the two-phase that modified model can produce PH1E and the PH2E clock generation circuit schematic diagram that do not overlap
Embodiment
Technical solution of the present invention is consulted Fig. 1.Fig. 1 is the clock generation circuit structure chart that do not overlap of independent regulation two-phase pulsewidth.
As delay parameter T
D＜=T
D1+ T
D2The time, sequential is as shown in Figure 2.
Clock PH1 phase pulse duration is: T/2-T
D2-T
D
Clock PH2 phase pulse duration is: T/2-T
D2+ T
D
Two-phase does not overlap, and the overlapping time is not clock PH1 mutually: T with PH2
D2
Clock PH1E rising edge time of advent-PH1 rising edge time=T that arrives
D1-T
D2
Clock PH2E rising edge time of advent-PH2 rising edge time=T that arrives
D1-T
D2
Clock PH1E trailing edge is prior to PH1 trailing edge arrival T
D2
Clock PH2E trailing edge is prior to PH2 trailing edge arrival T
D2
Wherein T is the clock cycle of input duty cycle 50%.
Work as T
D1=T
D2The time, clock PH1E and PH1 are risen simultaneously, clock PH2E and PH2 rise simultaneously.
As delay parameter T
D1+ T
D2＜T
D＜T/2-2*T
D1-T
D2The time, sequential is as shown in Figure 3.
Clock PH1 pulsewidth is T/2-T
D2-T
D, clock PH2 pulsewidth is T/2+T
D1, the overlapping time is not respectively T for PH1 and PH2
D2And T
D-T
D1The time-delay T that increases
DAll be used for increasing and do not overlap the time, shorten the PH1 pulsewidth, without any help, so the time-delay of DLY unit should not surpass T to the prolongation of PH2 pulsewidth
D1+ T
D2
As delay parameter T
D〉=T/2-2*T
D1-T
D2The time, sequential is as shown in Figure 4.
The time-delay DLY that increases is used for increasing and does not overlap the time, shortens the PH1 pulsewidth, and without any help, and PH1E also no longer turn-offs early than PH1 to the prolongation of PH2 pulsewidth.Therefore the time-delay of DLY unit can not surpass T/2-2*T
D1-T
D2
Claims (1)
1. the clock generation circuit that do not overlap of an independent regulation two-phase pulsewidth is characterized in that, contains: 7 inverters (B1, B2, B3, B4, B5, B6, B7), 2 NAND gate (G1, G2), 2 PMOS pipes (M1, M2), 4 NMOS pipes (N1, N2, N3, N4) and 5 delay circuits (DLY1, DLY2, DLY3, DLY4, DLY5):
The input of described first inverter (B1) is connected input clock CLK with the input of described the 3rd delay unit (DLY3).
Described first NAND gate (G1), be provided with two inputs, link to each other with the output (CLK1) of described first inverter (B1), the output of described the 5th inverter (B5) respectively, also be provided with an output, this output is connected to the grid of the input of described first delay circuit (DLY1), described PMOS pipe (M1) and the grid of described NMOS pipe (N1) simultaneously
Described second NAND gate (G2), be provided with two inputs, link to each other with the output (CLK2) of described the 3rd delay unit (DLY3), the output of described the 3rd inverter (B3) respectively, also be provided with an output, this output is connected to the grid of the input of described second delay circuit (DLY2), described the 2nd PMOS pipe (M2) and the grid of described the 4th NMOS pipe (N4) simultaneously
Described first delay circuit (DLY1), be provided with an output, be connected to the grid of described the 2nd NMOS pipe (N2), be also connected to the input of described second inverter (B2), the output of this second inverter (B2) is exported first clock (PH1E) in advance that do not overlap
Described second delay circuit (DLY2), be provided with an output, be connected to the grid of described the 3rd NMOS pipe (N3), be also connected to the input of described the 7th inverter (B7), second of the output output of the 7th inverter (B7) does not overlap and shifts to an earlier date clock (PH2E)
Described PMOS pipe (M1), source electrode connects power supply, after being connected, the source electrode that drain electrode and a described NMOS manage (N1) links to each other with the input of described the 4th delay circuit (DLY4) again, and the drain electrode of NMOS pipe (N1) links to each other with the source electrode that described the 2nd NMOS manages (N2), and the grounded drain of the 2nd NMOS pipe (N2)
Described the 2nd PMOS pipe (M2), source electrode connects power supply, after being connected, the source electrode that drain electrode and described the 4th NMOS manage (N4) links to each other with the input of described the 5th delay circuit (DLY5) again, and the drain electrode of the 4th NMOS pipe (N4) links to each other with the source electrode that described the 3rd NMOS manages (N3), and the grounded drain of the 3rd NMOS pipe (N3)
Described the 4th delay circuit (DLY4), output links to each other with the input of described the 3rd inverter (B3), and the output of the 3rd inverter (B3) is connected to the input of described the 4th inverter (B4), and the output of the 4th inverter (B4) is exported first clock (PH1) that do not overlap
Described the 5th delay circuit (DLY5), output links to each other with the input of described the 5th inverter (B5), and the output of the 5th inverter (B5) is connected to the input of described hex inverter (B6), second clock (PH2) that do not overlap of output output of this hex inverter (B6)
Time-delay T when described the 3rd delay circuit (DLY3)
D, first delay circuit (DLY1) or second delay circuit (DLY2) time-delay T
D1, and the time-delay T of the 4th delay circuit (DLY4) or the 5th delay circuit (DLY5)
D2T satisfies condition
D＜=T
D1+ T
D2The time,
The described two-phase clock PH1 pulse duration that do not overlap is: T/2-T
D2-TD,
The described two-phase clock PH2 pulse duration that do not overlap is: T/2-T
D2+ TD,
Described two-phase does not overlap, and the overlapping time is not: T for clock PH1 and PH2
D2,
Described two-phase clock PH1E rising edge time of advent-PH1 rising edge time=T that arrives that do not overlap in advance
D1-T
D2, the PH1E trailing edge is prior to PH1 trailing edge T
D2,
Described two-phase clock PH2E rising edge time of advent-PH2 rising edge time=T that arrives that do not overlap in advance
D1-T
D2, the PH2E trailing edge is prior to PH2 trailing edge T
D2,
Wherein T is the cycle of input 50% duty cycle clock.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100818989A CN101534108B (en) | 2009-04-14 | 2009-04-14 | Non-overlapping clock-generating circuit with independently regulated two-phase pulse duration |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2009100818989A CN101534108B (en) | 2009-04-14 | 2009-04-14 | Non-overlapping clock-generating circuit with independently regulated two-phase pulse duration |
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|---|---|
| CN101534108A true CN101534108A (en) | 2009-09-16 |
| CN101534108B CN101534108B (en) | 2011-05-11 |
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| CN101783582A (en) * | 2010-02-26 | 2010-07-21 | 东南大学 | Single-input dual-output pulse-width modulation signal generating circuit with adjustable dead time |
| CN102082574A (en) * | 2011-03-11 | 2011-06-01 | 苏州易能微电子科技有限公司 | Switch capacitive circuit for asymmetric clock |
| CN102412811A (en) * | 2012-01-06 | 2012-04-11 | 桂林电子科技大学 | Adjustable non-overlapping clock signal generating method and generator |
| CN102545880A (en) * | 2011-12-22 | 2012-07-04 | 苏州云芯微电子科技有限公司 | Clock signal phase inverter with adjustable duty ratio and intersection point position |
| CN103439585A (en) * | 2013-08-23 | 2013-12-11 | 华东师范大学 | Measuring circuit of integrated circuit interconnecting wire stray capacitance and measuring method thereof |
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| US4953187A (en) * | 1989-01-23 | 1990-08-28 | Motorola, Inc. | High speed prescaler |
| US5444405A (en) * | 1992-03-02 | 1995-08-22 | Seiko Epson Corporation | Clock generator with programmable non-overlapping clock edge capability |
| CN100568728C (en) * | 2005-10-31 | 2009-12-09 | 中兴通讯股份有限公司 | A kind of clock signal detection circuit |
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2009
- 2009-04-14 CN CN2009100818989A patent/CN101534108B/en not_active Expired - Fee Related
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| CN101783582A (en) * | 2010-02-26 | 2010-07-21 | 东南大学 | Single-input dual-output pulse-width modulation signal generating circuit with adjustable dead time |
| CN101783582B (en) * | 2010-02-26 | 2012-08-15 | 东南大学 | Single-input dual-output pulse-width modulation signal generating circuit with adjustable dead time |
| CN102082574A (en) * | 2011-03-11 | 2011-06-01 | 苏州易能微电子科技有限公司 | Switch capacitive circuit for asymmetric clock |
| CN102545880A (en) * | 2011-12-22 | 2012-07-04 | 苏州云芯微电子科技有限公司 | Clock signal phase inverter with adjustable duty ratio and intersection point position |
| CN102545880B (en) * | 2011-12-22 | 2014-07-02 | 苏州云芯微电子科技有限公司 | Clock signal phase inverter with adjustable duty ratio and intersection point position |
| CN102412811A (en) * | 2012-01-06 | 2012-04-11 | 桂林电子科技大学 | Adjustable non-overlapping clock signal generating method and generator |
| CN102412811B (en) * | 2012-01-06 | 2013-11-20 | 桂林电子科技大学 | Adjustable non-overlapping clock signal generating method and generator |
| CN103439585A (en) * | 2013-08-23 | 2013-12-11 | 华东师范大学 | Measuring circuit of integrated circuit interconnecting wire stray capacitance and measuring method thereof |
| CN106130540A (en) * | 2016-07-05 | 2016-11-16 | 中国科学院上海微系统与信息技术研究所 | Broad-adjustable disjoint signals circuit and system |
| CN109302179A (en) * | 2018-09-03 | 2019-02-01 | 重庆西南集成电路设计有限责任公司 | Dual mode charge pump circuit and mode selection circuit and sample logic Circuit with tolerance |
| CN109302179B (en) * | 2018-09-03 | 2022-04-19 | 重庆西南集成电路设计有限责任公司 | Dual mode charge pump circuit and mode selection circuit and sampling logic tolerance circuit |
| CN112511140A (en) * | 2020-12-02 | 2021-03-16 | 清华大学 | High-voltage level shifting double-narrow pulse generating circuit capable of on-chip gating and fine tuning |
| CN113271702A (en) * | 2021-05-07 | 2021-08-17 | 华润微集成电路(无锡)有限公司 | Self-adaptive adjusting three-channel color lamp LED constant current driving circuit and method |
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| CN113285733A (en) * | 2021-07-26 | 2021-08-20 | 成都华兴大地科技有限公司 | Driving circuit for radio frequency transceiving |
| CN113285733B (en) * | 2021-07-26 | 2021-09-24 | 成都华兴大地科技有限公司 | Driving circuit for radio frequency transceiving |
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