CN101533845A - Photoelectric detector based on double control gate MOSFET structure - Google Patents

Abstract

The invention provides a detector with a double control gate MOSFET. The structure of each unit of the detector is that: two sides of the upper part of a P-type semiconductor silicon material on a substrate are provided with heavily doped N-type semiconductor areas to respectively form a source area (2) and a drain area (3) of the MOSFET; the outsides of the source area and the drain area are provided with heavily doped P-type semiconductor areas (4) for enclosure; two layers of insulating medium materials and a control gate are respectively arranged over the substrate; and an optoelectronic storage layer is arranged between the two layers of the insulating medium materials, and is made of polysilicon; the control gate is polysilicon, metal or transparent conductive electrode, and is a split gate and designed into a small control gate and a big control gate; the level of the unit of the detector is the control gate, the second layer of the insulating medium layer, a floating gate, the first layer of the insulating medium layer and the P-type semiconductor substrate (1) in turn from the top down; and a window transparent or semitransparent for detecting light waves of the detector is arranged from the control gate down to the substrate layer.

Description

Photodetector based on double control gate MOSFET structure

One, technical field

The present invention relates to a kind of imaging detection device, especially, be widely used in video camera, digital camera, palmtop PC, mobile phone, PDA etc. based on the photodetector of the double control gate MOSFET structure of CMOS technology.

Two, background technology

Extensively the solid imaging element of utilization mainly contains two classes now: charge-coupled device (CCD) and CMOS APS image device.Though ccd sensor all is better than cmos sensor at aspects such as sensitivity, resolution, noise controls, the cost height, integrated level is little, power consumption is big and need the shortcoming of multiple power supply; Cmos sensor then has the advantage of low cost, low-power consumption and high degree of integration, but also has the not high and bigger problem of noise of sensitivity.This shows that CCD and CMOS APS image device all respectively have pluses and minuses, the image device of new generation of therefore developing a kind of CCD of set and CMOS APS advantage is extremely important.

Typical visible light wave range image device CCD specification and pixel size:

maximum specification 10k x 10k (DALSA)

minimum pixel 2.4 microns (e2V) can't dwindle

well depth～1000e/ μ m ²

Typical case's CMOS-APS pixel specification (CMOS-APS imaging pixel unit has four big functions, photoelectron is collected and stored, amplifies, resets, addressing):

maximum specification 4k x 4k (0.18 micron technology, Raytheon etc.)

2.8 microns (0.25 micron technology Panasonic) is difficult to dwindle the minimum pixel

well depth 3000e/ μ m ²

CCD and CMOS-APS comprehensively are compared as follows table:

	CCD	CMOS-APS
			Leakage current	Very good＜1nA/cm 2	Bad〉50nA/cm 2
Duty ratio (Fill Factor)	Very good～100%	Bad＜60%
			Technological requirement with	Very high	Generally
Rate of finished products	Rate of finished products is low	The rate of finished products height
			Compatibility with CMOS technology	Incompatible	Compatible

The limitation of CCD and CMOS-APS: CCD and CMOS-APS are the image-forming components of extensive use in current scientific instrument and the family expenses image documentation equipment, but two kinds of image-forming components all have its unsurmountable shortcoming.CCD be in essence be parallel to each other can the directional transmissions electric charge a large amount of mos capacitances of series connection mutually, its limitation shows:

1) image taking speed is difficult to improve: need physical property ground dislocation charge in the CCD imaging process, therefore, its image taking speed is difficult to improve.

2) rate of finished products is low: because its mos capacitance framework of connecting mutually and the needs of transmission charge, in CCD pixel with delegation's series connection, any one mos capacitance lost efficacy or cisco unity malfunction all can influence the normal transmission of electric charge at this electric capacity, thereby caused coming in this row CCD pixel this electric capacity pixel cisco unity malfunction afterwards.Be usually expressed as secret note, informal voucher or the filaments of sun.Therefore, it requires high to technology controlling and process, so rate of finished products is lower usually, production cost is high.

3) pixel is difficult to further to dwindle: for the signal to noise ratio that maintains in the charge transfer constant, the CCD unit pixel dwindle requirement attenuate Oxide-Nitride (ON) thickness, and the reliability requirement of ON is constant, so further diminishing of CCD pixel has suitable difficulty.In addition, fringe field has also limited further dwindling of CCD pixel.

Above-described limitation is a problem in essence, is difficult to fundamentally solve.The influence of the technological factor of manufacturing CCD is very big.CCD is made on silicon integrated circuit, its technology basic composition comprises cleaning, oxidation, diffusion, photoetching, etching, ion injection, LPCVD, plasma growth and survey individual event technology, and the manufacturing of CCD is combined these individual event technologies exactly with different numbers and order.Oxidation, photoetching, ion inject.Oxidation is one of critical process during CCD makes, the SiO that oxidation generates ₂Film has important effect in CCD, (1) is as protection and the passivating film of CCD.2) as the dielectric of grid oxygen among the CCD.3) as the separator between the polysilicon membrane, SiO ₂Can prevent upper strata polysilicon and lower floor's inter polysilicon short circuit, oxide requires free of pinholes and space.In CCD makes, the mode of oxidizing of the dried oxygen-wet oxygen of more employing-dried oxygen combination.During CCD made, gate dielectric layer was by SiO ₂One deck silicon nitride film of layer and upward regrowth thereof constitutes jointly, and this is because silicon nitride (Si ₃N ₄) dielectric constant approximately is the twice of silicon dioxide, but because the thermal coefficient of expansion of silicon nitride approximately is the twice of silicon, cause the contact between silicon nitride and the silicon bad, and SiO ₂Approaching with the coefficient of expansion of Si, so form Si-SiO ₂-Si ₃N ₄As gate dielectric layer.Domestic and international now when the dielectric layer of research metal-oxide-semiconductor, substitute SiO with the high-dielectric-coefficient grid medium layer ₂Layer.The gate dielectric layer of research has: the metal oxide of IIIA family and IIIB family mainly comprises Al ₂O ₃, Y ₂O ₃, La ₂O ₃Deng; The group vib metal oxide mainly contains HfO ₂, ZrO ₂, TiO ₂Deng; Stacking provisions such as HfO ₂/ SiO ₂, ZrO ₂/ SiO ₂Deng.

Different with CCD, each pixel of CMOS-APS all is separate, therefore the dislocation charge that does not need physical property in whole signals transmission, from having overcome the weakness of CCD in essence, but each pixel of CMOS-APS all comprises 1 photodiode and the transistor more than three.This framework can cause following problem:

1) dark current noise height: because CMOS-APS adopts diode as light-sensitive device, its dark current is than high similar two magnitudes of CCD.

2) effective quantum efficiency is difficult to improve: different with CCD, CMOS-APS also comprises at least three transistors except photodiode, and duty ratio is less than 60%.

Three, summary of the invention

The present invention proposes a kind of new detector structure and method to set up, comprises the amplification method that reads of manufacturing process flow and signal.Especially the double control gate MOSFET imaging detector is provided with two control gates, by the control to two control gates, improves the accuracy of control and the sensitivity that detector signal reads.

The double control gate MOSFET detector, the formation of each unit of detector is: the both sides above substrate P type semiconductor silicon materials are provided with heavily doped N type semiconductor district, constitute source region and the drain region of MOSFET respectively, the outside in source, drain region is provided with heavily doped P type semiconductor district 4 and surrounds, being respectively equipped with two layers of dielectric material and controlling grid directly over the substrate, be provided with the photoelectron accumulation layer between two layers of dielectric material, described photoelectron accumulation layer is a polysilicon; The control grid is polysilicon, metal or transparency conductive electrode; Described control gate is a splitting bar, is designed to a little control gate and a big control gate; The level of detector cells is control gate, second layer insulating medium layer, floating grid, ground floor insulating medium layer and P type semiconductor substrate from top to bottom successively; Down be made as the transparent or translucent window of detector detection light wave from control gate to basalis.

The method to set up of each unit of described detector is: the both sides above substrate P type semiconductor silicon materials 1 are provided with heavily doped N type semiconductor district, constitute source region 2 and the drain region 3 of MOSFET respectively, the outside in source, drain region is provided with heavily doped P type semiconductor district 4 and surrounds, be respectively equipped with two layers of dielectric material and control grid directly over the substrate, be provided with the photoelectron accumulation layer between two layers of dielectric material, described photoelectron accumulation layer is that thickness is the polysilicon of 50～100nm; The control grid is that thickness is polysilicon, metal or the transparency conductive electrode of 100～200nm; Described control gate is a splitting bar, is designed to a little control gate 5 and a big control gate 6.The level of detector cells is control gate 5,6, second layer insulating medium layer 7, floating grid 8, ground floor insulating medium layer 9 and P type semiconductor substrate 1 from top to bottom successively.Down be made as the transparent or translucent window of detector detection light wave from control gate to basalis.Polysilicon is floated grid 8 as the photoelectron accumulation layer, is ground floor SiO below it ₂Insulating medium layer 9, thickness are 4～7nm, and by programming, the photoelectron that the voltage difference of control grid and substrate enough can make in the raceway groove greatly the time and be collected can enter floating grid by wearing effect then, rest on the floating grid and store.Being clipped between floating grid and the control gate is second layer insulating medium layer 7, and thickness is 12～20nm, adopts SiO ₂/ Si ₃N ₄/ SiO ₂Composite construction or high-k (high-k) medium its objective is to stop the photoelectron of storing on the floating grid to run off by control gate.

The technological process of described detector unit array is as follows:

At first carrying out active area definition and field oxide region isolates; Carrying out the structure of floating-gate MOS FET unit then, mainly is to form ground floor SiO ₂Insulating medium layer, the polysilicon levels such as grid, second layer ONO insulating medium layer, control gate of floating; Carry out backend process at last, mainly comprise metal interconnecting wires, dielectric deposit and planarization.

Described detector to the collection and the storage of photoelectron signal, to read the mode and the flow process of amplifying and resetting as follows:

Photoelectronic generation, collection and storage: between control gate and substrate, add a suitable positive bias pulse, can form depletion layer on P type semiconductor surface to substrate interior near the ground floor insulating medium layer, between exposure period, photon incides on the depletion layer and is absorbed the generation photoelectron by semiconductor, and photoelectron is moved to p N-type semiconductor N surface at the interface ordering about of control gate pole tension.Increase the control gate pole tension then, when voltage was enough big, photoelectron entered floating boom by the F-N tunnelling and since second layer insulating medium layer stop that photoelectron rests on the floating grid and stores.Collecting the photoelectronic stage, source electrode and drain electrode should be unsettled to prevent that electronics from injecting from source region and drain region; After photoelectron is stored on the floating grid, can produce the drift of threshold voltage,, measure the drain current of output and just can measure the photoelectron number of storing on the floating grid by to the reading of floating-gate MOS FET.

Signal read amplification: when photoelectron was collected on the floating boom, with source electrode and substrate ground connection, drain electrode connects a suitable positive voltage, and the voltage of big control gate is fixed, and regulates the voltage of little control gate, makes floating-gate MOS FET be operated in linear zone or subthreshold region.By regulating the voltage of two control gates, operating state that can point-device control floating-gate MOS FET, and can improve the sensitivity that signal is read.Export the drain current value by the measuring light electron transfer before and after floating boom, relatively both big I are determined the size of light signal.

Reset: on the control grid, add a back bias voltage, substrate ground connection; When back bias voltage was enough high, the photoelectron that stores on the floating grid was swept back in the P type semiconductor substrate by tunneling effect.Change for the threshold voltage of the back detector that guarantees to reset all is controlled in the very little error range at every turn, adopt when wiping to reset in conjunction with the mode that writes.

The invention has the beneficial effects as follows: detector is a basic structure with floating-gate MOS FET device, adopt the control gate splitted construction, designed small one and large one two control gates, by control to two control gates, improve the accuracy of control, improved the sensitivity that detector signal reads.This detector and floating boom CMOS process compatible, the manufacturing technology maturation realizes easily.Can also utilize the structure of Flash memory to constitute detection array for basic framework.Compare with CMOS-APS with CCD, double control gate MOSFET has the advantage of a lot of CCD and CMOS-APS concurrently, but has overcome their a lot of weakness, is that the ideal of image device of future generation is selected, and its characteristics and superiority comprise:

Scalability is fabulous: the yardstick of the MOSFET that contemporary flash memory technology uses is at 4～10F ²(F: minimum photoetching line dimension), when using the 50nm photoetching technique, the area of a MOSFET may diminish to 0.01 micron ², promptly at 1 micron ²On can make 100 floating-gate MOS FET.In contrast to this, the pixel of CCD minimum is～3 microns of 3 x ², and CMOS-APS is～the 1x1 micron ²The use of floating-gate MOS FET technology can provide image devices such as CMOS-APS and CCD incomparable resolution, thereby make physical resolution be higher than optical resolution.

Compatible substantially with the flash memory production technology: as can to produce double control gate MOSFET by standard floating-gate MOS FET technology is finely tuned.

Image taking speed is fast: double control gate MOSFET adopts the photoelectron identical with CCD to survey mechanism, but does not need to carry photoelectron, so image taking speed is faster than CCD.

Leakage current is low: photosensitive compound medium grid MOSFET adopts the detection mechanism identical with CCD, so its leakage current is than low one to two magnitude of the CMOS-APS that adopts photodiode.

Insensitive to defective workmanship: because double control gate MOSFET does not need to carry photoelectron, the inefficacy of any one pixel can not influence other pixel.

Control is flexible: can control MOSFET detector operation state by changing two voltages on the control gate, regulate the size of output signal, therefore can enlarge signal corresponding dynamic scope by reading with different gate voltages, improve the accuracy that reads, this is the advantage that CCD and CMOS-APS do not have.

Therefore it has advantages such as high integration, high-resolution, low cost, low-power consumption, and alternative CCD and CMOS APS image device are as the video high density transducer of a new generation.

Four, description of drawings

Fig. 1 is the cross-sectional view of detector of the present invention

Fig. 2 is the planar structure schematic diagram of detector of the present invention

Fig. 3 is planar structure schematic diagram (a) behind detector array active area of the present invention and the field oxide region and its along AA ' and BB ' direction schematic cross-section (b), (c)

Fig. 4 is that detector array of the present invention forms planar structure schematic diagram (a) behind second insulating medium layer and its along AA ' and BB ' direction schematic cross-section (b), (c)

Fig. 5 is the planar structure schematic diagram (a) on edge, detector array second layer polysilicon of the present invention fluting back and its along AA ' and BB ' direction schematic cross-section (b), (c)

Fig. 6 is that detector array of the present invention forms planar structure schematic diagram (a) behind small one and large one control gate and its along AA ' and BB ' direction schematic cross-section (b), (c)

Fig. 7 is that detector array of the present invention forms the P+ district schematic diagram outside source, the drain region

Fig. 8 is that detector array of the present invention forms source, drain region schematic diagram

Fig. 9 is that detector array of the present invention forms planar structure schematic diagram (a) behind the contact hole and its along BB ' and CC ' direction schematic cross-section (b), (c)

Figure 10 is that detector array of the present invention forms ground floor metal interconnecting wires schematic diagram

Figure 11 is that detector array of the present invention forms second layer metal interconnection line schematic diagram

Figure 12 is that detector of the present invention output current and photoelectron number when linear zone is worked concern schematic diagram

Figure 13 is that output current and the photoelectron number of detector of the present invention when subthreshold region is worked concerns schematic diagram

Five, embodiment

(1) structure of detector

The generalized section of panel detector structure is shown in 1, and floor map as shown in Figure 2.Both sides above substrate P type semiconductor silicon materials 1 are provided with source region 2 and the drain region 3 that heavily doped N type semiconductor district constitutes MOSFET respectively, and the outside in source, drain region is provided with heavily doped P type semiconductor 4 and surrounds the district.This detector has the two-layer polysilicon grid, and second layer polysilicon gate is a control gate, and control gate adopts splitted construction, is divided into a little control gate 5 and a big control gate 6, is connected with the electrode of outside respectively.Thickness is that the ground floor polysilicon gate of 50～100nm is a floating grid 8, and it is embedded between ground floor dielectric 7 and the second layer insulating medium layer 9.The ground floor insulating medium layer is thin SiO ₂Insulating barrier, thickness are 4～7nm, and thickness is that the second layer insulating medium layer 9 of 100～200nm is SiO ₂/ Si ₃N ₄/ SiO ₂Composite construction or high-k (high-k) dielectric layer, thickness is 12～20nm.To there being pair detector to survey the transparent or translucent window of optical wavelength between the basalis, the P type semiconductor area below the window is an imaging area below control gate 5,6.The spacing of the length of little control gate 5 and two control gates 5,6 is by the minimum feature size decision of technology.For example 0.18 micron.

(2) manufacturing process flow of detector array

1) definition of the active area of detector array and isolation mainly are to utilize photoetching, corrosion to be formed with source region 10, and utilize the isolation between shallow-trench isolation technology (STI) the realization active area, form field oxide region 11.After finishing above-mentioned technology, detector array planar structure and its are along AA ' and BB " sectional view of direction is shown in Fig. 3 (a) and (b), (c).

2) growth regulation one deck insulating medium layer 9 on P type silicon substrate is the SiO of thickness 7nm ₂Gate oxide, deposition thickness is first polysilicon layer 8 of 100nm in the above then, etching and remove described first polysilicon layer selectively is with the floating grid 8 that limits described detector cells.Growth second layer dielectric 7 on floating boom is respectively that thickness is the SiO of 5nnm/6nm/6.5nm again ₂/ Si ₃N ₄/ SiO ₂, form the ONO composite construction.After finishing above-mentioned technology, detector array planar structure and its are along AA ' and BB " sectional view of direction is shown in Fig. 4 (a) and (b), (c).

3) deposition thickness is the second layer polysilicon 12 of 200nm, second layer polysilicon is slotted, form second layer split polysilicon, finish detector array planar structure behind the polysilicon fluting and its along the sectional view of AA ' and BB ' direction shown in Fig. 5 (a) and (b), (c).

4) carry out etching and remove described second polysilicon layer by the size of small one and large one two control gates, with big control gate 6 and the little control gate 5 that limits described detector cells.After finishing above-mentioned technology, detector plane structure and its along the sectional view of AA ' and BB ' direction shown in Fig. 6 (a) and (b), (c).

5) the boron ion implantation dopant is so that obtain P+ district 4 outside described detector array elements source, the drain region, as shown in Figure 7.

6) the fluting place forms sidewall oxide 14, carries out ion then and injects arsenic or phosphorus dopant, obtains the source region 5 and the drain region 6 of described detector array elements, as shown in Figure 8.

7) contact hole photoetching and corrosion obtain detector array elements drain contact hole 15, source electrode contact hole 17, big control gate contact hole 16 and little control gate contact hole 18 respectively.Finish detector array planar structure after the contact hole technology and its along the sectional view of BB ' and CC ' direction shown in Fig. 9 (a) and (b), (c).

8) deposit ground floor metallic aluminium anti-carves aluminium, forms the ground floor metal interconnecting wires, and connect detector array and list the big control grid 19 of each column unit, little control grid 20, public source 21, its schematic diagram is as shown in figure 10.

9) deposit second layer metal aluminium anti-carves aluminium, forms the second layer metal interconnection line, connects the drain electrode 22 that detector array lists every capable unit, and its schematic diagram as shown in figure 11.

10) carry out dielectric deposit and planarization.

(3) detector operation principle and process

1) photoelectron is collected and storage:

1. photoelectron produces: between control grid and substrate, add a suitable positive bias pulse, and source electrode and drain electrode is unsettled, form depletion layer as photoelectronic collection district on P type semiconductor surface to substrate interior near the ground floor insulating medium layer.When rayed during at depletion layer photon absorbed by semiconductor, the electronics on the semiconductor valence band obtains enough energy and is excited to conduction band, produces photoelectron.Since have between source, drain region and the substrate highly doped P separate from, can form higher potential barrier in substrate one side and stop the electronics in source, drain region to spread to photoelectronic collection district.

2. photoelectron-transfer and wearing then: add positive voltage between control grid and substrate, photoelectron-transfer to ground floor insulating medium layer and P type semiconductor substrate at the interface; When added instantaneous positive voltage pulse reaches 10V～20V, before the P type semiconductor surface does not also form inversion layer, make the electric field in the ground floor dielectric enough strong, make the photoelectron of being collected take place to wear effect then and cross SiO ₂Insulating barrier arrives on the floating grid.

3. photoelectron storage: when electric field was more weak in the second layer insulating medium layer, photoelectron can be stored on the floating grid.

2) signal read amplification:

After photoelectron was collected floating grid, source electrode and substrate ground connection, drain electrode connects positive voltage, regulate the current potential of control grid, make floating-gate MOS FET be operated in linear zone or subthreshold region, by direct measurement to output leakage current, the leakage current that reads before and after the exposure is compared to determine the size of light signal, the current change quantity that obtains draining concerns as follows with the photoelectron number purpose of collecting:

$\mathrm{\Δ}{I}_{\mathrm{DS}}=\frac{{\mathrm{\μ}}_n{C}_{\mathrm{ox}}W}{L}\·\frac{N_{\mathrm{FG}}q}{C_T}\·V_{\mathrm{DS}}---\left(1\right)$

Δ I wherein _DSPreceding for exposing-exposure back drain current variable quantity, N _FGBe the photoelectron number of storing on the floating boom, C _TBe total equivalent capacity of detector photoelectron accumulation layer, C _OxBe the unit-area capacitance of ground floor insulating medium layer, W and L are respectively the width and the length of floating-gate MOS FET raceway groove, μ _nBe electron mobility, V _DSBe the voltage difference of drain electrode with grid.

It is as follows that signal is read the embodiment of amplification: adopt the CMOS technological design of 0.18 μ m, the channel length of floating-gate MOS FET and width are designed to 1 μ m, the length of little control gate and width are designed to 0.18 μ m and 1 μ m respectively, and the length and the width of big control gate are designed to 0.64 μ m and 1 μ m respectively.According to the power of exposure, the representative value of transferring to the photoelectron density of storing on the floating boom is 10-1000/ μ m ²

1. get drain-source voltage V _DS=0.1V regulates the control gate pole tension, makes floating-gate MOS FET be operated in linear zone, then exports drain current and is

$I_{\mathrm{DS}}={\mathrm{\&beta;}}^{\mathrm{CG}1}\&CenterDot;(V_{\mathrm{CG}1}-V_T^{\mathrm{CG}1}+\frac{Q_{\mathrm{FG}}}{C_{\mathrm{CG}1}}+\frac{{\mathrm{\&alpha;}}_{\mathrm{<figure-callout\; id="2"\; label="CG"\; filenames="A200910030729E00091.png,A200910030729E00096.png"\; state="\{\{state\}\}">CG</figure-callout>}2}}{{\mathrm{\&alpha;}}_{\mathrm{<figure-callout\; id="1V"\; label="CG"\; filenames="A200910030729E00106.png"\; state="\{\{state\}\}">CG</figure-callout>}1}}{V}_{\mathrm{CG}2})V_{\mathrm{DS}}---\left(2\right)$

β in the formula ^CG1Be the transconductance parameters of equivalence to little control gate,

Be the threshold voltage of equivalence to little control gate, Q _FGBe charge stored on the floating grid.C _CG1Be the equivalent capacity between little control gate and the floating grid, C _CG2Be the equivalent capacity between big control gate and the floating grid.α _CG2And α _CG1Be capacitive coupling coefficient, definition α _CG2=C _CG2/ C _T, α _CG1=C _CG1/ C _T, C _TTotal equivalent capacity for detector photoelectron accumulation layer.Because control gate is divided into small one and large one two control gates, the electric capacity of little control gate is less, and the drift value that obtains the threshold voltage of device from little control gate is

Little control gate is increased the control sensitivity of signal.The representative value of little control gate electric capacity is C _CG1During=0.62fF, then the maximum drift amount of threshold voltage can reach 0.258V.The representative value of capacitive coupling coefficient is α _CG1=0.15, α _CG2=0.55, regulate big control-grid voltage and make $\frac{{\mathrm{\&alpha;}}_{\mathrm{<figure-callout\; id="2"\; label="CG"\; filenames="A200910030729E00091.png,A200910030729E00096.png"\; state="\{\{state\}\}">CG</figure-callout>}2}}{{\mathrm{\&alpha;}}_{\mathrm{<figure-callout\; id="1V"\; label="CG"\; filenames="A200910030729E00106.png"\; state="\{\{state\}\}">CG</figure-callout>}1}}{\mathrm{<figure-callout\; id="2"\; label="V\; CG"\; filenames="A200910030729E00091.png,A200910030729E00096.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{CG}}=V_T^{\mathrm{CG}1},$ Balance out the influence of threshold voltage, then (2) formula can be rewritten as

$I_{\mathrm{DS}}={\mathrm{\&beta;}}^{\mathrm{CG}1}\&CenterDot;(V_{\mathrm{CG}1}+\frac{Q_{\mathrm{FG}}}{C_{\mathrm{CG}1}})V_{\mathrm{DS}}---\left(3\right)$

Work as V _CG1When getting 1V, 2V and 3V, obtain the graph of a relation of output current and photoelectron number respectively according to (3) formula, as shown in figure 12, linear between the two.Work as V _CG1Be 1V, the relative value maximum that drain current changes, during no photoelectron, drain current is 11.6 μ A, and when photoelectron was 1000, drain current was 8.6 μ A, and the drain current variable quantity is 25.8%, and the drain current that each photoelectron causes is changed to 3nA.

2. get V _CG2=1V, V _CG1=0.6V, V _DS=1V makes floating-gate MOS FET be operated in subthreshold region, and the relation of output current and photoelectron number is exponential relationship as shown in figure 13 between the two.During no photoelectron, drain current is 9.359nA, when photoelectron is 1000, drain current is 3.684nA, the drain current variable quantity is 60.1%, and the variable quantity of the drain current that photoelectron causes when subthreshold region has higher sensitivity and dynamic range apparently higher than the linear work district.

As seen, adopt two control gates to carry out reading of signal, can control accurately the detector operation state, the voltage of big control gate can be fixed, change the voltage of little control gate, enlarge signal corresponding dynamic scope by reading, and improve the sensitivity that detector signal reads with different gate voltages.Photoelectron number on floating boom can make detector be operated in subthreshold region more after a little while, improves the sensitivity that signal reads; Be operated in linear zone when photoelectron number can make detector more for a long time, and the change control-grid voltage enlarges signal corresponding dynamic scope and sensitivity.

3) reset at control and add back bias voltage, substrate ground connection on the grid; Increasing back bias voltage scans out the photoelectron in the floating boom floating boom or the hole is swept floating boom by wearing then; In concrete the application, consider the problem of " over-erasure ", adopted the mode of wiping to reset in conjunction with writing, the threshold voltage of the back detector that at every turn resets all is controlled in the very little error range changes.

Claims (7)

1, double control gate MOSFET detector, the formation that it is characterized in that each unit of detector is: the both sides in substrate P type semiconductor silicon materials (1) top are provided with heavily doped N type semiconductor district, constitute source region (2) and drain region (3) of MOSFET respectively, the outside in source, drain region is provided with heavily doped P type semiconductor district (4) and surrounds, being respectively equipped with two layers of dielectric material and controlling grid directly over the substrate, be provided with the photoelectron accumulation layer between two layers of dielectric material, described photoelectron accumulation layer is a polysilicon; The control grid is polysilicon, metal or transparency conductive electrode; Described control gate is a splitting bar, is designed to a little control gate (5) and a big control gate (6); The level of detector cells is control gate (5,6), second layer insulating medium layer (7), floating grid (8), ground floor insulating medium layer (9) and P type semiconductor substrate (1) from top to bottom successively; Down be made as the transparent or translucent window of detector detection light wave from control gate to basalis.

2, by the described double control gate MOSFET detector of claim 1, it is characterized in that polysilicon makes floating grid, thickness is 50～100nm, as the photoelectron accumulation layer; Below it ground floor SiO ₂Insulating medium layer, thickness are 4～7nm, and by programming, the photoelectron that the voltage difference of control grid and substrate enough can make in the raceway groove greatly the time and be collected can enter floating grid by wearing effect then, and rest on floating grid and store.

3,, it is characterized in that second dielectric that contacts with the control grid is SiO by the described double control gate MOSFET detector of claim 1 ₂/ Si ₃N ₄/ SiO ₂Composite construction medium or high dielectric constant, thickness are 12～20nm, stop the photoelectron of storing on the floating grid to run off by control gate.

4, by the described double control gate MOSFET detector of claim 1, it is characterized in that adopting thickness is that polysilicon, metal or the transparency conductive electrode of 100～200nm is control gate, control gate adopts splitted construction, is divided into small one and large one two control gates, is connected with the electrode of outside respectively; To there being pair detector to survey the transparent or translucent window of optical wavelength between the basalis, the P type semiconductor area below the window is an imaging area below control gate.

5, be provided with by claim 1 or 4 described double control gate MOSFET detectors, it is characterized in that control gate is divided into small one and large one two control gates, the minimum spacing between the minimum length of little control gate and two control gates is the minimum feature size of technology.

6,, it is characterized in that on small one and large one two control gates, applying two control voltages and control MOSFET detector operation state by the described double control gate MOSFET detector of claim 1.

7, the preparation method of double control gate MOSFET detector cells: in the silicon materials substrate, at first carry out active area definition and field oxide region and isolate; Carry out the structure of floating-gate MOS FET unit then; Form ground floor SiO ₂Insulating medium layer, the polysilicon levels such as grid, second layer ONO insulating medium layer, polysilicon control grid of floating; Carry out backend process at last, mainly comprise metal interconnecting wires, dielectric deposit and planarization; It is characterized in that carrying out etching and removing described second polysilicon layer, to limit small one and large one two control gates of described detector cells by the size of small one and large one two control gates.

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