CN101533676B - Method for enhancing debugger capacity of non-volatile memory - Google Patents
Method for enhancing debugger capacity of non-volatile memory Download PDFInfo
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- CN101533676B CN101533676B CN2008100836111A CN200810083611A CN101533676B CN 101533676 B CN101533676 B CN 101533676B CN 2008100836111 A CN2008100836111 A CN 2008100836111A CN 200810083611 A CN200810083611 A CN 200810083611A CN 101533676 B CN101533676 B CN 101533676B
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Abstract
The invention relates to a method for enhancing the debugger capacity of a non-volatile memory, wherein each page of the non-volatile memory is provided with a plurality of user data storage areas, a plurality of system data storage areas and a plurality of debugging code data storage areas, each user data storage area is respectively corresponding to one system data storage area and one debugging code data area. The method comprises the steps of retaining all of and part of the information respectively stored in at least one first system data storage area and one second system data storage area in the paging; and releasing the memory space of the second system data storage area except for part of the information for the corresponding debugging code data storage space thereof so as to increase the storage space of the debugging code data storage area corresponding to the second system data storage area.
Description
Technical field
The present invention relates to a kind of debug technology of medium, and be particularly related to a kind of method that increases debugger capacity of non-volatile memory.
Background technology
Along with the arriving of information age, the relevant information arround people often need use and handle at one's side.In order to comply with this trend, in many electronic products, all need dispose the storer of a constant volume, and wherein a kind ofly can be used for for a long time storage person and be non-volatility memorizer.
In general, storer is to be formed by the construction of many memory cell (memory cell) institute.When the capacity of storer is big more, also just representing the quantity of memory cell many more, the cost of relative storer is also along with increase.Therefore, in order to dwindle storer circuitry needed area, so propose a kind of multilayer memory cell Sheffer stroke gate type flash memory (multi level cell NAND flash memory).The characteristics of this multilayer memory cell Sheffer stroke gate type flash memory are to utilize different potential to store data, and therefore can reach a memory cell stores the purpose of a plurality of data, and significantly saves circuit area whereby.Yet the shortcoming of this multilayer memory cell Sheffer stroke gate type flash memory is that after access repeatedly, memory cell institute canned data can be changed, and causes the leakage (data loss) of information.
In order to solve the problem of above-mentioned spill-over, usually on multilayer memory cell Sheffer stroke gate type flash memory, can store all that (error correction code is ECC) to do the action of debug to multilayer memory cell Sheffer stroke gate type flash memory institute canned data except that error code.And this generation that removes error code has a variety of methods, and wherein the most normal adopted method is BCH (Bose, Ray-Chaudhuri, Hocquenghem) sign indicating number and RS (Reed-Solomon) sign indicating number.
Yet no matter which kind of mode of use produces the bug check sign indicating number, the byte number of bug check sign indicating number will be the factor of decision debugger capacity.Below please with reference to Fig. 1, Fig. 1 illustrates the memory configurations situation synoptic diagram of a paging of existing multilayer memory cell Sheffer stroke gate type flash memory.The memory span of paging (page) 100 is 2112 bytes, and is divided into 111～114,4 system data memory blocks 121～124,4 user data storage areas, and 4 debug code data memory blocks 131～134.Wherein, user data field 111～114 is all 512 bytes, and system data memory block 121～124 is all 3 bytes, and debug code data memory block 131～134 then all is 13 bytes.In this paging 100, because all debug code data memory blocks 131～134 all are 13 bytes, if produce except that error code with the mode of BCH code, the figure place that this moment can debug is merely fixing 32.
Summary of the invention
For under fixing storage space; Increase the debugger capacity of non-volatility memorizer effectively; The method of increase debugger capacity of non-volatile memory of the present invention can be by the storage space that increases debug code data memory block, to increase the debugger capacity to non-volatility memorizer.
The present invention proposes a kind of method that increases debugger capacity of non-volatile memory; Wherein non-volatility memorizer has a plurality of pagings; And each paging has a plurality of users data storage area and a plurality of system datas memory block and a plurality of debug code datas memory block, and each user data storage area is corresponding with its corresponding separately system data memory block and a debug code data memory block respectively.The method comprises the following steps: at first, keeps all information of one first system data memory block of one first paging in these pagings; Then; Discharge in the one second system data memory block of said first paging storage space except partial information or all storage spaces and give its corresponding debug code data memory block, so as to increasing the storage space with corresponding debug code data memory block, the second system data memory block.
Whether logical address (logic address) corresponding informance and first block of in one embodiment of this invention, storing first block that first paging is subordinate in the above-mentioned first system data memory block at least are the information of bad block.
In one embodiment of this invention, this partial information of being kept of the above-mentioned second system data memory block is whether first block is the information of bad block.
In one embodiment of this invention, the storage space that discharged of the above-mentioned second system data memory block is the shared storage space of logical address corresponding informance of storage first block.
In addition; In one embodiment of this invention; Above-mentioned and corresponding debug code data memory block, the first system data memory block and can comprise various error correcting codes respectively with corresponding debug code data memory block, the second system data memory block preferably comprise BCH error correcting code or RS error correcting code.
In one embodiment of this invention, above-mentioned non-volatility memorizer is multilayer memory cell Sheffer stroke gate type flash memory (multi level cell NAND flash memory).
The present invention proposes the another kind of method that increases debugger capacity of non-volatile memory; Wherein non-volatility memorizer has a plurality of pagings; And each paging has a plurality of users data storage area and a plurality of system datas memory block and a plurality of debug code datas memory block; Each user data storage area is corresponding with its corresponding separately system data memory block and a debug code data memory block respectively; The method comprises the following steps: at first, keeps all information of one first system data memory block of one first paging in these pagings; Then; Discharge the storage space of one second system data memory block of first paging; And use to this debug code data memory block corresponding the storage space mean allocation that the second system data memory block is discharged, to increase the storage space of all debug code data memory blocks in first paging with all user data storage areas of first paging.
In one embodiment of this invention, the storage space of the second above-mentioned system data memory block has a plurality of bytes, and the quantity of these bytes be first paging those debug code data memory blocks quantity positive integer doubly.
The present invention increases the storage space of debug code data memory block because of adopting the storage space that discharges system data memory block in the non-volatility memorizer.Thus, under the situation that does not increase storage space, also can increase debugger capacity to this non-volatility memorizer.
In order to let the above-mentioned feature and advantage of the present invention can be more obviously understandable, hereinafter is special lifts preferred embodiment, and conjunction with figs., elaborates as follows.
Description of drawings
Fig. 1 illustrates the memory configurations situation synoptic diagram of a paging of existing multilayer memory cell Sheffer stroke gate type flash memory.
Fig. 2 illustrates the process flow diagram of method of the increase debugger capacity of non-volatile memory of first embodiment of the invention.
Fig. 3 A illustrates an embodiment of the first embodiment of the present invention.
Fig. 3 B illustrates another embodiment of the first embodiment of the present invention.
Fig. 4 A illustrates another memory configurations situation of a paging of multilayer memory cell Sheffer stroke gate type flash memory.
Fig. 4 B illustrates another embodiment of the first embodiment of the present invention.
Fig. 5 illustrates the process flow diagram of method of the increase debugger capacity of non-volatile memory of second embodiment of the invention.
Fig. 6 A illustrates an embodiment of the second embodiment of the present invention.
Fig. 6 B illustrates another embodiment of the second embodiment of the present invention.
Description of reference numerals
100: paging
111～114,411～414: the user data storage area
121～124,421～424: the system data memory block
131～134,431～434: debug code data memory block
S210～S220: the step of the first embodiment of the present invention
S510～S520: the step of the second embodiment of the present invention
Embodiment
Following content will be to the method for increase debugger capacity of non-volatile memory proposed by the invention a plurality of embodiment that give an example, and understand spirit of the present invention so as to making this area tool know usually that the knowledgeable can know, and can implement it according to this.And in following embodiment, its mentioned non-volatility memorizer is multilayer memory cell Sheffer stroke gate type flash memory (multi level cell NAND flash memory).
At first please with reference to Fig. 2, Fig. 2 illustrates the process flow diagram of method of the increase debugger capacity of non-volatile memory of first embodiment of the invention.Wherein, Applied non-volatility memorizer has a plurality of pagings among this first embodiment; And each paging all has a plurality of users data storage area and a plurality of system datas memory block and a plurality of debug code datas memory block, and each user data storage area is corresponding with its corresponding separately system data memory block and a debug code data memory block respectively.
Aspect the step of implementing, at first, keep all data (S210) of one first system data memory block of one first paging in above-mentioned numerous paging at least.Then, discharge one second storage space of system data memory block except a part of information or all storage spaces of said first paging, and the space that these are released out can dispose to its corresponding debug code data memory block (S220).So, can increase the storage space of the debug code data memory block of the second system data memory block like this, and then increase ability the second system data memory block debug.
What deserves to be mentioned is that in multilayer memory cell Sheffer stroke gate type flash memory, the system data storage area stores has whether logical address corresponding informance and this block of the block that paging was subordinate at its place are the information of bad block usually.And can d/d part be logical address corresponding informance (because this information is all identical in this paging, therefore only need keep a group) wherein usually, relative, whether the information that must be retained is the information of bad block for this block then.
In the first above-mentioned embodiment; Also can be directed against the action that more system data memory block (for example all system data memory blocks except the first system data memory block) is carried out above-mentioned reservation and discharged storage space, like this can be so that the storage space of the debug code data memory block of more user data storage area correspondence increases the ability of debug.Certainly, more can be directed against more paging (each paging even) and implement the illustrated step of the preceding paragraph, to increase the debugger capacity of non-volatility memorizer.
Below will propose an embodiment, and assistant specifies the embodiment of first embodiment with diagram to the first above-mentioned embodiment.
Please with reference to Fig. 3 A, Fig. 3 A illustrates an embodiment of the first embodiment of the present invention.Continuation is an example with the storer of a paging of the multilayer memory cell Sheffer stroke gate type flash memory painted among Fig. 1.In the present embodiment, be that the data of being stored in the system data memory block 122～124 of 3 bytes all only keep 1 byte and discharge 2 bytes of memory spaces originally.Thus, its storage space of corresponding respectively debug code data memory block 132～134 then all increase to 15 bytes.
If produce the error code of removing in the debug code data memory block with the coded system of BCH code, then please cooperate table 1 again, it is indicated in figure place B1 and the correspondence table of byte number B2 that the storage space of the required debug code data memory block of ER is counted in the debug desiring to reach:
Table 1
Because the storage space of debug code data memory block 132～134 then all increases to 15 bytes; And the storage space of debug code data memory block 131 remains 13 bytes; Therefore cooperate table 1, just can learn that in this embodiment the debug number that can reach is (9 * 3)+8=35 position.Debug number than existing framework has more 3.
In addition; The above-mentioned error code of removing can also use the mode of RS sign indicating number to produce; Then please cooperate table 2 this moment, and it is indicated in and does not take place under the continuously wrong situation, and figure place B3 and the correspondence table of byte number B4 of the storage space of the required debug code data memory block of ER1 counted in the debug that can reach:
Table 2
Because the storage space of debug code data memory block 132～134 then all increases to 15 bytes; And the storage space of debug code data memory block 131 remains 13 bytes; Cooperation table 2 just can be learnt again, and the debug number that in this embodiment, can reach is (6 * 3)+5=23 position.The debug number that can reach than existing framework has more 3 (the debug number that existing framework uses the RS coding mode to reach is 20).
In addition, please with reference to Fig. 3 B, Fig. 3 B illustrates another embodiment of the first embodiment of the present invention.This embodiment is mainly to represent that the user might not keep the total data of a system data memory block, also can keep the total data of more system data memory block.In this embodiment, system data memory block 121 and system data memory block 122 are all by whole reservations.System data memory block 123 and system data memory block 124 then all discharge 2 bytes of memory spaces, also make the storage space of debug code data memory block 133,134 increase to 15 bytes whereby.So also can increase debug number (the debug number that can reach with BCH code and RS coding mode is respectively 34 and 22) effectively.
If memory configurations situation with the paging that illustrates existing multilayer memory cell Sheffer stroke gate type flash memory among above-mentioned Fig. 1; Changing becomes another memory configurations situation that illustrates a paging of multilayer memory cell Sheffer stroke gate type flash memory like Fig. 4 A, and this first embodiment still can be suitable for.At first with reference to Fig. 4 A; In Fig. 4 A, user data field 411～414 is still 512 bytes, and system data memory block 421～424 then all changes to 4 bytes; Under this framework, 431～434 of pairing debug code data memory blocks are all reduced by 1 byte and are become 12 bytes.At this moment, if the debug number that uses Bose-Chaudhuri-Hocquenghem Code mode institute to reach is 7 * 4=28 position, if use RS coded system the debug number that can reach then be 5 * 4=20 position.
Below refer again to Fig. 4 B, Fig. 4 B illustrates another embodiment of the first embodiment of the present invention.Under this embodiment; System data memory block originally 422～424 is discharged fully; Therefore the storage space of its pairing debug code data memory block 432～434 all increases to 16 bytes, and with the mode of BCH code, the debug number that institute can reach is (9 * 3)+7=34 position; The debug number that can reach with the mode of RS sign indicating number then is (7 * 3)+5=26 position, has all increased by 6 debug number than existing framework.
Comprehensive above-mentioned each embodiment can be known, in this first embodiment, is not limited to one by the system data memory block that keeps fully, and the user can adjust the quantity of the system data memory block that must keep fully according to the needs in the reality use.In addition, the storage space of the non-system data memory block that keeps fully also can discharge fully or part discharges (part keeps), and the demand that the user can also use according to reality is adjusted, and reaches the maximum debug number that it can increase.
Below will provide second embodiment and detailed description according to another method of the present invention again, and make this area tool know that usually the knowledgeable can understand and enforcement according to this.
Please with reference to Fig. 5, Fig. 5 illustrates the process flow diagram of method of the increase debugger capacity of non-volatile memory of second embodiment of the invention.Wherein, Applied non-volatility memorizer has a plurality of pagings among this second embodiment; And each paging all has a plurality of users data storage area and a plurality of system datas memory block and a plurality of debug code datas memory block, and each user data storage area is corresponding with its corresponding separately system data memory block and a debug code data memory block respectively.
Aspect the step of implementing; All information (S510) that at first keep one first system data memory block in the paging; Then; Discharge the storage space (can certainly discharge the storage space of a plurality of other system data memory blocks) of one second system data memory block in the above-mentioned paging; If the storage space that discharged for the positive integer of debug code data memory block numbers all in this paging doubly, then with the space average that is discharged distribute to this paging in all debug code data memory blocks (S520) use.Thus, the storage space of all debug code data memory blocks all can increase in this paging, and then increases possible maximum debug number.
Identical with first embodiment, this second embodiment also can carry out to a plurality of pagings (or even all pagings) in the non-volatility memorizer, more to increase the debug number.
Below will propose two embodiments, and assistant is with diagram, with more careful this second embodiment of explanation to second embodiment.
Below please with reference to Fig. 6 A, Fig. 6 A illustrates an embodiment of the second embodiment of the present invention.This embodiment adopts the paging of one 2112 byte of the multilayer memory cell Sheffer stroke gate type flash memory among Fig. 4 A to be configured to example equally.And in this embodiment, system data memory block 421 is wherein kept fully, and system data memory block 422～424 is all discharged fully.Therefore, had more 4 * 3=12 byte.And 12 just be 3 times of debug code data memory block number (being 4); Therefore give all debug code data memory blocks 431～434 with these 12 additional byte number mean allocation again; Make each debug code data memory block 431～434 all increase 12/4=3 bytes of memory space; Thus, debug code data memory block 431～434 increases by 12 bytes of memory spaces originally and becomes 15 bytes of memory spaces.
Therefore; Producing the maximum debug number that then possibly reach except that error code as if the mode with BCH code is 9 * 4=36 position; And with the mode of RS sign indicating number; Do not take place under the wrong continuously situation at this multilayer memory cell Sheffer stroke gate type flash memory, the debug number that produce then possibly reached except that error code is 6 * 4=24 position, and the debug number than existing framework has more 8 and 4 respectively.
In addition, please refer again to Fig. 6 B, Fig. 6 B illustrates another embodiment of the second embodiment of the present invention.In the embodiment that Fig. 6 B illustrates, system data memory block 421 and system data memory block 422 are all kept fully, and system data memory block 423 and system data memory block 424 then discharge fully.Therefore, the total bytes that is released out is 8 bytes, and wherein 8 are 2 times of debug code data memory block number (being 4), are 14 bytes so can increase debug code data memory block 431～434.Thus; Producing the maximum debug number that then possibly reach except that error code as if the mode with BCH code is 8 * 4=32 position; And with the mode of RS sign indicating number; Do not take place under the wrong continuously situation at this multilayer memory cell Sheffer stroke gate type flash memory, the debug number that produce then possibly reached except that error code is 6 * 4=24 position, and all the debug number than existing framework has more 4.
Can know by above-mentioned each embodiment, in this second embodiment, be not limited to one by the system data memory block that keeps fully, the user can adjust the quantity of the system data memory block that must keep fully according to the needs in the reality use.
In sum, the present invention utilizes the data in the delivery system data storage area, and gives debug code data memory block with the memory allocation that discharges.By increasing the figure place of removing error code, increase the debug number of non-volatility memorizer.The present invention need not take the storage space of user data storage area, need not increase many storage spaces yet, under the condition that does not increase cost, effectively increases the debug number.
Though the present invention discloses as above with preferred embodiment; Right its is not in order to limit the present invention; Has common knowledge the knowledgeable in the technical field under any; Do not breaking away from the spirit and scope of the present invention, when can doing a little change and retouching, so protection scope of the present invention is as the criterion as the scope person of defining that look the accompanying Claim book.
Claims (11)
1. method that increases debugger capacity of non-volatile memory; Wherein this non-volatility memorizer has a plurality of pagings; And each paging has a plurality of users data storage area and a plurality of system datas memory block and a plurality of debug code datas memory block; Each user data storage area is corresponding with its corresponding separately system data memory block and a debug code data memory block respectively, and this method comprises the following steps:
Keep all information that one first system data memory block of one first paging is stored in those pagings; And
Storage space or all storage space of the one second system data memory block that discharges this first paging except a part of information given its corresponding this debug code data memory block, so as to increasing the storage space with corresponding this debug code data memory block, this second system data memory block.
2. the method for increase debugger capacity of non-volatile memory as claimed in claim 1, wherein this first with this second system data memory block in storing one first block that this first paging is subordinate at least logical address corresponding informance and this first block whether be the information of bad block.
3. the method for increase debugger capacity of non-volatile memory as claimed in claim 2, wherein whether this partial information of being kept of this second system data memory block is the information of bad block for this first block.
4. the method for increase debugger capacity of non-volatile memory as claimed in claim 2, wherein the storage space that discharged of this second system data memory block for this second system data memory block in order to store the shared storage space of logical address corresponding informance of this first block.
5. the method for increase debugger capacity of non-volatile memory as claimed in claim 1 wherein comprises BCH error correcting code or RS error correcting code respectively with this corresponding debug code data memory block, first system data memory block and with this corresponding debug code data memory block, second system data memory block.
6. the method for increase debugger capacity of non-volatile memory as claimed in claim 1, wherein this non-volatility memorizer is a multilayer memory cell Sheffer stroke gate type flash memory.
7. method that increases debugger capacity of non-volatile memory; Wherein this non-volatility memorizer has a plurality of pagings; And each paging has a plurality of users data storage area and a plurality of system datas memory block and a plurality of debug code datas memory block; Each user data storage area is corresponding with its corresponding separately system data memory block and a debug code data memory block respectively, and this method comprises the following steps:
All information that keep one first system data memory block of one first paging in those pagings; And
Discharge the storage space of one second system data memory block of this first paging; And the storage space mean allocation that this second system data memory block is discharged is given and corresponding this debug code data memory block, all user data storage areas of this first paging, so as to increasing the storage space of all debug code data memory blocks in this first paging.
8. the method for increase debugger capacity of non-volatile memory as claimed in claim 7; Wherein the storage space of this second system data memory block has a plurality of bytes, and the number of those bytes be this first paging those debug code data memory blocks number positive integer doubly.
9. the method for increase debugger capacity of non-volatile memory as claimed in claim 7, wherein this first with this second system data memory block in storing one first block that this first paging is subordinate at least logical address corresponding informance and this first block whether be the information of bad block.
10. the method for increase debugger capacity of non-volatile memory as claimed in claim 7 wherein comprises BCH error correcting code or RS error correcting code respectively with this corresponding debug code data memory block, first system data memory block and with this corresponding debug code data memory block, second system data memory block.
11. the method for increase debugger capacity of non-volatile memory as claimed in claim 7, wherein this non-volatility memorizer is a multilayer memory cell Sheffer stroke gate type flash memory.
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| CN1658163A (en) * | 2004-02-19 | 2005-08-24 | 日本电气株式会社 | Method of data writing to and data reading from storage device and data storage system |
| CN101124639A (en) * | 2005-09-30 | 2008-02-13 | 西格马特尔公司 | System and method of accessing non-volatile computer memory |
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| CN1658163A (en) * | 2004-02-19 | 2005-08-24 | 日本电气株式会社 | Method of data writing to and data reading from storage device and data storage system |
| CN101124639A (en) * | 2005-09-30 | 2008-02-13 | 西格马特尔公司 | System and method of accessing non-volatile computer memory |
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