CN101533384A

CN101533384A - Dual processor controlling system sharing one program memory and method thereof

Info

Publication number: CN101533384A
Application number: CN200810085335A
Authority: CN
Inventors: 杰勒德·戈梅兹; 陈振波; 梅雪; 埃米莉·托里斯
Original assignee: Schneider Electric SE
Current assignee: Schneider Electric SE; Schneider Electric Industries SAS
Priority date: 2008-03-14
Filing date: 2008-03-14
Publication date: 2009-09-16

Abstract

The invention provides a dual processor controlling system sharing one memory, which comprises a reset unit used for transmitting a first reset signal to a first processor for resetting the first processor, a memory used for storing programs of the first processor and a second processor, the first processor used for carrying out access to the memory by the serial perpheral interface SPI thereof so as to read the program after receiving the first reset signal of the reset unit, setting the serial perpheral interface at a high-impedance state after completing the access to the memory, and outputting a second reset signal to the second processor, and the second processor used for responding the second reset signal from the first processor and carrying out access to the memory by the serial perpheral interface so as to read the program.

Description

Share the dual processor controlling system and the method for one program memory

Technical field

The present invention relates to the architecture design between the microprocessor and storer in a kind of control system.Specifically refer to two microprocessors and share the architecture design of a slice storer.

Background technology

In general-purpose control system, a slice microprocessor is used the application program of a slice storage system usually, and two microprocessors then need two memory stores application program separately, and its structure as shown in Figure 1.

Fig. 1 shows the architecture design of traditional dual processor and dual-memory.In Fig. 1, processor 1 and processor 2 utilize two

storeies

1 and 2 to store its application program separately respectively.

Because processor 1 and processor 2 use storer separately respectively.Therefore, cost is higher, waste printed board space, and be difficult to safeguard.

Summary of the invention

The problems referred to above at prior art propose the present invention, the present invention shares the storage chip of a slice band SPI (Serial PeripheralInterface) interface with two special microprocessors, can realize that like this, also two microprocessors use the design of same application program.

The invention provides a kind of dual processor controlling system of shared single memory, comprising: reset unit is used for sending first reset signal so that it is resetted to first processor; Storer, storage is used for the program of the first processor and second processor; First processor, after receiving first reset signal of reset unit, by its serial peripheral equipment interface SPI storer is carried out access with the fetch program, and after the access of finishing storer, Serial Peripheral Interface (SPI) is changed to high-impedance state, and exports second reset signal to second processor; And second processor, in response to second reset signal, storer is carried out access with the fetch program by its Serial Peripheral Interface (SPI) from first processor.

The present invention also provides a kind of dual processor control method of shared single memory, comprising: send first reset signal so that it is resetted to first processor; After receiving first reset signal, first processor carries out access with the fetch program by Serial Peripheral Interface (SPI) to storer, and after the access of finishing storer, Serial Peripheral Interface (SPI) is changed to high-impedance state, and export second reset signal to second processor; And in response to second reset signal from first processor, the Serial Peripheral Interface (SPI) by second processor carries out access with the fetch program to storer.

In dual processor controlling system and method according to shared single memory of the present invention, because two processors sharing a slice storeies, thereby can save cost, and save shared printed board space, be beneficial to the miniaturization Design of total system.In addition,, thereby be convenient to safeguard, save manpower because two processors use same firmware version.

Description of drawings

In conjunction with the drawings the preferred embodiments of the present invention are described in detail, above-mentioned and other purposes of the present invention, characteristic and advantage will become apparent, and wherein identical label is specified the unit of same structure, and therein:

Fig. 1 shows the traditional dual processor and the framework of dual-memory;

Fig. 2 shows the block diagram according to the dual processor controlling system of shared single memory of the present invention;

Fig. 3 shows the physical circuit figure according to the dual processor controlling system of shared monolithic EEPROM of the present invention or FLASH storer; And

Fig. 4 shows the process flow diagram according to the dual processor control method of shared single memory of the present invention.

Embodiment

With reference to the accompanying drawing that the embodiment of the invention is shown the present invention is described fully below.Yet the present invention can realize with many different forms, and not will be understood that and be limited to embodiment described here.On the contrary, provide these embodiment so that make the disclosure thorough and complete, and will give full expression to scope of the present invention to those skilled in the art.In the accompanying drawings, for the sake of clarity amplified assembly.

Although should be appreciated that and can use the term first, second, third, etc. to describe each element, assembly and/or part here, these elements, assembly and/or part are not limited by these terms.These terms only are used for element, assembly or part are made a distinction mutually.Therefore, first element of discussing below, assembly or part can be called second element, assembly or part under the prerequisite that does not deviate from the present invention's teaching.

Fig. 2 shows the block diagram according to the dual processor controlling system of shared single memory of the present invention.In Fig. 2, two processors use a slice storer to come stored programme jointly, and this processor and this storer all have the SPI interface.

As shown in Figure 2, this design comes the storage system executive routine with a slice storer, communicates by letter by spi bus between storer and two microprocessors.

Control system of the present invention comprises: the unit 1 that resets, processor 2, processor 3 and storer 4.Reset unit 1 is connected with processor 2, and reset unit 1 outputs to processor 2 with reset signal, so that processor 2 is carried out reset operation.And resetting of processor 3 controlled by the reset signal of processor 2 outputs.

After the reset signal that receives reset unit 1, processor 2 is called in executive routine by spi bus earlier and is entered in its internal RAM from storer 3, processor 2 is changed to high-impedance state by firmware with its SPI interface then, discharge spi bus, send reset signal simultaneously and it is resetted for processor 3.

After processor 3 was reset, processor 3 started communicating by letter between spi bus and the storer 4, from storer 4 interior read-out system executive routines, and program code is stored in its internal RAM, storage is changed to high resistant by firmware with the SPI interface after finishing, and discharges spi bus.

Here, processor 2 and processor 3 can call the identical system executive in the storer 4.

So far, two

microprocessors

2 and 3 will be used to carry out by the reading system executive routine from internal RAM separately.

Below, be that example describes with two special microprocessor chip XCEL, but it will be understood by those skilled in the art that the present invention is applicable to that also other have the processor chips of SPI interface.

Fig. 3 shows the physical circuit figure according to the dual processor controlling system of shared monolithic EEPROM of the present invention or FLASH storer.Here, be that example describes with for example EEPROM or FLASH storer.But it should be appreciated by those skilled in the art that other storeies that have the SPI interface are also applicable to the present invention.

As shown in Figure 3, the SPI interface of EEPROM or FLASH 4 is by SDI (serial data input), SDO (serial data output), and SCLK (serial-shift clock), four kinds of signals of CS (from enable signal) constitute.

The SPI interface of processor XCEL2 and processor XCEL 3 has 4 signal: MOSI: main go out/from go into, MISO: mainly go into/from go out, SCK: serial clock and SCS: subordinate is selected.

The SDO port of EEPROM or FLASH 4 is to the MISO of processor XCEL port output signal, and the SDI port of EEPROM or FLASH 4 receives the input of the MOSI port of from processor XCEL 2 and 3.Processor XCEL 2 and 3 SCK and SCS port communicate with SCLK and the CS port of EEPROM or FLASH 4 respectively.

When processor XCEL 2 receives the reset signal of electrification reset unit 1, start SPI interface and EEPROM or FLASH 4 and communicate.Processor XCEL 2 is from EEPROM or FLASH4 reading system executive routine, and deposits it in internal RAM.Processor XCEL 2 is changed to high-impedance state by firmware with its SPI interface then, discharges spi bus, sends reset signal simultaneously and it is resetted for processor XCEL 3.

Receive the reset signal of from processor XCEL 2 at processor XCEL 3 after, processor XCEL 3 starts communicating by letter between spi bus and EEPROM or the FLASH 4, from EEPROM or FLASH 4 interior read-out system executive routines, and program code is stored in its internal RAM, after storage finishes, by firmware the SPI interface is changed to high resistant, discharges spi bus.

So far, two processor XCEL 2 and 3 will use to carry out by the reading system executive routine from internal RAM separately.

As shown in Figure 4, at step S1, send reset signal so that first processor is resetted to first processor.At step S2, this first processor communicates by SPI interface and storer, with from the memory read program fetch.At step S3, this first processor is changed to high-impedance state with SPI, and sends reset signal to second processor.At step S4, after second processor received reset signal, the Serial Peripheral Interface (SPI) by second processor carried out access with the fetch program to storer.At step S5, the SPI interface of second processor is changed to high resistant, and discharges spi bus.

Though described the present invention in conjunction with being considered to most realistic and optimum embodiment at present, but those skilled in the art are to be understood that and the invention is not restricted to the disclosed embodiments, on the contrary, the present invention is intended to cover various modifications and the equivalent construction that comprises within the spirit of claims and the category.

Claims

1. the dual processor controlling system of a shared single memory comprises:

Reset unit is used for sending first reset signal so that it is resetted to first processor;

Storer, storage is used for the program of the first processor and second processor;

First processor, after receiving first reset signal of reset unit, by its serial peripheral equipment interface SPI storer is carried out access with the fetch program, and after the access of finishing storer, Serial Peripheral Interface (SPI) is changed to high-impedance state, and exports second reset signal to second processor; And

Second processor in response to second reset signal from first processor, carries out access with the fetch program by its Serial Peripheral Interface (SPI) to storer.

2. control system as claimed in claim 1, wherein said storer has Serial Peripheral Interface (SPI).

3. control system as claimed in claim 2, wherein said storer are EEPROM or FLASH.

4. control system as claimed in claim 3, the program that wherein is used for the first processor and second processor can be the same system executive routine.

5. control system as claimed in claim 4, wherein the first processor and second processor will be stored in respectively from the described system executive that storer reads its RAM separately.

6. control system as claimed in claim 5, wherein the first processor and second processor reading system executive routine from RAM is separately used to carry out.

7. the dual processor control method of a shared single memory comprises:

Send first reset signal so that it is resetted to first processor;

After receiving first reset signal, first processor carries out access with the fetch program by Serial Peripheral Interface (SPI) to storer, and after the access of finishing storer, Serial Peripheral Interface (SPI) is changed to high-impedance state, and export second reset signal to second processor; And

In response to second reset signal from first processor, the Serial Peripheral Interface (SPI) by second processor carries out access with the fetch program to storer.

8. control method as claimed in claim 7, wherein said storer has Serial Peripheral Interface (SPI).

9. control method as claimed in claim 8, wherein said storer are EEPROM or FLASH.

10. control method as claimed in claim 9, the program that wherein is used for the first processor and second processor can be the same system executive routine.

11. control method as claimed in claim 10, wherein the described system executive that reads from storer is respectively stored in the RAM of the first processor and second processor.

12. control method as claimed in claim 11, wherein the first processor and second processor reading system executive routine from RAM is separately used to carry out.