CN101527546B - class-D power amplifier - Google Patents

Abstract

The invention relates to a D-type power amplifier, which relates to a power amplifier and aims to solve the problems of larger chip size and easy generation of total harmonic distortion caused by the fact that a triangular wave generator or a sawtooth wave generator is required to generate carrier waves in the prior art; the output end of the square wave output circuit is connected with the input end of the gate control circuit; the output end of the gate pole control circuit is connected with the input end of the output power circuit; the output end of the output power circuit is connected with the output end of the amplifier; a feedback loop is connected between the amplifier output and an input of the integrator.

Description

A kind of D power-like amplifier

Technical field

The present invention relates to a kind of D power-like amplifier, particularly adopt a kind of D power-like amplifier of hysteresis modulation.

Background technology

The efficient of D power-like amplifier is higher than linear amplifier such as A/B class A amplifier A, because its output is worked under switching mode, therefore power consumption is minimized.The square wave that is produced by output power circuit can be used for load such as loud speaker are powered.Usually, can add extra filter between output power circuit and load loud speaker, filtered signal namely is the input signal after amplifying.

Traditional D class A amplifier A as shown in Figure 1 comprises a comparator C MP, and it receives triangular wave T and the input signal S1 that produces from triangular-wave generator TG.Comparator C MP produces the square wave S2 of variable duty ratio by comparing triangular signal T and input signal S1.When inputting greater than triangular wave T, output S2 is low; Otherwise when inputting less than triangular wave T, output S2 is high.So, obtained proportional a variation in the pwm signal of input signal S1, as shown in Figure 2 of duty ratio at the output of comparator C MP.Then the modulated signal S2 of this pulse duration is transferred into gate control circuit, and then goes to control opening and turn-offing of output transistor M1 and M2, namely, produces the square-wave signal of an amplification.Then, this square-wave signal is reduced to the input signal of amplification by the filter circuit that is comprised of inductance and electric capacity.

D class A amplifier A shown in Figure 1 is because when switching transistor M1, M2 conducting, the voltage that drops to its two ends is very little, so its efficient is high especially.The D power-like amplifier can have the efficient up to 90% like this.Yet there are some shortcomings in traditional D power-like amplifier as shown in Figure 1.It needs a triangular-wave generator TG or saw-toothed wave generator to produce carrier wave triangular wave T or the sawtooth waveforms of comparison.Triangular-wave generator or saw-toothed wave generator are structurally relatively complicated, and when it is integrated in a D class A amplifier A chip internal, need very large chip size.Simultaneously, as non-linear total harmonic distortion (Total Harmonic Distortion, THD) problem that also produced of triangular wave or the sawtooth waveforms of carrier wave.

Summary of the invention

The object of the invention is to solve prior art needs triangular-wave generator or saw-toothed wave generator to produce carrier wave and the chip size that brings more greatly, easily produces the problem of total harmonic distortion, a kind of improved D power-like amplifier is provided, this D power-like amplifier is simple in structure, need not triangular-wave generator or saw-toothed wave generator, weaken simultaneously the non-linear total harmonic distortion that causes by carrier wave.

The present invention is a kind of D power-like amplifier, comprise amplifier in, integrator, square wave output circuit, feedback loop, gate control circuit, output power circuit, amplifier out, wherein said integrator comprises two inputs and an output, and this output is connected with the input of described square wave output circuit; The output of described square wave output circuit is connected with the input of described gate control circuit; The output of described gate control circuit is connected with the input of described output power circuit; The output of described output power circuit is connected with described amplifier out; Described feedback loop is connected between the input and described amplifier out of described integrator.

A kind of D power-like amplifier as described in the present invention, described feedback loop comprises the resistance between the described input that is connected in described amplifier out and described integrator.

A kind of D power-like amplifier as described in the present invention, described square wave output circuit comprises the first comparator, the second comparator, dc bias circuit and logical circuit, two outputs of wherein said dc bias circuit respectively with the in-phase input end of described the first comparator be connected the inverting input of the second comparator and be connected; The inverting input of described the first comparator be connected the in-phase input end of comparator connect after as the input of described square wave output circuit, be connected with the output of described integrator, the output of described the first comparator be connected the output of the second comparator and be connected with two inputs of logical circuit respectively; The output of described logical circuit is connected with the input of described gate control circuit.

A kind of D power-like amplifier as described in the present invention, described logical circuit comprises the first NAND gate and the second NAND gate, wherein the first NAND gate input is connected with the output of the second NAND gate, and its another input is connected with the output of the first comparator; An input of the second NAND gate is connected with the output of the first NAND gate, and its another input is connected with the output of the second comparator; The output of the first NAND gate is connected with the input of gate control circuit.

Such as the described a kind of D power-like amplifier of the preferred embodiment of the present invention, described dc bias circuit comprises dc signal source, the first direct current offset source and the second direct current offset source; The anode in wherein said the first direct current offset source is connected with the in-phase input end of the first comparator; The negative terminal in described the second direct current offset source is connected with the inverting input of the second comparator; The negative terminal in described the first direct current offset source be connected the direct current offset source anode be connected the anode of dc signal source and connect; The negativing ending grounding of described dc signal source.

Such as the described a kind of D power-like amplifier of the preferred embodiment of the present invention, described integrator comprises operational amplifier, electric capacity and resistance, electric capacity, resistance are connected in parallel between the output and inverting input of operational amplifier, the inverting input of described operational amplifier receives the output signal of the amplifier out that feeds back via feedback loop simultaneously, and the in-phase input end of described operational amplifier connects amplifier in.

Such as the described a kind of D power-like amplifier of the preferred embodiment of the present invention, described dc bias circuit comprises direct current decoupling circuit, direct current biasing power supply and direct current biasing and level shift circuit, an input of direct current decoupling circuit is connected with amplifier in, its output is connected with direct current biasing and level shift circuit, another input of direct current biasing and level shift circuit is connected with the direct current biasing source, two outputs of direct current biasing and level shift circuit respectively with the in-phase input end of the first comparator be connected the inverting input of comparator and be connected.

Such as the described a kind of D power-like amplifier of the preferred embodiment of the present invention, described integrator comprises operational amplifier, electric capacity and resistance, electric capacity, resistance are connected in parallel between the output and inverting input of operational amplifier, the inverting input of described operational amplifier receives the output signal of the amplifier out that feeds back via feedback loop simultaneously, and the in-phase input end of described operational amplifier is connected with the dc reference signal source.

The invention has the advantages that this D power-like amplifier triangular-wave generator or saw-toothed wave generator of need not simple in structure, when therefore this D power-like amplifier is integrated in chip internal, chip size will be very little, and it is fast at a high speed to utilize feedback loop to adjust precision, and the simultaneously non-linear total harmonic distortion that causes by carrier wave is also weakened greatly.

Description of drawings

Fig. 1 illustrates the module map of D power-like amplifier in the prior art;

Fig. 2 illustrates the signal relation figure of prior art D power-like amplifier shown in Figure 1;

Fig. 3 illustrates the basic block diagram of a kind of D power-like amplifier of the first specific embodiment according to the present invention;

Fig. 4 (A) illustrates the oscillogram according to a kind of D power-like amplifier input signal of the present invention;

Fig. 4 (B) illustrates the oscillogram according to a kind of D power-like amplifier load output current of the present invention;

Fig. 4 (C) illustrates the oscillogram according to a kind of D power-like amplifier load output voltage of the present invention;

Fig. 5 illustrates the basic block diagram of the D power-like amplifier of the second specific embodiment according to the present invention.

Embodiment

The first specific embodiment

As shown in Figure 3, be one of the present invention structure chart that adopts the D power-like amplifier of hysteresis modulation.This D power-like amplifier comprises an integrator 2 that is comprised of resistance R 2, capacitor C and operational amplifier U0, resistance R 2, capacitor C are connected in parallel between the output and inverting input of operational amplifier U0, those skilled in the art will appreciate that this integrator can be other forms.

This D power-like amplifier also comprises amplifier in 1, square wave output circuit 3, feedback loop 4, gate control circuit 5, output power circuit 6, amplifier out 7, wherein: integrator 2 comprises two inputs and an output, and this output is connected with the input of described square wave output circuit 3; The output of square wave output circuit 3 is connected with the input of described gate control circuit 5; The output of gate control circuit 5 is connected with the input of described output power circuit 6; The output of output power circuit 6 is connected with described amplifier out 7; Feedback loop 4 is connected between the input and described amplifier out 7 of described integrator 2.

The in-phase input end of operational amplifier U0 receives input signal V _IN, inverting input receives the output signal SW that feeds back via feedback loop 4, and feedback loop 4 comprises the resistance R 1 between the inverting input that is connected to amplifier out 7 and operational amplifier U0 in the present embodiment.The input signal V that the signal that inverting input receives and in-phase input end receive _INDifference by operational amplifier U ₀Amplify integration on capacitor C.

In the present embodiment, square wave output circuit 3 comprises the first comparator U1, the second comparator U2, dc bias circuit 31 and logical circuit 32, wherein: two outputs of dc bias circuit 31 respectively with the in-phase input end of described the first comparator U1 be connected the inverting input of the second comparator U2 and be connected; The inverting input of the first comparator U1 be connected the in-phase input end of comparator U2 connect after as the input of described square wave output circuit 3, be connected with the output of described integrator 2, the output of described the first comparator U1 be connected the output of the second comparator U2 and be connected with two inputs of logical circuit 32 respectively; The output of logical circuit 32 is connected with the input of described gate control circuit 5.

And dc bias circuit 31 comprises dc signal source 310, the first direct current offset source 311 and the second direct current offset source 312; Wherein: the anode in the first direct current offset source 311 is connected with the in-phase input end of the first comparator U1; The negative terminal in the second direct current offset source 312 is connected with the inverting input of the second comparator U2; The negative terminal in the first direct current offset source 311 be connected direct current offset source 312 anode be connected the anode of dc signal source 310 and connect; The negativing ending grounding of dc signal source 310.

The DC component that dc bias circuit 31 detects input signal arranges the dc-bias VT of dc signal source 310, makes both DC component identical, with collaborative work.Simultaneously, in two side-play amounts of dc-bias VT stack, the superpose value in the first direct current offset source 311 of dc-bias VT is VT ₁Side-play amount after be connected to the in-phase input end of the first comparator U1; The superpose value in the second direct current offset source 312 of dc-bias VT is VT ₂Side-play amount after be connected to the inverting input of the second comparator U2, in the present embodiment, get VT ₁=0.1V, VT ₂=-0.1V, but those skilled in the art will recognize that side-play amount can be other values, rather than be limited in the value that the present embodiment is got.The output of the first comparator U1 is connected to the input of the first NAND gate U5; The output of the second comparator U2 is connected to the input of the second NAND gate U6.The output of the second NAND gate U6 is connected to another input of the first NAND gate U5, the output of the first NAND gate U5 is connected to another input of the second NAND gate U6, and be transferred into the amplifier output power circuit 6 that is formed by transistor M1 and M2 via gate control circuit 5 simultaneously, thereby obtain output signal SW at amplifier out 7.The gate pole of transistor M1 and M2 all is connected in gate control circuit 5.The source electrode of upper pipe p channel transistor M1 is connected in supply voltage V _CC, its drain electrode is connected in drain electrode and the amplifier out 7 of lower pipe N channel transistor M2; The source electrode of lower pipe N channel transistor M2 is connected in ground.Output signal SW is then by by inductance L _FAnd capacitor C _FFilter 8 filtering that form, thus load 9 be supplied to, such as loud speaker; Perhaps need not filter and directly be supplied to inductive load.

Because the gain of operational amplifier U0 is quite high, the voltage of its in-phase input end and inverting input can be regarded as equal (empty short).Difference between operational amplifier U0 in-phase input end and the inverting input is integrated on capacitor C.Operational amplifier U ₀Output and the difference of bias point reflected error voltage, error is mainly produced by output signal SW.Then the first comparator U1 and the second comparator U2 compare the signal of the first and second threshold levels of the output of operational amplifier U0 and dc bias circuit output respectively and decide switching frequency and duty ratio.That is, when the output of operational amplifier U0 less than the second threshold level " VT+VT ₂", the first comparator U1 is output as height, uses " 1 " expression; the second comparator U2 is output as low, with " 0 " expression, so low level of the first NAND gate U5 output is to gate control circuit 5; the at this moment upper transistor M1 conducting of output power circuit 6, the level V at amplifier out 7 places _OUT=V _CC, so that output signal SW uprises, thereby also uprise through the output of operational amplifier U0 after the feedback; When the output of operational amplifier U0 slowly increases between the second threshold level " VT+VT ₂" and the first threshold level " VT+VT ₁" between the time, the first comparator U1 is output as height, with " 1 " expression; the second comparator U2 output also be high; with " 1 " expression, so the first NAND gate U5 keeps its output state before, two transistorized conducting states of output power circuit 6 also remain unchanged; When the output resume increase of operational amplifier U0 so that greater than the first threshold level " VT+VT ₁" time, the first comparator U1 is output as low, uses " 0 " expression; the second comparator U2 is output as height, with " 1 " expression, so high level of the first NAND gate U5 output is to gate control circuit 5; the at this moment lower transistor M2 conducting of output power circuit 6, the amplifier out 7 level V of place _OUT=0, so that output signal SW step-down, thereby through the output of operational amplifier U0 after the feedback also step-down; When the output of operational amplifier U0 slowly is decreased between the second threshold level " VT+VT ₂" and the first threshold level " VT+VT ₁" between the time, the first comparator U1 is output as height, with " 1 " expression; the second comparator U2 output also be high; with " 1 " expression, so the first NAND gate U5 keeps its output state before, two transistorized conducting states of output power circuit 6 also remain unchanged; When the output resume of operational amplifier U0 reduces until less than the second threshold level " VT+VT ₂", just repeat top running status.Therefore, the gate control circuit 5 of exporting to of the first NAND gate U5 provides a signal that level just changes.Correspondingly, transistor M1 and M2 open along with pwm signal or turn-off.Like this, obtained a square wave at amplifier out 7 places.On the one hand, the output signal SW at amplifier out 7 places is sent to load via filter 8; On the other hand, output signal SW is fed back to the inverting input of operational amplifier U0 through feedback loop 4, listened to the part of feedback signal and input signal V _INOffset.As mentioned above, the in-phase input end of operational amplifier U0 and inverting input are close to and equate.The high-frequency modulation signal that the HFS of feedback signal is obtained by capacitor C institute integration and the gate pole level of the first comparator U1 and the second comparator U2 compare and obtain the PWM ripple.Thereby under the condition of triangular-wave generator or saw-toothed wave generator, amplifier adopts the hysteresis modulation to obtain pwm signal.

As mentioned above, can find out the loop voltag value VHY=VT that stagnates ₁-VT ₂Ideally, the loop voltag value that stagnates represents output signal SW and input signal V _INScope behind the errors integration.If ignore the impact of high-frequency modulation signal, the voltage V of output signal SW _OUTShould be by input signal V _INDetermine.The output of operational amplifier U0 equals dc-bias VT, it should with input signal V _INDC component V _OFFAlso equate.The gain of supposing operational amplifier U0 is enough large, and then the in-phase input end of operational amplifier U0 and inverting input equate, the tiny signal that the tiny signal of operational amplifier U0 output should be inputted in proportion to.So the gain G equation can be expressed as follows:

$\frac{V_{\mathrm{OUT}}-V_{\mathrm{IN}}}{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="S2008100449049E00011.png,S2008100449049E00021.png"\; state="\{\{state\}\}">R</figure-callout>}1}=\frac{V_{\mathrm{IN}}}{R2}---\left(1\right)$

$\&DoubleRightArrow;G=\frac{V_{\mathrm{OUT}}}{V_{\mathrm{IN}}}=\frac{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="S2008100449049E00011.png,S2008100449049E00021.png"\; state="\{\{state\}\}">R</figure-callout>}1+R2}{R2}---\left(2\right)$

Because switching frequency is higher than audio bandwidth far away, can use V _INPExpression is independent of the input voltage V of time _INA bit, and in whole switch periods, keep constant.When upper transistor M1 conducting, V _OUT=VCC, during instantly transistor M2 conducting, V _OUT=0V, so calculating formula is expressed as follows:

When upper transistor M1 conducting and lower transistor M2 turn-off, t wherein _rPlay the duration of transistor M2 shutoff for upper transistor M1 conducting:

$\frac{\mathrm{VHY}\&times;C}{t_r}=\frac{V_{\mathrm{OUT}}-V_{\mathrm{INP}}}{R1}-\frac{\mathrm{VHY}}{R2}---\left(3\right)$

$\&DoubleRightArrow;t_r=\frac{\mathrm{VHY}\&times;C\&times;\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="S2008100449049E00011.png,S2008100449049E00021.png"\; state="\{\{state\}\}">R</figure-callout>}1\&times;R2}{(V_{\mathrm{CC}}-V_{\mathrm{INP}})\&times;R2-\mathrm{VHY}\&times;R1}---\left(4\right)$

Upper transistor M1 turn-offs and during lower transistor M2 conducting, wherein t _fTurn-off the duration of transistor M2 conducting for upper transistor M1:

$\frac{\mathrm{VHY}\&times;C}{t_f}=\frac{V_{\mathrm{INP}}-V_{\mathrm{OUT}}}{R1}-\frac{\mathrm{VHY}}{R2}---\left(5\right)$

$\&DoubleRightArrow;t_f=\frac{\mathrm{VHY}\&times;C\&times;{\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="S2008100449049E00011.png,S2008100449049E00021.png"\; state="\{\{state\}\}">R</figure-callout>}}_1\&times;R_2}{\left(V_{\mathrm{INP}}\right)\&times;R_2-\mathrm{VHY}\&times;R_1}---\left(6\right)$

Switch periods T _SWFor:

$T_{\mathrm{SW}}=t_r+t_f=\frac{\mathrm{VHY}\&times;C\&times;\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="S2008100449049E00011.png,S2008100449049E00021.png"\; state="\{\{state\}\}">R</figure-callout>}1\&times;R2}{(V_{\mathrm{CC}}-V_{\mathrm{INP}})\&times;R2-\mathrm{VHY}\&times;\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="S2008100449049E00011.png,S2008100449049E00021.png"\; state="\{\{state\}\}">R</figure-callout>}1}+\frac{\mathrm{VHY}\&times;C\&times;\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="S2008100449049E00011.png,S2008100449049E00021.png"\; state="\{\{state\}\}">R</figure-callout>}1\&times;R2}{\left(V_{\mathrm{INP}}\right)\&times;R2-\mathrm{VHY}\&times;R1}---\left(7\right)$

Can find out from equation (7): the switching frequency of the D class A amplifier A of the stagnant ring modulation of this employing is followed the variation of input signal and is changed.

According to equation (4), (6), (7), duty ratio is:

$D=\frac{t_r}{T_{\mathrm{SW}}}=\frac{t_r}{t_r+t_f}=\frac{\frac{\mathrm{VHY}\&times;C\&times;\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="S2008100449049E00011.png,S2008100449049E00021.png"\; state="\{\{state\}\}">R</figure-callout>}1\&times;R2}{(V_{\mathrm{CC}}-V_{\mathrm{INP}})\&times;R2-\mathrm{VHY}\&times;\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="S2008100449049E00011.png,S2008100449049E00021.png"\; state="\{\{state\}\}">R</figure-callout>}1}}{\frac{\mathrm{VHY}\&times;C\&times;\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="S2008100449049E00011.png,S2008100449049E00021.png"\; state="\{\{state\}\}">R</figure-callout>}1\&times;R2}{(V_{\mathrm{CC}}-V_{\mathrm{INP}})\&times;R2-\mathrm{VHY}\&times;\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="S2008100449049E00011.png,S2008100449049E00021.png"\; state="\{\{state\}\}">R</figure-callout>}1}+\frac{\mathrm{VHY}\&times;C\&times;\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="S2008100449049E00011.png,S2008100449049E00021.png"\; state="\{\{state\}\}">R</figure-callout>}1\&times;R2}{\left(V_{\mathrm{INP}}\right)\&times;R2-\mathrm{VHY}\&times;\mathrm{<figure-callout\; id="1"\; label="R"\; filenames="S2008100449049E00011.png,S2008100449049E00021.png"\; state="\{\{state\}\}">R</figure-callout>}1}}$

$=\frac{V_{\mathrm{INP}}\&times;R2-\mathrm{VHY}\&times;R1}{V_{\mathrm{CC}}\&times;R2-2\mathrm{VHY}\&times;R1}---\left(8\right)$

Can find out from equation (8), the duty ratio of the D class A amplifier A of the stagnant ring modulation of this employing is followed the variation of input signal and is changed.

Fig. 4 (A), Fig. 4 (B), Fig. 4 (C) show the D class operational amplifier input signal that the present invention adopts the hysteresis modulation, the output current in the load, the oscillogram of output voltage.

The second specific embodiment

Figure 5 shows that the basic block diagram of the D class operational amplifier of the present invention's the second specific embodiment.In this structure, identical with the first specific embodiment, there is an integrator that is formed by resistance R 2, capacitor C, operational amplifier U0.The output of operational amplifier U0 is connected to the inverting input of comparator U1 and the in-phase input end of comparator U2.Be with the first specific embodiment difference, it is VR that the in-phase input end of operational amplifier U0 connects a DC level value _EfDc reference signal 10, end of oppisite phase receives the output signal SW that feeds back via feedback loop 4, feedback loop 4 comprise resistance R 1 the same as the first specific embodiment in the present embodiment; The present embodiment adopts direct current decoupling circuit U8 that input signal is removed DC component simultaneously, afterwards at direct current biasing and level shift circuit U7 place, also is VR with value _EfDirect current biasing source VB _IasInput signal is reset DC component, and two dc offsets superpose, thereby obtain two signals with different dc offsets, the signal of described two different dc offsets is connected directly to the in-phase input end of the first comparator U1 and the inverting input of the second comparator U2.That is, at first the DC component of input signal is carried out then at direct current biasing and level shift circuit U7 part its DC component being re-set as direct current biasing source VB every directly _IasBias, and V _{IN (dc)}=VR _Ef, obtain V _{IN (ac)}+ VR _Ef, V wherein _{IN (dc)}The DC component that the expression input signal is reset, V _{IN (ac)}The alternating current component of expression input signal.Then at V _{IN (ac)}+ VR _EfSide-play amount of the above's stack is VT ₁Direct current offset and obtain inputing to the first signal V1 of the first comparator U1 in-phase input end, this V1 is as the first threshold level of this embodiment, its value is V1=V _{IN (ac)}+ VR _Ef+ VT ₁, simultaneously at V _{IN (ac)}+ VR _EfThe above's side-play amount that superposes again is VT ₂Direct current offset and obtain inputing to the second comparator U ₂The secondary signal V2 of inverting input, this V2 are as the second threshold level of this embodiment, and its value is V2=V _{IN (ac)}+ VR _Ef+ VT ₂In the present embodiment, VT ₁=0.1V, VT ₂=-0.1V.The connected mode of other parts of circuit is the same with the first specific embodiment circuit shown in Figure 3, no longer repeat, and the part identical with Fig. 3 adopts identical Reference numeral.

Because the gain of operational amplifier U0 is quite high, the voltage of its in-phase end and end of oppisite phase can be regarded as equal (empty short).Operational amplifier U ₀The reference level VR that in-phase input end receives _EfThe difference of the signal that receives with inverting input is integrated on capacitor C.The output of operational amplifier U0 is amplified by the operational amplifier gain, and at direct current biasing VR _EfFloat near the point.The output of operational amplifier U0 and the difference of bias point have reflected error voltage, and error is mainly produced by output signal SW.Then the first comparator U1 and the second comparator U2 compare the output of operational amplifier U0 and set threshold level and decide switching frequency and duty ratio.Namely, when the output of operational amplifier U0 less than the second threshold level V2, the first comparator U1 is output as height, represent with " 1 ", the second comparator U2 is output as low, with " 0 " expression, so low level of the first NAND gate U5 output is to gate control circuit 5, the at this moment upper pipe M1 conducting of output power circuit 6, the amplifier out 7 level V of place _OUT=V _CC, so that thereby the output that output signal SW uprises through operational amplifier U0 after the feedback also uprises; When the output of operational amplifier U0 slowly increases between the second threshold level V2 and the first threshold level V1, the first comparator U1 is output as height, represent with " 1 ", the second comparator U2 output also is high, represent with " 1 ", so the first NAND gate U5 keeps the output state before it, two transistorized conducting states of output power circuit 6 also remain unchanged; When the output resume of operational amplifier U0 increases consequently greater than the first threshold level V1, the first comparator U1 is output as low, represent with " 0 ", the second comparator U2 is output as height, represent with " 1 ", so the first NAND gate U5 exports a high level to gate drive circuit 5, the at this moment lower pipe M2 conducting of output power circuit 6, the amplifier out 7 level V of place _OUT=0, thereby so that output signal SW step-down through feedback after the also step-down of output of operational amplifier U0; When the output of operational amplifier U0 slowly is decreased between the second threshold level V2 and the first threshold level V1, the first comparator U1 is output as height, represent with " 1 ", the second comparator U2 output also is high, represent with " 1 ", so the first NAND gate U5 keeps the output state before it, two transistorized conducting states of output power circuit 6 also remain unchanged; When the output resume of operational amplifier U0 reduces until less than the second threshold level V2, just repeat top running status.Therefore, the gate control circuit 5 of exporting to of the first NAND gate U5 provides a signal that level just changes.Correspondingly, transistor M1 and M2 open along with pwm signal or turn-off.Like this, obtained a square wave at amplifier out 7 places.On the one hand, the output signal SW at amplifier out 7 places is sent to load via filter; On the other hand, output signal SW is fed back to the inverting input of operational amplifier U0 via feedback loop 4.At operational amplifier U0 place, the direct current biasing of feedback signal and reference level VR _EfOffset.As mentioned above, the in-phase input end of operational amplifier U0 and inverting input are close to and equate.The HFS of feedback signal is obtained high-frequency modulation signal by the capacitor C integration, result and input signal V that it and low frequency part superpose _INCompare with the gate pole level stack result of comparator U1 and U2 and to obtain the signal that level just changes.Thereby, under the condition of triangular-wave generator or saw-toothed wave generator, obtaining the PWM ripple.

The same with the basic structure of the D class operational amplifier that adopts the hysteresis modulation in the first specific embodiment, the frequency of the D class operational amplifier of the described employing hysteresis modulation of the second specific embodiment and duty ratio are also followed the variation of input signal and are changed.

Can see, the first NAND gate U5 and the second NAND gate U6 play a part rest-set flip-flop.That is: the first NAND gate U5 plays reset response, is equivalent to R; The second NAND gate U6 plays the set effect, is equivalent to S.Work as R=1, during S=0, the first NAND gate U ₅The level that flows to gate control circuit 5 is low; Work as R=0, during S=1, the first NAND gate U5 flows to the level of gate control circuit 5 for high; Work as R=1, during S=1, the first NAND gate U5 flows to the level of gate control circuit 5 for keeping original output state.Therefore, one skilled in the art would recognize that this amplifier can adopt the module of other similar functions to replace the first NAND gate U5 and the second NAND gate U6, and be not limited only to the first disclosed NAND gate U5 and the second NAND gate U6.Simultaneously, the switching tube of output power circuit 6 is not limited only to the combination of PMOS and NMOS, all right other respective combination; And can be full-bridge circuit, and be not limited only to disclosed single-ended half-bridge circuit.

Above; to understand the present invention for those skilled in the art; and the detailed description that the present invention is carried out; but can expect; within not breaking away from the scope that claim of the present invention contains, can also make other changes and modifications, these variations and revising all in the scope that claim of the present invention is protected.

Claims (7)

1. a D power-like amplifier comprises amplifier in (1), integrator (2), square wave output circuit (3), feedback loop (4), gate control circuit (5), output power circuit (6), amplifier out (7), wherein

Described integrator (2) comprises two inputs and an output, and this output is connected with the input of described square wave output circuit (3);

The output of described square wave output circuit (3) is connected with the input of described gate control circuit (5);

The output of described gate control circuit (5) is connected with the input of described output power circuit (6);

The output of described output power circuit (6) is connected with described amplifier out (7);

Described feedback loop (4) is connected between the input of described amplifier out (7) and described integrator (2); Wherein

Described square wave output circuit (3) comprises the first comparator (U1), the second comparator (U2), dc bias circuit (31) and logical circuit (32), two outputs of wherein said dc bias circuit (31) respectively with the in-phase input end of described the first comparator (U1) be connected the inverting input of the second comparator (U2) and be connected; The inverting input of described the first comparator (U1) be connected the in-phase input end of comparator (U2) connect after as the input of described square wave output circuit (3), be connected with the output of described integrator (2), the output of described the first comparator (U1) be connected the output of the second comparator (U2) and be connected with two inputs of logical circuit (32) respectively; The output of described logical circuit (32) is connected with the input of described gate control circuit (5);

Described logical circuit (32) plays a part rest-set flip-flop.

2. a kind of D power-like amplifier as claimed in claim 1 is characterized in that, described feedback loop (4) comprises the described input that is connected in described integrator (2) and the resistance (R1) between the described amplifier out (7).

3. a kind of D power-like amplifier as claimed in claim 2 is characterized in that, described logical circuit (32) comprises the first NAND gate (U5) and the second NAND gate (U6), wherein

An input of the first NAND gate (U5) is connected with the output of the second NAND gate (U6), and its another input is connected with the output of the first comparator (U1);

An input of the second NAND gate (U6) is connected with the output of the first NAND gate (U5), and its another input is connected with the output of the second comparator (U2);

The output of the first NAND gate (U5) is connected with the input of gate control circuit (5).

4. a kind of D power-like amplifier as claimed in claim 3 is characterized in that, described dc bias circuit (31) comprises dc signal source (310), the first direct current offset source (311) and the second direct current offset source (312); Wherein

The anode in described the first direct current offset source (311) is connected with the in-phase input end of the first comparator (U1);

The negative terminal in described the second direct current offset source (312) is connected with the inverting input of the second comparator (U2);

The negative terminal in described the first direct current offset source (311) be connected direct current offset source (312) anode be connected the anode of dc signal source (310) and connect;

The negativing ending grounding of described dc signal source (310).

5. a kind of D power-like amplifier as claimed in claim 4, it is characterized in that, described integrator (2) comprises operational amplifier (U0), electric capacity (C) and resistance (R2), electric capacity (C), resistance (R2) are connected in parallel between the output and inverting input of operational amplifier (U0), the inverting input of described operational amplifier (U0) receives the output signal of the amplifier out (7) that feeds back via feedback loop (4) simultaneously, and the in-phase input end of described operational amplifier (U0) connects amplifier in (1).

6. a kind of D power-like amplifier as claimed in claim 3, it is characterized in that, described dc bias circuit (31) comprises direct current decoupling circuit (U8), direct current biasing power supply (VBias) and direct current biasing and level shift circuit (U7), an input of direct current decoupling circuit (U8) is connected with amplifier in (1), its output is connected with an input of direct current biasing and level shift circuit (U7), another input of direct current biasing and level shift circuit (U7) is connected with direct current biasing power supply (VBias), two outputs of direct current biasing and level shift circuit (U7) respectively with the in-phase input end of the first comparator (U1) be connected the inverting input of comparator (U2) and be connected.

7. a kind of D power-like amplifier as claimed in claim 6, it is characterized in that, described integrator (2) comprises operational amplifier (U0), electric capacity (C) and resistance (R2), electric capacity (C), resistance (R2) are connected in parallel between the output and inverting input of operational amplifier (U0), the inverting input of described operational amplifier (U0) receives the output signal of the amplifier out (7) that feeds back via feedback loop (4) simultaneously, and the in-phase input end of described operational amplifier (U0) is connected with dc reference signal source (10).

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