CN101526705A - Liquid crystal display panel, thin film transistor substrate and manufacturing process thereof - Google Patents
Liquid crystal display panel, thin film transistor substrate and manufacturing process thereof Download PDFInfo
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- CN101526705A CN101526705A CN200810065795A CN200810065795A CN101526705A CN 101526705 A CN101526705 A CN 101526705A CN 200810065795 A CN200810065795 A CN 200810065795A CN 200810065795 A CN200810065795 A CN 200810065795A CN 101526705 A CN101526705 A CN 101526705A
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Abstract
The invention relates to a liquid crystal display panel, a thin film transistor substrate and a manufacturing process thereof. The thin film transistor substrate comprises a plurality of first scanning lines which are mutually parallel, a plurality of second scanning lines which are parallel with the first scanning lines and are overlapped with at least part of the first scanning lines, a plurality of data wires which are in perpendicular insulation intersection with the first scanning lines and the second scanning lines, a plurality of first pixel electrodes, a plurality of second pixel electrodes, a plurality of first thin film transistors and a plurality of second thin film transistors. Grids of the first thin film transistors are connected to the first scanning lines, while source electrodes are connected to the data wires and drain electrodes are connected to the first pixel electrodes. Grids of the second thin film transistors are connected to the second scanning lines, while source electrodes are connected to the data wires and drain electrodes are connected to the second pixel electrodes. The thin film transistor substrate and the liquid crystal display panel using the thin film transistor substrate have a higher aperture ratio.
Description
Technical field
The present invention relates to the manufacturing process of a kind of thin film transistor base plate, thin film transistor base plate and use the display panels of this thin film transistor base plate.
Background technology
Display panels generally includes a thin film transistor base plate, a colored filter substrate and is clipped in liquid crystal layer between these two substrates, it is by applying voltage respectively to these two substrates, control therebetween that liquid crystal molecule reverses and realizes passing through or not passing through of light, thereby reach the purpose of demonstration.The liquid crystal drive mode of tradition display panels is a nematic mode, yet its angular field of view is narrow,, when observing picture from different perspectives, will observe different display effects that is.
For solving the narrower problem in nematic mode display panels visual angle, industry proposes a kind of four territory vertical alignment-type liquid crystal display panels, by a plurality of "＜" shape projection and groove being set at interval at these two substrates, each pixel cell is divided into four zones, liquid crystal molecule tool one fixed orientation that each is regional, thereby the liquid crystal molecular orientation in the whole pixel cell disperses, and then enlarges the overall viewing angle of this pixel cell, improves the viewing angle characteristic of display panels.
Yet, because long axis of liquid crystal molecule is different with the optical index of minor axis, will produce color offset phenomenon when observing four territory vertical alignment-type liquid crystal display panels from different perspectives, influence display quality.For improving the color offset phenomenon of four territory vertical alignment-type liquid crystal display panels, industry proposes again a pixel cell is divided into two sub-pixel unit, each sub-pixel unit is divided into four zones, offer two operating voltages that sub-pixel unit is different by two thin film transistor (TFT)s respectively, thereby eight territories of realizing vertical alignment-type liquid crystal display panel show, improve color offset phenomenon.
Seeing also Fig. 1, is the floor map that a kind of prior art is used for the thin film transistor base plate of eight territory vertical alignment-type liquid crystal display panels.This thin film transistor base plate 100 comprises many first sweep traces 118, many second sweep traces 119, many data lines 138, a plurality of the first film transistor 101, a plurality of second thin film transistor (TFT) 103, a plurality of first pixel electrode 154, a plurality of second pixel electrode 155, a plurality of first through hole 144 and a plurality of second through holes 145.
These many first sweep traces 118 are parallel to each other with these many second sweep traces 119 and setting at interval successively.These many data lines 138 and this first sweep trace 118 and 119 vertically insulated intersecting of second sweep trace.This first film transistor 101 is positioned at the intersection of this first sweep trace 118 and this data line 128, and it comprises a first grid 116, one first source electrode 134 and one first drain electrode 135.This first grid 116 is connected to this first sweep trace 118; This first source electrode 134 is connected to this data line 138; This first drain electrode 135 is connected to this first pixel electrode 154 by this first through hole 144.This second thin film transistor (TFT) 103 is positioned at the intersection of this second sweep trace 119 and this data line 138, and it comprises a second grid 117, one second source electrode 136 and one second drain electrode 137.This second grid 117 is connected to this second sweep trace 119; This second source electrode 136 is connected to this data line 138; This second drain electrode 137 is connected to this second pixel electrode 155 by this second through hole 145.
Yet, this thin film transistor base plate 100 comprises many first sweep trace 118 and second sweep traces 119 that are provided with at interval, this first sweep trace 118 and second sweep trace, 119 area occupied are bigger, cause adopting the display panels aperture opening ratio of this thin film transistor base plate 100 less, influence the display effect of this display panels.
Summary of the invention
For solving the lower problem of prior art thin film transistor base plate aperture opening ratio, be necessary the thin film transistor base plate that provides a kind of aperture opening ratio higher.
Simultaneously, be necessary to provide a kind of manufacturing process and the display panels that uses this thin film transistor base plate that can obtain than the thin film transistor base plate of high aperture.
A kind of thin film transistor base plate, it comprises many first sweep traces that are parallel to each other, many be parallel to this first sweep trace and with partly overlapping at least second sweep trace of this first sweep trace; Many with this first sweep trace and the vertically insulated crossing data line of second sweep trace; A plurality of first pixel electrodes; A plurality of second pixel electrodes; A plurality of the first film transistors and a plurality of second thin film transistor (TFT).The transistorized grid of this first film is connected to this first sweep trace, and source electrode is connected to this data line, and drain electrode is connected to this first pixel electrode; The grid of this second thin film transistor (TFT) is connected to this second sweep trace, and source electrode is connected to this data line, and drain electrode is connected to this second pixel electrode.
A kind of manufacturing process of above-mentioned thin film transistor base plate, it comprises the steps: that a. provides a substrate, forms this first grid and first sweep trace in this substrate; B. on this first grid and first sweep trace, form a gate insulator; On this gate insulator, form the semiconductor channel layer in regular turn; C. on this semiconductor channel layer, form this first source electrode, second source electrode, first drain electrode, second drain electrode and the data line; D. on this first source electrode, second source electrode, first drain electrode, second drain electrode and data line, form a passivation layer; On this passivation layer, form this second grid, second sweep trace, first pixel electrode and second pixel electrode with e..
A kind of display panels, it comprises that a colored filter substrate, a thin film transistor base plate and are clipped in the liquid crystal layer between these two substrates; This colored filter substrate comprises a public electrode, and this thin film transistor base plate comprises many first sweep traces that are parallel to each other, many be parallel to this first sweep trace and with partly overlapping at least second sweep trace of this first sweep trace; Many with this first sweep trace and the vertically insulated crossing data line of second sweep trace; A plurality of first pixel electrodes; A plurality of second pixel electrodes; A plurality of the first film transistors and a plurality of second thin film transistor (TFT).The transistorized grid of this first film is connected to this first sweep trace, and source electrode is connected to this data line, and drain electrode is connected to this first pixel electrode; The grid of this second thin film transistor (TFT) is connected to this second sweep trace, and source electrode is connected to this data line, and drain electrode is connected to this second pixel electrode.
Compared with prior art, the thin film transistor base plate that obtains by above-mentioned manufacturing process, its first sweep trace and second sweep trace are overlapped at least, thereby this first sweep trace and the second sweep trace area occupied are less, use the display panels aperture opening ratio of this thin film transistor base plate higher.
Description of drawings
Fig. 1 is the floor map that a kind of prior art is used for the thin film transistor base plate of eight territory vertical alignment-type liquid crystal display panels.
Fig. 2 is the floor map of thin film transistor base plate first embodiment of the present invention.
Fig. 3 is the diagrammatic cross-section of thin film transistor base plate shown in Figure 2 along the III-III direction.
Fig. 4 is the manufacturing process flow diagram of thin film transistor base plate shown in Figure 2.
Fig. 5 is each step synoptic diagram of the manufacturing process of thin film transistor base plate shown in Figure 2 to Figure 15.
Figure 16 is the floor map of thin film transistor base plate second embodiment of the present invention.
Figure 17 is the synoptic diagram of display panels one better embodiment of the present invention.
Figure 18 is the schematic equivalent circuit of display panels shown in Figure 17.
Embodiment
See also Fig. 2 and Fig. 3, Fig. 2 is the floor map of thin film transistor base plate first embodiment of the present invention, and Fig. 3 is the diagrammatic cross-section of this thin film transistor base plate along the III-III direction.This thin film transistor base plate 200 comprises many first sweep traces 218, many second sweep traces 259, many data lines 238, a plurality of the first film transistor 201, a plurality of second thin film transistor (TFT) 203, a plurality of first pixel electrode 254, a plurality of second pixel electrode 255, a plurality of first through hole 244 and a plurality of second through holes 245.
These many first sweep traces 218 are parallel to each other, and these many second sweep traces 259 also are parallel to each other, and this first sweep trace 218 is overlapping with these second sweep trace, 259 insulation.Wherein, this second sweep trace 259 be positioned at this first sweep trace 218 directly over and this first sweep trace 218 covered fully.The material of this first sweep trace 218 is a metal, as: aluminium (Al) is metal, molybdenum (Mo), chromium (Cr), tantalum (Ta) or copper (Cu).The material of this second sweep trace 259 is a transparency conducting layer, as: indium tin oxide (Indium Tin Oxide, ITO) or indium-zinc oxide (Indium Zinc Oxide, IZO).
These many data lines 238 and this first sweep trace 218 and 259 vertically insulated intersecting of second sweep trace, thus define a plurality of rectangular areas 204.Wherein, each rectangular area 204 comprises a first film transistor 201, one second thin film transistor (TFT) 203, one first pixel electrode 254 and one second pixel electrode 255.
This first film transistor 201 is positioned at the intersection of this first sweep trace 218 and this data line 238, and it is a channel-etch type thin film transistor (TFT).Comprise that a first grid 216, one first source electrode 234, one first drain electrode 235 and are clipped in this first grid 216 and this first source electrode, semiconductor channel layer 226 between 234,235 drains.This first grid 216 is connected to this first sweep trace 218; This first source electrode 234 is connected to this data line 238; This first drain electrode 235 is connected to this first pixel electrode 254 by this first through hole 244.The material of this first grid 216 is a metal, as: aluminum-based metal, molybdenum, chromium, tantalum or copper.
This second thin film transistor (TFT) 203 is positioned at this second sweep trace 259 and is oppositely arranged with the intersection of this data line 238 and with this first film transistor 201, it is a raceway groove protection type thin film transistor (TFT), comprises a second grid 257, semiconductor channel layer 226 and is clipped in second source electrode 236, one second drain electrode 237 between this second grid 257 and this semiconductor channel layer 226; The material of this second grid 257 is a transparency conducting layer, as: indium tin oxide or indium-zinc oxide.This second grid 257 is connected to this second sweep trace 259; This second source electrode 236 is connected to this data line 238; This second drain electrode 237 is connected to this second pixel electrode 255 by this second through hole 245.
See also Fig. 4 to Figure 15, Fig. 4 is the manufacturing process flow diagram of this thin film transistor base plate 200, and Fig. 5 is each step synoptic diagram of the manufacturing process of this thin film transistor base plate 200 to Figure 15.The manufacturing process of this thin film transistor base plate 200 mainly comprises five road masks, and concrete steps are as follows:
Step S21: form the first grid and first sweep trace;
See also Fig. 5 and Fig. 6, a substrate of glass 211 is provided, form a gate metal layer 213 and one first photoresist layer 215 thereon in regular turn.Wherein, this gate metal layer 213 can be a single layer structure, also can be a sandwich construction, and its material can be aluminum-based metal, molybdenum, chromium, tantalum or copper.
Provide this first photoresist layer 215 of one first mask alignment to expose, again the first photoresist layer 215 after the exposure is developed, thereby form a predetermined photoresist pattern.This gate metal layer 213 is carried out etching, removing, and then form this first grid 216 and this first sweep trace 218, remove this first photoresist layer 215 not by the part of grid pole metal level 213 of this photoresist pattern covers.Wherein, this first grid 216 is connected to this first sweep trace 218.
Step S22: form gate insulator and semiconductor channel layer;
See also Fig. 7 and Fig. 8, deposition one silicon nitride (SiNx) film on this substrate of glass 211, this first grid 216 and this first sweep trace 218, thus form a gate insulator 221; On this gate insulator 221, form semi-conductor layer 223 and one second photoresist layer 225 more in regular turn in regular turn.Wherein, this semiconductor layer 223 comprises that one is positioned at amorphous silicon layer on this gate insulator 221 (figure does not show) and and is positioned at heavily doped amorphous silicon layer (scheming not show) on this amorphous silicon layer.
Provide this second photoresist layer 225 of one second mask alignment to expose, again the second photoresist layer 225 after the exposure is developed, thereby form a predetermined photoresist pattern.This semiconductor layer 223 is carried out etching, removing, and then form this semiconductor channel layer 226, remove this second photoresist layer 225 not by the part semiconductor layer 223 of this photoresist pattern covers.
Step S23: the slit that forms first source electrode, first drain electrode, second source electrode, second source electrode, data line and semiconductor channel layer;
See also Fig. 9, Figure 10 and Figure 11, on this gate insulator 221 and this semiconductor channel layer 226, form one source/drain metal layer 231 and one the 3rd photoresist layer 233 in regular turn.Provide one the 3rd mask alignment the 3rd photoresist layer 233 to expose, again the 3rd photoresist layer 233 after the exposure is developed, thereby form a predetermined photoresist pattern.This source/drain metal layer 231 is carried out etching, and then form this first source electrode 234, first drain electrode, 235, second source electrode 236, second drain electrode 237 and the data line 238.Further use HCl and SF
6Mixed gas as etching gas this semiconductor channel layer 226 is carried out etching, form the slit 239 of this semiconductor channel layer 226, remove the 3rd photoresist layer 233.Wherein, this first source electrode 234 is connected to this data line 238; Second source electrode 237 is connected to this data line 238.
Step S24: form passivation layer, first through hole and second through hole;
See also Figure 12 and Figure 13, on the slit 239 of this gate insulator 221, this first source electrode 234, first drain electrode, 235, second source electrode 236, second drain electrode 237, data line 238 and semiconductor channel layer 226, form a passivation layer 241 and one the 4th photoresist layer 243 in regular turn.Provide one the 4th mask alignment the 4th photoresist layer 243 to expose, again the 4th photoresist layer 243 after the exposure is developed, thereby form a predetermined photoresist pattern.This passivation layer 241 is carried out etching, and then form this first through hole 244 that runs through this passivation layer 241 and second through hole 245, remove the 4th photoresist layer 243.Wherein, 244 pairs of this first through holes should first drain electrode 235, and 245 pairs of this second through holes should second drain electrode 237.
Step S25: form second grid, second sweep trace, first pixel electrode and second pixel electrode;
See also Figure 14 and Figure 15, on this passivation layer 241, this first through hole 244 and second through hole 245, form a transparency conducting layer 251 and one the 5th photoresist layer 253 in regular turn.Provide one the 5th mask alignment the 5th photoresist layer 253 to expose, again the 5th photoresist layer 253 after the exposure is developed, thereby form a predetermined photoresist pattern.This transparency conducting layer 251 is carried out etching, and then form this second grid 257, this second sweep trace 259, this first pixel electrode 254 and second pixel electrode 255, remove the 5th photoresist layer 253.Wherein, this first pixel electrode 254 is connected to this first drain electrode 235 by this first through hole 244, this second pixel electrode 255 is connected to this second drain electrode 237 by this second through hole 245, this second sweep trace 259 is connected to this first grid 257, and this second sweep trace 259 is positioned at directly over this first sweep trace 218, and this first sweep trace 218 is covered fully.
Compared with prior art, the thin film transistor base plate 200 that obtains by above-mentioned manufacturing process, its first sweep trace 218 and 259 insulation of second sweep trace are overlapping, thereby this first sweep trace 218 and second sweep trace, 259 area occupied are less, use the display panels aperture opening ratio of this thin film transistor base plate 200 higher.
Seeing also Figure 16, is the floor map of thin film transistor base plate second embodiment of the present invention.The thin film transistor base plate 280 of this embodiment and the thin film transistor base plate 200 of first embodiment are roughly the same, and its key distinction is: second sweep trace 288 and first sweep trace only part 289 are overlapping.
Seeing also Figure 17, is the synoptic diagram of display panels one better embodiment of the present invention.This display panels 300 comprises that a colored filter substrate 310, a thin film transistor base plate 320 and are clipped in the liquid crystal layer 330 between this colored filter substrate 310 and the thin film transistor base plate 320.The thin film transistor base plate 200 that this thin film transistor base plate 320 uses above-mentioned manufacturing process to obtain.This colored filter substrate 310 comprises a public electrode (figure does not show).
Seeing also Figure 18, is the schematic equivalent circuit of display panels shown in Figure 180.Be positioned at public electrode 305 definition one pixel cell 306 of a first film transistor 301, one second thin film transistor (TFT) 303, one first pixel electrode 354, one second pixel electrode 355 and these first, second pixel electrode 354,355 correspondences of same rectangular area.Wherein, public electrode 305 definition one first sub-pixel unit 307 of this first film transistor 301, one first pixel electrode 354 and these first pixel electrode, 354 correspondences; Public electrode 305 definition one second sub-pixel unit 308 of this second thin film transistor (TFT) 303, one second pixel electrode 355 and these second pixel electrode, 355 correspondences.
When driving this display panels 300, apply one first cut-in voltage to delegation's first sweep trace 318, make the first film transistor 301 conductings on this row first sweep trace 318, apply a plurality of first gray scale voltages simultaneously to this data line 338, this first GTG electrode shows this first sub-pixel unit 307 by the source electrode of this first film transistor 301, this first pixel electrode 354 that drains.
Stop to apply this first cut-in voltage, apply one greater than second cut-in voltage of this first cut-in voltage to next line second sweep trace 359, make second thin film transistor (TFT), 303 conductings on this row second sweep trace 359, apply a plurality of second gray scale voltages simultaneously to this data line 338, this second GTG electrode shows this second sub-pixel unit 308 by the source electrode of this second thin film transistor (TFT) 303, this second pixel electrode 355 that drains.
Because this first film transistor 301 is channel-etch type thin film transistor (TFT)s; this second thin film transistor (TFT) 303 is that raceway groove protection type thin film transistor (TFT) and its grid material are transparency conducting layer; when applying identical cut-in voltage; the conducting degree of this first film transistor 301 is than second thin film transistor (TFT), 303 height; therefore; apply different cut-in voltages to this first film transistor 301 and second thin film transistor (TFT) 303; the conducting degree that can guarantee this first, second thin film transistor (TFT) 301,303 is identical, keeps good display.
It is described that thin film transistor base plate 200 of the present invention is not limited to above-mentioned embodiment, as: in first embodiment, the material of this second sweep trace 359 also can be metal.
In addition, thin film transistor base plate of the present invention also can be applied to traditional display panels, and two adjacent sweep trace insulation are overlapping, to increase aperture opening ratio.
Claims (10)
1. thin film transistor base plate, it comprises that many first sweep traces that are parallel to each other, many are parallel to second sweep trace of this first sweep trace, many and this first sweep trace and the vertically insulated crossing data line of second sweep trace, a plurality of first pixel electrode, a plurality of second pixel electrode, a plurality of the first film transistor and a plurality of second thin film transistor (TFT), the transistorized grid of this first film is connected to this first sweep trace, source electrode is connected to this data line, and drain electrode is connected to this first pixel electrode; The grid of this second thin film transistor (TFT) is connected to this second sweep trace, and source electrode is connected to this data line, and drain electrode is connected to this second pixel electrode, and it is characterized in that: this second sweep trace and this first sweep trace are overlapped at least.
2. thin film transistor base plate as claimed in claim 1 is characterized in that: this first film transistor is the channel-etch type thin film transistor (TFT), and this second thin film transistor (TFT) is a raceway groove protection type thin film transistor (TFT).
3. thin film transistor base plate as claimed in claim 1, it is characterized in that: the material of this second sweep trace and second grid is a transparency conducting layer, the material of this first pixel electrode and second pixel electrode is a transparency conducting layer, and this first pixel electrode, second pixel electrode, this second sweep trace and this second grid are to form in same mask manufacturing technology steps.
4. thin film transistor base plate as claimed in claim 1, it is characterized in that: this thin film transistor base plate further comprises a plurality of first through holes and a plurality of second through hole, this the first film transistor drain is to be connected to this first pixel electrode by this first through hole, and the drain electrode of this second thin film transistor (TFT) is to be connected to this second pixel electrode by this second through hole.
5. the manufacturing process of thin film transistor base plate as claimed in claim 1, it comprises the steps:
A., one substrate is provided, in this substrate, forms this first grid and first sweep trace;
B. on this first grid and first sweep trace, form a gate insulator; On this gate insulator, form the semiconductor channel layer in regular turn;
C. on this semiconductor channel layer, form this first source electrode, second source electrode, first drain electrode, second drain electrode and the data line;
D. on this first source electrode, second source electrode, first drain electrode, second drain electrode and data line, form a passivation layer; With
E. on this passivation layer, form this second grid, second sweep trace, first pixel electrode and second pixel electrode.
6. the manufacturing process of thin film transistor base plate as claimed in claim 5, it is characterized in that: among this step e, this first pixel electrode, second pixel electrode, this second grid and second sweep trace are to form in same mask manufacturing technology steps.
7. the manufacturing process of thin film transistor base plate as claimed in claim 5, it is characterized in that: further comprise in this steps d forming a plurality of first through holes and second through hole that runs through this passivation layer, corresponding first drain electrode of this first through hole, this second through hole to should second drain electrode, this first through hole and second through hole are to form in the same mask manufacturing technology steps.
8. the manufacturing process of thin film transistor base plate as claimed in claim 7, it is characterized in that: e is specific as follows for this step: form a transparency conducting layer and a photoresist layer on this passivation layer, this first through hole and second through hole in regular turn, provide this photoresist layer of a mask alignment to expose, again the photoresist layer after the exposure is developed, form a predetermined photoresist pattern, transparency conducting layer is carried out etching, and then form this second sweep trace, this first pixel electrode and second pixel electrode, remove this photoresist layer.
9. display panels, it comprises that a colored filter substrate, a thin film transistor base plate and are clipped in the liquid crystal layer between these two substrates; This colored filter substrate comprises a public electrode, this thin film transistor base plate comprises that many first sweep traces that are parallel to each other, many are parallel to second sweep trace of this first sweep trace, many and this first sweep trace and the vertically insulated crossing data line of second sweep trace, a plurality of first pixel electrode, a plurality of second pixel electrode, a plurality of the first film transistor and a plurality of second thin film transistor (TFT), the transistorized grid of this first film is connected to this first sweep trace, source electrode is connected to this data line, and drain electrode is connected to this first pixel electrode; The grid of this second thin film transistor (TFT) is connected to this second sweep trace, and source electrode is connected to this data line, and drain electrode is connected to this second pixel electrode, and it is characterized in that: this second sweep trace and this first sweep trace are overlapped at least.
10. display panels as claimed in claim 9; it is characterized in that: this first film transistor is the channel-etch type thin film transistor (TFT); this second thin film transistor (TFT) is a raceway groove protection type thin film transistor (TFT), and first cut-in voltage that is applied to this first sweep trace is greater than second cut-in voltage that is applied to this second sweep trace.
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| Application Number | Priority Date | Filing Date | Title |
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| CN2008100657959A CN101526705B (en) | 2008-03-07 | 2008-03-07 | Liquid crystal display panel, thin film transistor substrate and manufacturing process thereof |
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| CN2008100657959A CN101526705B (en) | 2008-03-07 | 2008-03-07 | Liquid crystal display panel, thin film transistor substrate and manufacturing process thereof |
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| CN101526705A true CN101526705A (en) | 2009-09-09 |
| CN101526705B CN101526705B (en) | 2011-02-16 |
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| CN2008100657959A Expired - Fee Related CN101526705B (en) | 2008-03-07 | 2008-03-07 | Liquid crystal display panel, thin film transistor substrate and manufacturing process thereof |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102314031A (en) * | 2010-07-01 | 2012-01-11 | 群康科技(深圳)有限公司 | Thin film transistor array plate for liquid crystal display |
| CN102810304A (en) * | 2012-08-09 | 2012-12-05 | 京东方科技集团股份有限公司 | Pixel unit, pixel structure, display device and pixel driving method |
| CN103217846A (en) * | 2013-04-23 | 2013-07-24 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN105185295A (en) * | 2015-08-24 | 2015-12-23 | 友达光电股份有限公司 | Pixel array |
| CN107958910A (en) * | 2017-12-21 | 2018-04-24 | 惠科股份有限公司 | Active switch array base palte and its manufacture method |
| CN113629075A (en) * | 2021-08-03 | 2021-11-09 | 深圳市华星光电半导体显示技术有限公司 | Back plate, backlight module and manufacturing method thereof |
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| WO2001082273A1 (en) * | 2000-04-21 | 2001-11-01 | Seiko Epson Corporation | Electrooptical device |
| KR100980010B1 (en) * | 2003-07-14 | 2010-09-03 | 삼성전자주식회사 | Thin film transistor array panel |
| US7557886B2 (en) * | 2004-06-29 | 2009-07-07 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102314031A (en) * | 2010-07-01 | 2012-01-11 | 群康科技(深圳)有限公司 | Thin film transistor array plate for liquid crystal display |
| CN102810304A (en) * | 2012-08-09 | 2012-12-05 | 京东方科技集团股份有限公司 | Pixel unit, pixel structure, display device and pixel driving method |
| CN102810304B (en) * | 2012-08-09 | 2015-02-18 | 京东方科技集团股份有限公司 | Pixel unit, pixel structure, display device and pixel driving method |
| CN103217846A (en) * | 2013-04-23 | 2013-07-24 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN103217846B (en) * | 2013-04-23 | 2015-12-02 | 京东方科技集团股份有限公司 | Array base palte and display device |
| US9385144B2 (en) | 2013-04-23 | 2016-07-05 | Boe Technology Group Co., Ltd. | Array substrate and display device |
| CN105185295A (en) * | 2015-08-24 | 2015-12-23 | 友达光电股份有限公司 | Pixel array |
| CN107958910A (en) * | 2017-12-21 | 2018-04-24 | 惠科股份有限公司 | Active switch array base palte and its manufacture method |
| CN107958910B (en) * | 2017-12-21 | 2020-06-12 | 惠科股份有限公司 | Active switch array substrate and manufacturing method thereof |
| CN113629075A (en) * | 2021-08-03 | 2021-11-09 | 深圳市华星光电半导体显示技术有限公司 | Back plate, backlight module and manufacturing method thereof |
| CN113629075B (en) * | 2021-08-03 | 2022-09-27 | 深圳市华星光电半导体显示技术有限公司 | Back plate, backlight module and manufacturing method thereof |
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| Publication number | Publication date |
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| CN101526705B (en) | 2011-02-16 |
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