CN101521952A - Device for realizing wireless sensor network access protocol - Google Patents
Device for realizing wireless sensor network access protocol Download PDFInfo
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- CN101521952A CN101521952A CN200910061561A CN200910061561A CN101521952A CN 101521952 A CN101521952 A CN 101521952A CN 200910061561 A CN200910061561 A CN 200910061561A CN 200910061561 A CN200910061561 A CN 200910061561A CN 101521952 A CN101521952 A CN 101521952A
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Abstract
The invention discloses a device for realizing a wireless sensor network access protocol. The channel contention mechanisms with different MAC protocols are mapped as the software programs inside a coprocessor, the reusability of the MAC can be enhanced by using the programmable flexibility of the coprocessor, the flexibility of the hardware is promoted, and the design cost of the hardware is reduced. The device comprises a sending part, a coprocessor part and a receiving part, wherein the coprocessor part comprises an interrupt flag register, a random number generator, a programmable MAC timer and a coprocessor; the coprocessor receives a signal from a CPU interface through an internal bus, the sending part, the receiving part and the interrupt flag register are controlled according to the generated control command, and the switching control between the receiving state and the sending state as well as the realization of the CSMA/CA algorithm are finished. The FPGA verification shows that the invention has simple design structure and small occupied area, can support the 20-250kbps communication rate, fully considers the feasibility of communication under the different wireless sensor network protocols and is especially suitable for the node chip of the wireless sensor network.
Description
Technical field
The invention belongs to the digital integrated circuit field, be specifically related to a kind of implement device of wireless sensor network access protocol, this method is exclusively used in medium access key-course (MAC, Medium AccessControl) access protocol, the hardware that is particularly useful for having csma (CSMA-CA, the carrier sence multiple access with collision avoidance) access protocol that conflict avoids is realized.
Background technology
Along with the high speed development of wireless communication technology, with the radio network technique as the basis arise at the historic moment.(Wireless Sensor Network WSN) is exactly one of them outstanding representative to wireless sensor network.WSN has merged the advantage of modern network technology, wireless communication technology, sensor technology, embedded computing technique, and node adopts specific protocol from forming net, and collaborative work is widely used in fields such as military affairs, environmental monitoring, space exploration.2003, U.S.'s " technology review " magazine was chosen as it first of the ten big emerging technologies that exerted far reaching influence on human future.
Wireless sensor network has different design objects with traditional wireless network (as WLAN, honeycomb mobile telephone network), the latter is intended to maximize bandwidth availability ratio by optimizing route and policy in resource management in the environment of high-speed mobile, guarantees for the user provides service quality simultaneously.And in wireless sensor network, except the minority node need move, most of node is static, network runs in the adverse circumstances that people can't be approaching usually, the energy can't substitute, so the design efficient strategy reduces power consumption, the life cycle that prolongs network becomes the key problem of wireless sensor network.
The MAC agreement is mainly used in that transmission for data connects and allocation of network resources rationally and effectively between each node.The characteristic of wireless sensor network and use and to impel its mac-layer protocol different with traditional wireless MAC layer protocol, its main purpose is energy-conservation and successfully transmits, and the justice of each node and time delay are less important.
At the application of different sensing networks, the researcher has proposed a plurality of MAC agreements from different aspects, and wherein IEEE802.15.4 is the most representative agreement, and it adopts the CSMA-CA algorithm as channel contention mechanism.In addition, the transducer MAC agreement based on competition also has S-MAC, T-MAC or the like.
CSMA-CA---MAC channel access mechanism, the wireless sensor network WAP (wireless access protocol) relates to and avoids collision and reduce number of retransmissions, is one of main consideration of MAC design.Occurred the research of a lot of CSMA-CA algorithms both at home and abroad, CSMA-CA algorithm and energy consumption are arranged, the relation of channel throughput has the improvement of CSMA-CA algorithm, the CSMA-CA algorithm is arranged to adaptability research of different communication environment or the like.But the research that realizes about association's processing hardware seldom.
Realize that the mode that inserts algorithm mainly contains two kinds, a kind of is software mode, and another kind is a hardware mode.If the MAC agreement realizes just can saving cost with software as far as possible, but correspondingly can produce more power consumption.If all realize then increase cost with hardware.Plan takes the method for software-hardware synergism design to average out on the MAC of wireless sensor network protocols layer software/hardware realized.
The design of traditional IEEE802.3 ethernet mac mainly comprises transmission, receives and control three parts, and control section adopts and embeds hardware flow control and CSMA algorithmic controller.IEEE802.11 WLAN (wireless local area network) MAC is embedded CSMA-CA algorithmic controller.Be used for the MAC of sensor network owing to be subjected to the restriction of cost and power consumption, must do the requirement that sizable adjustment adapts to agreement with respect to traditional MAC design.Based on the MAC of coprocessor control accelerator is that different sensors network MAC agreement is particularly being put forward on the research basis of IEEE802.15.4 agreement.The MAC of this architectural framework mainly comprises three parts: send, receive and coprocessor.Coprocessor is the core of whole M AC, and control receives and the transmit status machine is coordinated half-duplex transmitting-receiving control.The another one function of coprocessor is to finish the CSMA-CA algorithm or support to other MAC agreement is provided by the mode that program is carried out.
Summary of the invention
The object of the present invention is to provide a kind of WAP (wireless access protocol) implement device based on coprocessor, the wireless access mechanism of different MAC agreements is mapped as the software program of coprocessor inside, utilize the reusability of coprocessor programmable flexibility enhancing MAC, promote hardware flexibility, reduce cost of hardware design.
The implement device of wireless sensor network access protocol provided by the invention comprises the transmission part, control section and receiving unit; Send part and be used to realize that targeting sequencing and frame separator insert, carry out CRC and calculate, finish frame and send and automatic-answering back device; Receiving unit is used for realizing physical layer is received identification of Frame separator and CRC check, and go forward side by side row address matching check and frame information filter; It is characterized in that: described control section is the coprocessor part, comprises interrupt identification bit register, tandom number generator, MAC timer able to programme and coprocessor;
MAC timer able to programme generates the set time by programming, offer coprocessor, tandom number generator provides the random time that needs for coprocessor, coprocessor is by the signal of internal bus reception from cpu i/f, according to producing control command, control sends part, receiving unit and interrupt identification bit register, finishes accepting state, the realization of switching controls between the transmit status and CSMA/CA algorithm;
Separately start and send data by sending enable signal control sending part behind the end of operation, begin to receive data, control the interrupt identification bit register and put interrupt bit, make device be in interrupt status by interrupting asserts signal by receiving enable signal control receiving unit.
Coprocessor used in the present invention is 8 bit processors of a RISC framework, uses 16 buses and Harvard (Harvard) structure.The CSMA-CA coprocessor has independently instruction set, carries out the switching of two kinds of mode of operations by quick command strobes and program, realizes that CPU is to the control to radio-frequency module of the control of CSMA-CA coprocessor and CSMA-CA coprocessor.It not only can carry out the application program of CSMA-CA algorithm together with MAC layer timer, and radio-frequency module is directly controlled in executive control operation fast, reduces CPU and handles burden, accelerates the communication of radio-frequency module, handles thereby finish association.The present invention is on primary study IEEE802.15.4 agreement basis, consider speed simultaneously, trading off of power consumption and flexibility, a kind of sensor network MAC control accelerator architecture that meets the IEEE802.15.4 protocol requirement based on the coprocessor framework has been proposed, the MAC of this architecture also supports agreements such as S-MAC, T-MAC.FPGA checking result shows that this project organization is simple, and area occupied is little, can support the 20-250kbps traffic rate, has taken into full account communication feasibility under the different radio sensing network agreement, is particularly suitable for being applied in the radio sensing network node chip.
Description of drawings
Fig. 1 is the structural representation of the implement device of wireless sensor network access protocol provided by the invention;
Fig. 2 for the coprocessor internal structure and with the schematic diagram that concerns of inner other module of MAC;
Fig. 3 is the working state schematic representation based on the MAC hardware accelerator of coprocessor framework;
Fig. 4 is an IEEE802.15.4 agreement CSMA-CA algorithm flow chart;
Fig. 5 is S-MAC protocol and T-MAC protocol schematic diagram;
Table 1 supports the periodicity of T-MAC and S-MAC agreement to intercept the example program.
Embodiment
The present invention is further detailed explanation below in conjunction with accompanying drawing and example.
As shown in Figure 1, this figure is the MAC architecture based on the coprocessor framework, and the MAC of this architectural framework mainly is divided into transmission part 1, coprocessor part 2 and receiving unit 3.
Send part 1 and be used to realize that targeting sequencing and frame separator insert, CRC calculates, functions such as frame transmission and automatic-answering back device.Mainly comprise the transmission fifo module, realize sending asynchronous buffer device function; Preamble field and initial symbol generation module realize that targeting sequencing and start-of-frame insert; The CRC computing module is realized the calculating of CRC; Send the data arbitration modules, realize the framing operation; Transmit status machine module is used to produce the sending module control signal; The automatic-answering back device module produces hardware from dynamic response; The transmitting counter module realizes tally function.
The transmitting counter module produces count signal and sends into transmit status machine module, this module produces to transmit control signal again and cooperates the CRC computing module to calculate crc value, send into transmission data arbitration modules in the lump with the targeting sequencing and the start-of-frame insertion of preamble field and the generation of initial symbol generation module and the transmission data that send in the fifo module, the operation of realization framing, it is corresponding automatically to send into automatic-answering back device module generation hardware under the control of transmit status machine module, after hardware is corresponding, the transmission data that send after the data arbitration modules is operated framing send, and send into physical interface module.
Receiving unit 3 is used for realizing physical layer is received the identification of Frame separator, CRC check, matching addresses inspection, functions such as frame information filtration.Mainly comprise the reception fifo module, realize receiving asynchronous buffer device function; The address comparison module realizes that the receiving data frames matching addresses detects; The initial detection module of frame is used to receive the data preamble field and detects; The received frame parsing module is realized received frame identification; Accepting state machine module, the control signal of generation receiver module; Receive data channel, provide transmission channel for receiving data; Count pick up device module is finished tally function; The CRC check module is finished the data CRC check.
Count pick up device module produces count signal and sends into accepting state machine module, this module produces the receiver module control signal, control received frame parsing module is realized received frame identification, the control address comparison module realizes that the receiving data frames matching addresses detects and the initial detection module of frame realizes that reception data preamble field detects simultaneously, these two modules are returned testing result and are sent into accepting state machine module, control reception data are sent into the reception fifo module by the reception data channel and are realized receiving asynchronous buffer device function, finally send into cpu i/f.
Coprocessor part 2 also is an emphasis of the present invention, and it is responsible for accepting state, the realization of switching controls between the transmit status and CSMA/CA algorithm.This part can adopt structure as shown in Figure 2 to realize that it comprises interrupt identification bit register 4, tandom number generator 5, MAC timer 6 able to programme and coprocessor 7.
Interrupt identification bit register 4 is to be used for the sign interruption, tandom number generator 5 is used to the random time that coprocessor 7 provides to be needed, MAC timer 6 able to programme is used to provide the programmable set time, and coprocessor 7 is responsible for the realization and the translation thereof of CSMA/CA algorithm and is carried out.
Set time able to programme that MAC timer 6 able to programme and randomizer 5 generation CSMA/CA algorithms need and random time are to cooperate the work of coprocessor 7, the signal that coprocessor 7 receives from cpu i/f by internal bus 9, finish translation and execution, produce and send enable signal and reception enable signal instruction.Send part 1 by the control of transmission enable signal and begin to send data, begin to receive data, control interrupt identification bit register 4 by the interruption asserts signal and put interrupt bit, make device be in interrupt status by receiving enable signal control receiving unit 3.
As shown in Figure 2, coprocessor 7 comprises internal bus 8, internal bus 9, first, second MUX 10,11, registers group, control signal generating module 12, instruction RAM13, write pointer, program counter and command register.
First internal bus 8 receives the quick control command of carrying out of needs that CPU sends.Second internal bus 9 is used to receive the control command according to the program execution that CPU sends.Registers group comprises special function register, and radio frequency register, and the PC register of other functions are used for realizing depositing substantially, promptly deposit the control command that second internal bus 9 receives; First MUX 10 realizes the multiselect one to registers group, and the control command of choosing is sent into the instruction RAM13 or second MUX 11 according to the difference of execution pattern.
Write pointer is used to refer to the address that writes of program code, just adds one whenever RFST writes an instruction to command memory; Program counter is used for calculating the address that the next one will execute instruction; Write pointer and program counter are used for the work of matched orders RAM13, finish instruction storage accurately.
Instruction RAM13 is used to store the control command of being chosen by first MUX 10; MUX 11 is used to realize that instruction that instruction RAM13 is sent here and the alternative that internal bus 8 is sent instruction here operate, and stores command register into; Control signal generating module 12 is decoding operating parts of coprocessor, the instruction that its translation comes from command register, produce control signal corresponding, begin to send data by producing transmission enable signal control transmission part 1, begin to receive data by producing reception enable signal control receiving unit 3, control interrupt identification bit register 4 by generation interruption asserts signal and produce interruption.
The data flow trend of coprocessor 7 inside is described below in conjunction with the execution pattern of coprocessor.Coprocessor has two kinds of execution patterns: quick execution pattern and program execution mode.
Under quick execution pattern, CPU stores in the registers group by the control bit of internal bus 9 with correspondence, by first MUX 10, through second MUX 11 and command register again write control signal generation module 12 carry out fast decoding and execution.Thereby control sends the work of part 1 and receiving unit 2.
Under program execution mode, the instruction of CSMA/CA algorithm is stored in the registers group by internal bus 9, under the cooperation of write pointer and program counter, instruction write instruction RAM13 by MUX 10 by internal bus 8 again, select it 11 to deposit command memory in by multichannel, after obtaining execution command, control signal generating module 12 begins decoding and produces the transmission enable signal and receive enable signal and interrupt signal.
The control signal that coprocessor produces after to command decoder can be controlled and receive and sending module, produces four kinds of operating states as shown in Figure 3: sleep, receive, and send, send acknowledgement frame.Coprocessor is dynamically controlled the shutoff of submodule clock by finishing the switching of these several operating states.Introduce the switching of these several operating states below respectively.
1) sleep state: under this state, the clock of MAC control accelerator inside all submodules except that co-processor module all will stop.When carrying out a TXON (enabling sending module) instruction or RXON (enabling receiver module) instruction, coprocessor leaves sleep state.
2) accepting state and transmit status: coprocessor is carried out a TXON instruction and is entered transmit status, then changes accepting state after a frame is sent completely automatically over to.Coprocessor is carried out a RXON instruction and is entered accepting state, and accepting state is main operating state, still is in accepting state after successfully receiving a frame or frame check failure.
3) send the acknowledgement frame state: under accepting state, when coprocessor is carried out the TACK instruction, enter into this state.Under all working state, when coprocessor was carried out RFOFF (dormancy instruction), MAC entered sleep state.
Example
IEEE802.15.4 agreement CSMA-CA algorithm is the channel contention algorithm when being used for transfer of data between node, three important parameters: NB is arranged, CW and BE, NB, (retreat number of times, promptly retreating with backoff is the number of times of chronomere) in this algorithm; The initial value of NB is 0, when equipment has data to transmit, retreat the time through one section after, send CCA and detect, if detect channel busy, then fall back a period of time at random, the NB value adds 1, in 802.15.4, NB value maximum is defined as 4, when channel still detecting channel after time of delay for busy through 4 times retreat, then abandon this transmission, to avoid excessive expense.CW, (length of collision window, content window length), just retreat the length of time of delay, unit is backoff, and being defined in the MAC parameter attribute storehouse of a back-off periods provided by parameter a Unit Backoff Period, is the time of 20symbol.The initial value of CW is 2, maximum BE, (retreating index, backoff exponent), and span is 0～5, and the default value that 802.15.4 recommends is 3, and maximum is 5.When BE is made as 0, then only carries out primary collision and detect.The CSMA-CA algorithm essence of program executive mode is used Y exactly, two registers of Z are stored BE and NB respectively, number of times with register X storage random back-off, be used for branch's redirect in the implementation algorithm flow process with the condition judgment jump instruction, and utilize overflowing of MAC timer that the minimum time unit that retreats of agreement regulation is set.The instantiation program is seen Fig. 4.
The S-MAC agreement is on IEEE802.11 MAC agreement basis, the sensing network MAC agreement that proposes at the requirement of the saving energy of sensing network, it is periodically intercepted/sleeps working method and reduce the free time and intercept by adopting, and Cycle Length is changeless (as shown in Figure 5).Node still adopts periodic wakeup to intercept in the T-MAC agreement, and different is that sleep and movable time no longer are (as shown in Figure 5) fixed.Programmable timer in the coprocessor can be regulated the chronomere of intercepting and sleeping by bit wide n is set.So the MAC based on the coprocessor design is MAC able to programme.On the basis of CSMA-CA algorithm, the activity-dormancy mechanism support program that increases the S-MAC agreement provides the support to the S-MAC agreement.The program of T-MAC agreement is similar substantially with S-MAC, and both overflow on being provided with of cycle different at timer, and the setting of background register is also different.Instantiation sees Table 1.
Table 1
The present invention not only is confined to above-mentioned embodiment; persons skilled in the art are according to embodiment and the disclosed content of accompanying drawing; can adopt other multiple embodiment to implement the present invention; therefore; every employing project organization of the present invention and thinking; do some simple designs that change or change, all fall into the scope of protection of the invention.
Claims (2)
1, a kind of implement device of wireless sensor network access protocol comprises sending part (1), control section and receiving unit (3); Send part (1) and be used to realize that targeting sequencing and frame separator insert, carry out CRC and calculate, finish frame and send and automatic-answering back device; Receiving unit (3) is used for realizing physical layer is received identification of Frame separator and CRC check, and go forward side by side row address matching check and frame information filter; It is characterized in that: described control section is a coprocessor part (2), comprises interrupt identification bit register (4), tandom number generator (5), MAC timer able to programme (6) and coprocessor (7);
MAC timer able to programme (6) generates the set time by programming, offer coprocessor (7), tandom number generator (5) provides the random time that needs for coprocessor (7), coprocessor (7) is by the signal of internal bus reception from cpu i/f, according to producing control command, control sends part (1), receiving unit (3) and interrupt identification bit register (4), finishes accepting state, the realization of switching controls between the transmit status and CSMA/CA algorithm;
Begin to send data by sending enable signal control transmission part (1) behind the end of operation, begin to receive data by receiving enable signal control receiving unit (3), control interrupt identification bit register (4) by the interruption asserts signal and put interrupt bit, make device be in interrupt status.
2, the implement device of wireless sensor network access protocol according to claim 1, it is characterized in that: coprocessor (7) comprises that coprocessor (7) comprises first, second internal bus (8,9), first, second MUX (10,11), registers group, control signal generating module (12), instruction RAM (13), write pointer, program counter and command register;
Write pointer and program counter are used for the work of matched orders RAM (13), make instruction RAM (13) accurately store the control command of being chosen by first MUX (10);
Second internal bus (9) is used to receive the control command according to the program execution that CPU sends, and be stored in the registers group, first MUX (10) realizes the multiselect one to registers group, and the control command of choosing is sent into instruction RAM (13) or second MUX (11) according to the difference of execution pattern;
First internal bus (8) is used to receive the quick control command of carrying out of needs that CPU sends, second MUX (11) is used for realizing that instruction that instruction RAM (13) is sent here and the alternative that internal bus (8) is sent instruction here operate, and stores in the command register;
The instruction that control signal generating module (12) translation comes from command register produces and sends enable signal, receives enable signal and interrupts asserts signal, sends to respectively and sends part (1), receiving unit (3) and interrupt identification bit register (4).
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102625480A (en) * | 2012-01-16 | 2012-08-01 | 中国科学院上海微系统与信息技术研究所 | Development platform based on medium-high-speed sensor network |
| CN105006122A (en) * | 2015-07-01 | 2015-10-28 | 浙江工业大学 | Wireless interface communication protocol for automatic inspection robot |
| CN107111926A (en) * | 2014-12-17 | 2017-08-29 | 横河电机株式会社 | Data gathering system |
| CN107490440A (en) * | 2017-04-27 | 2017-12-19 | 安徽华脉科技发展有限公司 | It is a kind of based on the multi-functional temp detecting system being wirelessly transferred |
-
2009
- 2009-04-10 CN CN200910061561A patent/CN101521952A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102625480A (en) * | 2012-01-16 | 2012-08-01 | 中国科学院上海微系统与信息技术研究所 | Development platform based on medium-high-speed sensor network |
| CN107111926A (en) * | 2014-12-17 | 2017-08-29 | 横河电机株式会社 | Data gathering system |
| CN107111926B (en) * | 2014-12-17 | 2020-11-13 | 横河电机株式会社 | Data collection system |
| CN105006122A (en) * | 2015-07-01 | 2015-10-28 | 浙江工业大学 | Wireless interface communication protocol for automatic inspection robot |
| CN105006122B (en) * | 2015-07-01 | 2018-07-10 | 浙江工业大学 | A kind of automatic crusing robot wireless interface means of communication |
| CN107490440A (en) * | 2017-04-27 | 2017-12-19 | 安徽华脉科技发展有限公司 | It is a kind of based on the multi-functional temp detecting system being wirelessly transferred |
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