CN101400178A - GSM/TD-SCDMA dual-mode terminal chip having single chip and single DSP construction - Google Patents
GSM/TD-SCDMA dual-mode terminal chip having single chip and single DSP construction Download PDFInfo
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- CN101400178A CN101400178A CNA2007100464063A CN200710046406A CN101400178A CN 101400178 A CN101400178 A CN 101400178A CN A2007100464063 A CNA2007100464063 A CN A2007100464063A CN 200710046406 A CN200710046406 A CN 200710046406A CN 101400178 A CN101400178 A CN 101400178A
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Abstract
The present invention discloses a GSM/TD-SCDMA terminal chip of a single-chip single DSP architecture, which realizes the GSM and TD system programs on a single DSP, thereby reducing the chip area and cost, lowering power consumption and improving the performance of interactive systems. The chip includes: a micro-controller; a single clock generator and crystal vibration; and a single DSP chip. The single DSP chip includes a chip control module, responding GSM frame interrupt and TD frame interrupt in time, distributing system resources to the GSM mode and TD-SCDMA mode, controlling the start-up of the GSM and TD-SCDMA radiofrequency signal, and shielding the GSM timer interruption or TD-SCDMA timer interruption for manually controlling network or single mode terminal; a sleeping mode dual affirmation module, detecting that the GSM and TD-SCDMA are all at a sleeping allowing state for allowing the DSP chip to enter into a sleeping mode; a GSM accelerator and a TD-SCDMA accelerator, for performing auxiliary digital signal processing to GSM and TD-SCDMA under the control of a single DSP. The invention can be applied to the mobile communications field.
Description
Technical field
The present invention relates to a kind of terminal chip of mobile communication, relate in particular to a kind of chip that adopts the GSM/TD-SCDMA dual-mode terminal of single-chip list DSP framework realization.
Background technology
3G (Third Generation) Moblie standard as Chinese independent intellectual property right, TD-SCDMA will begin large-scale networking and commercialization in recent years, but because the network equipment and mobile phone all must be changed, TD-SCDMA needs a period of time just may reach the popularity of existing GSM network.Therefore, in long a period of time, the state that TD network and GSM network all can be in mutual covering, move simultaneously.If same station terminal can insert two class networks, can bring great convenience to the user.In addition, from the angle of operator, in order to keep existing client here, the protection up-front investment can wish that also terminal can support the access of various modes.Therefore, one of the most urgent early stage demand of arranging net that is developed to of dual-mode terminal for TD-SCDMA.
GSM and TD-SCDMA use time-division multiplex technology, and the GSM signal is that base unit is handled with frame (frame), and each frame length is 4.615ms, is divided into 8 time slots (slot), and all slot lengths all equate.And the base unit of TD-SCDMA signal is subframe (sub-frame), and each subframe lengths is 5ms, is divided into 7 common time slots (TSO-TS6) and 3 special time slots (DwPTS/G/UpPTS), and its length and structure are as shown in Figure 1.
In the software of terminal is realized, be to locate by the interruption that chip provides to the identification of frame boundaries.Therefore, no matter support TD-SCDMA or gsm communication agreement, it is the timing interruption in cycle that chip all must provide with corresponding frame length.
So-called GSM/TD-SCDMA dual-mode terminal is meant that terminal both supported the TD-SCDMA pattern, also supports the GSM pattern.Dual-mode terminal is divided into dual-mode dual-standby and double-mode single-standby two Terminal Types again.Double-mode and double-standby terminal may be simultaneously operated in TD-SCDMA or two kinds of patterns of GSM at synchronization, and can transmit and receive data under pattern separately simultaneously.Any moment of double-mode single-standby terminal can only be operated under a kind of pattern in TD-SCDMA pattern or the GSM pattern, equally transmits and receive data with the single-mode terminal of associative mode.But still be that business is carried out in the process no matter in the free time, can both be manually and automatically carry out mode switch between TD-SCDMA and the GSM, switch the sub-district gravity treatment and the sub-district that also can be supported in interdepartmental system between TD-SCDMA sub-district and the GSM sub-district.When realizing that the key technology of these functions and difficult point are that terminal resides in any pattern, all need periodic measurement to belong to the adjacent sub-district relevant parameter of another pattern, and optionally carry out sub-district gravity treatment and handoff procedure.This just needs that terminal is done alternately between two kinds of patterns, transfer of data and synchronously, and according to a kind of state of pattern wherein, another pattern is controlled.
Present dual-mode terminal comprises two class designs, and first kind is to use a plurality of chips, realizes GSM and TD-SCDMA function on different chips respectively; Though second kind is used one chip, comprises a plurality of DSP in the chip, is used for supporting GSM and TD-SCDMA pattern respectively, the frame of two patterns interrupts providing on different DSP, and corresponding software also is two separate systems, isolated operation on DSP separately.
Fig. 2 shows the principle of the dual-mode terminal chip of above-mentioned first kind of design.See also Fig. 2, chipset 201 comprises GSM chip 202 and TD-SCDMA chip 203, and the chip of each pattern uses crystal oscillator separately respectively, that is the special-purpose crystal oscillator 205 of GSM and TD-SCDMA crystal oscillator 204 provide clock, produces interruption separately.
Fig. 3 shows the principle of the bimodulus interruption chip of above-mentioned second kind of design.See also Fig. 3, dual-mode terminal chip 301 comprises DSP302 that supports the GSM pattern and the DSP303 that supports the TD-SCDMA pattern.Microcontroller 330 wherein (MCU/ARM, Micro ControllerUnit/Advanced RISC Machines) is the main control unit in the chip 301, by most module co-ordinations of total line traffic control and scheduling chip internal.Chip internal memory 340 is called by microcontroller 330, is used to store the program code and data and the current operation result that are written into.I/O bridge 341 connects chip 301 and external devices, makes chip 301 can control these external devices.DSP (DigitalSignal Processor) is programmable digital signal processor.The DSP302 of responsible GSM pattern and the DSP303 of responsible TD-SCDMA pattern handle respectively through IQ passage ADC314 and carry out the GSM digital signal of analog to digital conversion and the TD-SCDMA digital signal of carrying out the analog to digital conversion by IQ passage ADC324.IQ passage DAC314 and IQ passage DAC324 also are responsible for will be through the DSP302 and 303 signals of handling of two patterns, carry out the digital to analogy conversion, send to the radio frequency control module 316 of GSM pattern and the radio frequency control module 326 of TD-SCDMA pattern respectively, and under the control of these two modules 316,326, signal is launched, this process is to assist under the assisting of DAC (auxiliary figure analog-converted) module 315 and auxiliary DAC (auxiliary figure analog-converted) module 325 of TD-SCDMA at GSM to finish.In addition, GSM DSP302 and TD-SCDMA DSP303 need also usually that GSM accelerator 313 and TD-SCDMA accelerator 323 are auxiliary to carry out Digital Signal Processing, for example finish the big signal processing of some repeated high amounts of calculation.The frame information that GSM time block 311 and TD-SCDMA time block 312 analysis GSM DSP302 and TD-SCDMA DSP303 provide, follow the tracks of GSM and the variation in time of TD-SCDMA signal frame respectively, the timing information with two patterns sends to clock generator 305 respectively.Clock generator 305 can also can use a common crystal oscillator 304 (as shown in Figure 3) for each pattern use crystal oscillator separately.Generate GSM regularly interrupt signal 306 and TD-SCDMA timing interrupt signal 307 respectively by clock generator 305, respectively these two timing interrupt signals are offered the DSP302 of GSM pattern and the DSP303 of TD-SCDMA pattern.
From Fig. 3 and foregoing description as can be seen, the GSM of this scheme and TD-SCDMA pattern are separate basically, and the GSM pattern is used its special-purpose GSM time block 311, data and program storage 312, GSM accelerator 313, IQ passage and ADC/DAC (analog to digital converter/digital to analog converter) 314, auxiliary DAC315 and GSM radio frequency control module 316.And the TD-SCDMA pattern also has its special-purpose TD-SCDMA time block 321, data and program storage 322, TD-SCDMA accelerator 323, IQ passage and ADC/DAC (analog to digital converter/digital to analog converter) 324, auxiliary DAC325 and TD-SCDMA radio frequency control module 326.
Sleep pattern is the mode of operation and the operating state of chip and each module of chip internal.Enter the module of sleep pattern, its power consumption and heat radiation all reduce greatly.Above-mentioned these two schemes, two patterns of GSM and TD-SCDMA are the control of independently sleeping.
Say in essence, two design for scheme thoughts of above-mentioned this all be GSM and TD-SCDMA as the standalone module separate processes, use different hardware to realize.GSM and relatively independent ground of TD-SCDMA separate processes need take more chip area, increase power consumption, and communication just means mutual between hardware module between pattern, and not only complexity but also speed are slower.
Summary of the invention
The objective of the invention is to address the above problem, a kind of GSM/TD-SCDMA dual-mode terminal chip of single-chip list DSP framework is provided, on single DSP, realize GSM and TD system schema simultaneously, reduce chip area, save cost, reduce power consumption, improved the interactive performance between system.
Technical scheme of the present invention is: the invention discloses a kind of GSM/TD-SCDMA dual-mode terminal chip of single-chip list DSP framework, comprising:
Microcontroller is by the module co-ordination of total line traffic control and this dual-mode terminal chip internal of scheduling;
Single clock generator and crystal oscillator, by the frequency division of this crystal oscillator, the GSM that the output generation time can independently be adjusted is interrupt signal and TD-SCDMA timing interrupt signal regularly;
Single dsp chip uses GSM pattern and TD-SCDMA pattern, comprising:
Chip control module, in time response GSM frame interrupts and the interruption of TD frame, be GSM pattern and TD-SCDMA mode assignments system resource, the radiofrequency signal of control GSM and TD-SCDMA starts, and shielding GSM regularly interrupts or TD-SCDMA regularly interrupts with manual selection network or single-mode terminal;
Sleeping mode dual affirmation module detects GSM and TD-SCDMA and all is in when allowing sleep state and makes this dsp chip enter sleep pattern;
GSM accelerator and TD-SCDMA accelerator carry out complementary Digital Signal Processing to GSM and TD-SCDMA under the control of this single dsp chip.
The GSM/TD-SCDMA dual-mode terminal chip of above-mentioned single-chip list DSP framework, wherein, this sleeping mode dual affirmation module comprises:
Regularly start inspection unit, scheduler program regularly starts inspection;
TD-SCDMA pattern sleep state judging unit judges whether the TD-SCDMA pattern allows to enter sleep state;
GSM pattern sleep state judging unit judges whether the GSM pattern allows to enter sleep state;
The DSP unit of sleeping is all judged at this TD-SCDMA pattern sleep state judging unit and this GSM pattern sleep state judging unit and to be allowed to enter that this dsp chip of control enters sleep state under the dormant situation;
Microcontroller sleep state judging unit judges whether this microcontroller enters sleep state;
The chip sleep unit is in sleep state and this this controller of microcontroller sleep state judgment unit judges at this dsp chip and has entered that whole this dual-mode terminal chip of control enters sleep state under the dormant situation.
The GSM/TD-SCDMA dual-mode terminal chip of above-mentioned single-chip list DSP framework, wherein, this chip control module comprises:
GSM interrupts pretreatment unit, and the GSM pattern is anticipated;
TD-SCDMA interrupts pretreatment unit, and the TD-SCDMA pattern is anticipated;
The priority control unit according to the current state of GSM and two patterns of TD-SCDMA and separately to the demand of resources of chip, arranges the execution order of these two patterns can both obtain enough system resource to guarantee GSM and TD-SCDMA pattern;
The GSM processing unit receives the control information of this priority control unit output, handles the digital signal of GSM data pattern, sends the GSM radio-frequency (RF) control signal;
The TD-SCDMA processing unit receives the control information of this priority control unit output, handles the digital signal of TD-SCDMA data pattern, sends the TD radio-frequency (RF) control signal.
The GSM/TD-SCDMA dual-mode terminal chip of above-mentioned single-chip list DSP framework, wherein, this GSM interrupts pretreatment unit and judges whether to be provided with and need interrupt to realize the function of TD-SCDMA single-mode terminal by shielding GSM, interrupt if need then mask GSM, if do not need the preliminary treatment result of then GSM being interrupted to pass to this priority control unit.
The GSM/TD-SCDMA dual-mode terminal chip of above-mentioned single-chip list DSP framework, wherein, this TD-SCDMA interrupts pretreatment unit and judges whether to be provided with and need interrupt to realize the function of GSM single-mode terminal by shielding TD-SCDMA, interrupt if need then mask TD-SCDMA, if do not need the preliminary treatment result of then TD-SCDMA being interrupted to pass to this priority control unit.
The GSM/TD-SCDMA dual-mode terminal chip of above-mentioned single-chip list DSP framework, wherein, this dual-mode terminal chip also comprises:
The single radio frequency control module, receive the TD radio-frequency (RF) control signal that GSM radio-frequency (RF) control signal that this GSM processing unit sends and this TD-SCDMA processing unit send and launch by the GSM/TD-SCDMA radio frequency control interface on this dsp chip, carry out the radio-frequency receiving-transmitting of GSM pattern and TD-SCDMA pattern.
The GSM/TD-SCDMA dual-mode terminal chip of above-mentioned single-chip list DSP framework, wherein, the cycle that this GSM regularly interrupts is 4.615ms, the cycle that this TD-SCDMA regularly interrupts is 5ms.
The present invention contrasts prior art following beneficial effect: the present invention has adopted the design of single-chip list DSP, comprises two kinds of employed hardware accelerators of system of GSM and TD-SCDMA on single DSP, makes it can concurrent working.Use same crystal oscillator to produce GSM and regularly interrupt regularly interrupting with TD-SCDMA and using unified auto frequency deviation adjustment (AFC) to follow the tracks of, two regularly interrupt inputing to single DSP, and two time locations that interrupt producing can independently be regulated.Simultaneously, GSM/TD-SCDMA RF (radio frequency) control interface that the last design of DSP can be used simultaneously is so that chip can be controlled two kinds of transmitting-receiving operations under the pattern simultaneously.The present invention adopts sleeping mode dual affirmation module, makes dsp chip enter sleep pattern when detecting when GSM and TD-SCDMA are in the state that allows sleep.The present invention also adopts chip control module in time to respond the interruption of GSM frame and the TD frame interrupts, and is GSM pattern and TD-SCDMA pattern reasonable distribution system resource.The contrast prior art because the present invention uses unified software and hardware structure to handle two kinds of wireless communication modules, makes the system module sum tail off, chip area reduces, production cost reduces, overall power consumption descends.Simultaneously because the communication between two kinds of systems does not need to do the mutual of DSP or chip chamber, make that the synchronous speed of data transmission period is faster, resource consumption still less, implementation efficiency is higher.
Description of drawings
Fig. 1 is the schematic diagram of TD-SCDMA structure of time slot.
Fig. 2 is the schematic diagram of existing a kind of dual-mode terminal chip.
Fig. 3 is the schematic diagram of existing another kind of dual-mode terminal chip.
Fig. 4 is the schematic diagram of the GSM/TD-SCDMA dual-mode terminal chip embodiment of single-chip list DSP framework of the present invention.
Fig. 5 is the schematic diagram of the embodiment of sleeping mode dual affirmation module of the present invention.
Fig. 6 is the schematic diagram of the embodiment of chip control module of the present invention.
Embodiment
The present invention will be further described below in conjunction with drawings and Examples.
Fig. 4 shows the principle of embodiment of the GSM/TD-SCDMA dual-mode terminal chip of single-chip list DSP framework of the present invention.See also Fig. 4, dual-mode terminal chip 401 comprises: microcontroller (MCU/ARM, Micro Controller Unit/Advanced RISC Machines) 430, chip internal memory 440, I/O bridge 441, single dsp chip 402, clock generator 404 and crystal oscillator 403, data and program storage 425, GSM time block 442, TD-SCDMA time block 443, GSM accelerator 413, TD-SCDMA accelerator 423, sleeping mode dual affirmation module, be responsible for the IQ passage ADC/DAC414 of GSM radiofrequency signal, be responsible for the IQ passage ADC/DAC424 of TD-SCDMA radiofrequency signal, radio frequency control module 416, auxiliary DAC409.
Microcontroller 430 is by most module co-ordinations of total line traffic control and these dual-mode terminal chip 401 inside of scheduling.Chip internal memory 440 is called by microcontroller 430, is used to store the program code and data and the current operation result that are written into.I/O bridge 441 connects chip 401 and external devices, makes chip 401 can control these external devices.Only be provided with a dsp chip 402 in the chip 401, handle simultaneously through IQ passage ADC414 and carry out the GSM digital signal of analog to digital conversion and the TD-SCDMA digital signal of carrying out the analog to digital conversion through IQ passage ADC424.IQ passage DAC414 and IQ passage DAC424 are responsible for the signal that dsp chip 402 is handled is carried out the digital to analogy conversion, send to radio frequency control module 416, under the control of this module 416 signal are launched.Radio frequency control module 416 is controlled by this dsp chip 402.This process is to finish down the auxiliary of auxiliary DAC409.Dsp chip 402 is controlled GSM and the employed hardware accelerator 413 of two kinds of patterns of TD-SCDMA and 423 simultaneously, but makes its concurrent working.Introduce the interruption that two fixed cycles produce from clock generator 404, one of them is to be that the GSM frame of 4.615ms regularly interrupts 405 in the cycle, another is to be that the TD-SCDMA frame of 5ms regularly interrupts 406 in the cycle, and these two time locations that interrupt producing can independently be regulated.Both use same crystal oscillator 403 frequency divisions to produce, and use unified AFC (auto frequency deviation adjustment) 409 to follow the tracks of.
Be provided with chip control module (not shown) in dsp chip 402, the principle of chip control module sees also Fig. 6.Chip control module comprises that GSM interrupts pretreatment unit 601, TD-SCDMA pretreatment unit 602, priority control unit 603, GSM processing unit 604 and TD-SCDMA processing unit 605.
Fig. 5 shows the principle of sleeping mode dual affirmation module, sees also Fig. 7.Sleeping mode dual affirmation module comprises: regular check unit 500, TD-SCDMA pattern sleep state judging unit 501, GSM pattern sleep state judging unit 502, DSP sleep unit 503, microcontroller sleep state judging unit 504, chip sleep unit 505.
The foregoing description provides to those of ordinary skills and realizes or use of the present invention; those of ordinary skills can be under the situation that does not break away from invention thought of the present invention; the foregoing description is made various modifications or variation; thereby protection scope of the present invention do not limit by the foregoing description, and should be the maximum magnitude that meets the inventive features that claims mention.
Claims (7)
1, a kind of GSM/TD-SCDMA dual-mode terminal chip of single-chip list DSP framework comprises:
Microcontroller is by the module co-ordination of total line traffic control and this dual-mode terminal chip internal of scheduling;
Single clock generator and crystal oscillator, by the frequency division of this crystal oscillator, the GSM that the output generation time can independently be adjusted is interrupt signal and TD-SCDMA timing interrupt signal regularly;
Single dsp chip uses GSM pattern and TD-SCDMA pattern, comprising:
Chip control module, in time response GSM frame interrupts and the interruption of TD frame, be GSM pattern and TD-SCDMA mode assignments system resource, the radiofrequency signal of control GSM and TD-SCDMA starts, and shielding GSM regularly interrupts or TD-SCDMA regularly interrupts with manual selection network or single-mode terminal;
Sleeping mode dual affirmation module detects GSM and TD-SCDMA and all is in when allowing sleep state and makes this dsp chip enter sleep pattern;
GSM accelerator and TD-SCDMA accelerator carry out complementary Digital Signal Processing to GSM and TD-SCDMA under the control of this single dsp chip.
2, the GSM/TD-SCDMA dual-mode terminal chip of single-chip list DSP framework according to claim 1 is characterized in that this sleeping mode dual affirmation module comprises:
Regularly start inspection unit, scheduler program regularly starts inspection;
TD-SCDMA pattern sleep state judging unit judges whether the TD-SCDMA pattern allows to enter sleep state;
GSM pattern sleep state judging unit judges whether the GSM pattern allows to enter sleep state;
The DSP unit of sleeping is all judged at this TD-SCDMA pattern sleep state judging unit and this GSM pattern sleep state judging unit and to be allowed to enter that this dsp chip of control enters sleep state under the dormant situation;
Microcontroller sleep state judging unit judges whether this microcontroller enters sleep state;
The chip sleep unit is in sleep state and this this controller of microcontroller sleep state judgment unit judges at this dsp chip and has entered that whole this dual-mode terminal chip of control enters sleep state under the dormant situation.
3, the GSM/TD-SCDMA dual-mode terminal chip of single-chip list DSP framework according to claim 1 and 2 is characterized in that this chip control module comprises:
GSM interrupts pretreatment unit, and the GSM pattern is anticipated;
TD-SCDMA interrupts pretreatment unit, and the TD-SCDMA pattern is anticipated;
The priority control unit according to the current state of GSM and two patterns of TD-SCDMA and separately to the demand of resources of chip, arranges the execution order of these two patterns can both obtain enough system resource to guarantee GSM and TD-SCDMA pattern;
The GSM processing unit receives the control information of this priority control unit output, handles the digital signal of GSM data pattern, sends the GSM radio-frequency (RF) control signal;
The TD-SCDMA processing unit receives the control information of this priority control unit output, handles the digital signal of TD-SCDMA data pattern, sends the TD radio-frequency (RF) control signal.
4, the GSM/TD-SCDMA dual-mode terminal chip of single-chip list DSP framework according to claim 3, it is characterized in that, this GSM interrupts pretreatment unit and judges whether to be provided with and need interrupt to realize the function of TD-SCDMA single-mode terminal by shielding GSM, interrupt if need then mask GSM, if do not need the preliminary treatment result of then GSM being interrupted to pass to this priority control unit.
5, the GSM/TD-SCDMA dual-mode terminal chip of single-chip list DSP framework according to claim 3, it is characterized in that, this TD-SCDMA interrupts pretreatment unit and judges whether to be provided with and need interrupt to realize the function of GSM single-mode terminal by shielding TD-SCDMA, interrupt if need then mask TD-SCDMA, if do not need the preliminary treatment result of then TD-SCDMA being interrupted to pass to this priority control unit.
6, the GSM/TD-SCDMA dual-mode terminal chip of single-chip list DSP framework according to claim 3 is characterized in that, this dual-mode terminal chip also comprises:
The single radio frequency control module, receive the TD radio-frequency (RF) control signal that GSM radio-frequency (RF) control signal that this GSM processing unit sends and this TD-SCDMA processing unit send and launch by the GSM/TD-SCDMA radio frequency control interface on this dsp chip, carry out the radio-frequency receiving-transmitting of GSM pattern and TD-SCDMA pattern.
7, the GSM/TD-SCDMA dual-mode terminal chip of single-chip list DSP framework according to claim 6 is characterized in that, the cycle that this GSM regularly interrupts is 4.615ms, and the cycle that this TD-SCDMA regularly interrupts is 5ms.
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| CN200710046406A CN100584126C (en) | 2007-09-26 | 2007-09-26 | GSM/TD-SCDMA double-mode terminal chip of single chip single DSP structure |
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| CN200710046406A CN100584126C (en) | 2007-09-26 | 2007-09-26 | GSM/TD-SCDMA double-mode terminal chip of single chip single DSP structure |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102209402A (en) * | 2010-03-31 | 2011-10-05 | 重庆重邮信科通信技术有限公司 | Interface of radio frequency chip and base band chip of multi-mode terminal |
| CN102394665A (en) * | 2011-06-28 | 2012-03-28 | 中兴通讯股份有限公司 | Radio frequency transceiver system and mobile terminal |
| CN103259939A (en) * | 2013-04-12 | 2013-08-21 | 北京创毅讯联科技股份有限公司 | Terminal dormant method and terminal |
| CN106575279A (en) * | 2014-05-29 | 2017-04-19 | 阿尔特拉公司 | An accelerator architecture on a programmable platform |
| CN115379597A (en) * | 2022-08-24 | 2022-11-22 | 浙江清芯微电子有限公司 | RISC-V based HPLC & HRF dual-mode communication chip architecture |
| US11797473B2 (en) | 2014-05-29 | 2023-10-24 | Altera Corporation | Accelerator architecture on a programmable platform |
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2007
- 2007-09-26 CN CN200710046406A patent/CN100584126C/en active Active
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102209402A (en) * | 2010-03-31 | 2011-10-05 | 重庆重邮信科通信技术有限公司 | Interface of radio frequency chip and base band chip of multi-mode terminal |
| CN102209402B (en) * | 2010-03-31 | 2015-10-07 | 重庆重邮信科通信技术有限公司 | The interface of a kind of multimode terminal radio frequency chip and baseband chip |
| CN102394665A (en) * | 2011-06-28 | 2012-03-28 | 中兴通讯股份有限公司 | Radio frequency transceiver system and mobile terminal |
| CN103259939A (en) * | 2013-04-12 | 2013-08-21 | 北京创毅讯联科技股份有限公司 | Terminal dormant method and terminal |
| CN103259939B (en) * | 2013-04-12 | 2015-02-18 | 北京创毅讯联科技股份有限公司 | Terminal dormant method and terminal |
| CN106575279A (en) * | 2014-05-29 | 2017-04-19 | 阿尔特拉公司 | An accelerator architecture on a programmable platform |
| CN106575279B (en) * | 2014-05-29 | 2019-07-26 | 阿尔特拉公司 | Accelerator architecture on programmable platform |
| US11797473B2 (en) | 2014-05-29 | 2023-10-24 | Altera Corporation | Accelerator architecture on a programmable platform |
| CN115379597A (en) * | 2022-08-24 | 2022-11-22 | 浙江清芯微电子有限公司 | RISC-V based HPLC & HRF dual-mode communication chip architecture |
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| CN100584126C (en) | 2010-01-20 |
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