CN101515573A - Conductive structure used for semiconductor integrated circuit - Google Patents
Conductive structure used for semiconductor integrated circuit Download PDFInfo
- Publication number
- CN101515573A CN101515573A CN 200810081039 CN200810081039A CN101515573A CN 101515573 A CN101515573 A CN 101515573A CN 200810081039 CN200810081039 CN 200810081039 CN 200810081039 A CN200810081039 A CN 200810081039A CN 101515573 A CN101515573 A CN 101515573A
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- China
- Prior art keywords
- conductor layer
- layer
- conductive structure
- conductor
- metal layer
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 13
- 239000010410 layer Substances 0.000 claims abstract description 138
- 239000004020 conductor Substances 0.000 claims abstract description 99
- 229910052751 metal Inorganic materials 0.000 claims abstract description 55
- 239000002184 metal Substances 0.000 claims abstract description 55
- 239000011241 protective layer Substances 0.000 claims abstract description 9
- 239000000463 material Substances 0.000 claims description 31
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical group [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 19
- 239000010931 gold Substances 0.000 claims description 19
- 229910052737 gold Inorganic materials 0.000 claims description 19
- 230000003139 buffering effect Effects 0.000 claims description 10
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical group [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical group [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 3
- 239000000956 alloy Substances 0.000 claims description 3
- 229910045601 alloy Inorganic materials 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 239000010936 titanium Substances 0.000 claims description 3
- 229910052719 titanium Inorganic materials 0.000 claims description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 3
- 229910052721 tungsten Inorganic materials 0.000 claims description 3
- 239000010937 tungsten Substances 0.000 claims description 3
- 229910052759 nickel Inorganic materials 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 10
- 238000005516 engineering process Methods 0.000 description 8
- 238000010586 diagram Methods 0.000 description 5
- 238000000034 method Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000004377 microelectronic Methods 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000010301 surface-oxidation reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention relates to a conductive structure used for a semiconductor integrated circuit. The semiconductor integrated circuit comprises a pad and a protective layer which locally covers the pad so as to define an opening area together. The conductive structure can be electrically connected with the pad through the opening area. The conductive structure comprises a lower metal layer, a first conductor layer, a second conductor layer and a conductor covering layer, wherein the first conductor layer is formed on the lower metal layer and electrically connected with the lower metal layer; and the second conductor layer is formed on the first conductor layer and electrically connected with the first conductor layer. Furthermore, the lower metal layer, the first conductor layer and the second conductor layer define a basic lug structure together, and the conductor covering layer is suitable for completely covering the basic lug structure basically.
Description
Technical field
The present invention relates to the conductive structure of semiconductor integrated circuit; Particularly relate to a kind of conductive structure that can prevent this conductive structure surfaces oxidation.
Background technology
The projection technology has been widely used in microelectronics (microelectronics) and micro-system fields such as (micro system), as the electrically connect interface between semiconductor integrated circuit and the circuit board.With circuit board and integrated circuit (integrated circuit; IC) chip be connected to example, integrated circuit (IC) chip can utilize variety of way to be connected with circuit board, and projection is formed in the integrated circuit (IC) chip in the defined open area of the protective layer on the liner, and the pin of liner and circuit board is electrically connected.
In metal species, the gold conductivity best, so encapsulation procedure generally use the gold as bump material, be called golden projection.See also Fig. 1, projection be formed on the liner 101 with protective layer 102 on the open area, this projection is defined jointly by one first conductive layer 104, one second conductive layer 105 and a lower metal layer 103.In this embodiment, the material of first conductor layer 104 and second conductor layer 105 is all gold, and forms in integrated mode.The processing procedure of typical gold projection need form a lower metal layer 103 earlier on liner 101.Lower metal layer 103 except adhesion coating as engagement protrusion and liner 101, usually also with a conductive layer electrically connect, with Fig. 1, be first conductor layer 104, in order to form these projections with electroplating process.Wherein first conductor layer 104 can form respectively or simultaneously, also can utilize same process and material basically with lower metal layer 103, with after forming projection, jointly as the usefulness of conductive media, make projection can be formed at lower metal layer 103 tops smoothly, and by lower metal layer 103 and liner 101 electrically connects.For example, the material of lower metal layer 103 can be selected from titanium, tungsten and its alloy.
Because the unit price of gold is higher, is the economization manufacturing cost, known technology development with gold and other metal combination projections.With projection cube structure shown in Figure 1 is example, and first conductor layer 104 and second conductor layer, 105 employed materials are with different.According to this improvement design, in the present embodiment, first conductor layer 104 accounts for the ratio of whole projection than second conductor layer, 105 height, therefore the material of first conductor layer 104 can be replaced with the slightly poor metal group of golden conductivity.
In some cases, first conductor layer 104 and second conductor layer 105 are easier to produce down golden effect altogether in solid-state state, and make conductivity variation between conductor layer, and then influence the conductivity of whole projection.In order to improve this situation, known technology more adds a buffering conductor layer 106 in first conductor layer 104 and 105 of second conductor layers sometimes, sees also Fig. 2.
Yet no matter be above-mentioned combination projection, or the combination projection that adds resilient coating all has a distinct disadvantage.When conductor layer is non-when being material with the gold, oxidation will take place in its surface easily, and then cause whole projection conductivity to descend even destroy the overall convex block structure.
In view of this, projection is reduced cost and surface that tool is difficult for oxidation is the problem that present industry leads expectation institute desire to solve.
Summary of the invention
One of purpose of the present invention is to provide a kind of conductive structure that is used for the semiconductor integrated circuit.This semiconductor integrated circuit comprises a liner and a protective layer.Local this liner that covers of this protective layer to define an open area, makes conductive structure fit and can pass through this open area, is electric connection with this liner.In addition, this conductive structure more comprises a lower metal layer, one first conductor layer and one second conductor layer, and this three defines a basic projection cube structure jointly.Wherein, shared bigger second conductor layer of volume of first conductor layer is big, so the material of this first conductor layer can select for use the metal group of other non-gold to reduce cost.
A further object of the present invention is to provide a surface to be difficult for the conductive structure of oxidation.Except that above-mentioned feature, this conductor structure more comprises one and covers conductor layer, in order to cover its basic projection cube structure.The material that covers conductor layer is selected from the metal group that is difficult for oxidation, thereby improves in the prior art, the problem of combination lug surface meeting oxidation.
For above-mentioned purpose of the present invention, technical characterictic and advantage can be become apparent, hereinafter be elaborated with preferred embodiment, conjunction with figs..
Description of drawings
Fig. 1 is a schematic diagram of known technology;
Fig. 2 is another schematic diagram of known technology;
Fig. 3 is the schematic diagram of first embodiment of the invention; And
Fig. 4 is the schematic diagram of second embodiment of the invention.
The main element symbol description:
101,301: liner
102,302: protective layer
103,303: lower metal layer
104,304: the first conductor layers
105,305: the second conductor layers
106,307: the buffering conductor layer
303a: the first metal layer
303b: second metal level
306: cover conductor layer
W1: first longitudinal size
W2: second longitudinal size
W3: the 3rd longitudinal size
Embodiment
Fig. 3 is the first embodiment of the present invention, and it is a kind of conductive structure that is used for the semiconductor integrated circuit.This semiconductor integrated circuit comprises a liner 301 and a protective layer 302.The protective layer 302 local liners 301 that cover to define an open area, make conductive structure suitably to be electric connection by this open area and this liner 301.Generally speaking, this open area promptly forms when semiconductor integrated circuit is finished, in order to follow-up formation conductive structure.
In the present embodiment, conductive structure comprises a lower metal layer 303, one first conductor layer 304, one second conductor layer 305 and covers conductor layer 306.The person of noting, except that covering conductor layer 306, the method that forms conductive structure is understood by knowing this operator, for example with plating mode, utilize lower metal layer 303 as conducting medium forming first conductor layer 304 and second conductor layer 305 or the like, in this superfluous words no longer.
Lower metal layer 303 part at least is formed in this open area, to cover this open area fully.This first conductor layer 304 then be formed on the lower metal layer 303 and be electrically connect, and have the first longitudinal size W1.Second conductor layer 305 be formed on first conductor layer 304 and be electric connection, and have the second longitudinal size W2.Wherein, the first longitudinal size W1 is not less than the second longitudinal size W2 basically, and this design considers that can use unit price in bigger conductor layer (i.e. first conductor layer 304) makes than the low material of gold, to save manufacturing cost.This lower metal layer 303, first conductor layer 304 and second conductor layer 305 define a basic projection cube structure jointly, this covering conductor layer 306 is suitable to cover basic projection cube structure fully, comprise the side that covers lower metal layer 303, to avoid basic projection cube structure to produce oxidation, reach the effect of firm this basic projection cube structure simultaneously.
In the present embodiment, this lower metal layer 303 more comprises the first metal layer 303a and the second metal level 303b.The first metal layer 303a is formed on the liner 301, and the second metal level 303b is formed on the first metal layer 303a, and both adopt different materials.In other embodiments, this lower metal layer 303 also can only be made of a metal level.Further, select about the material of the first metal layer 303a and the second metal level 303b, need be on the material of first conductor layer 304 formed thereon be selected decide, detailed in hereinafter.
About the material among this embodiment, consider the satisfactory electrical conductivity of gold, the material of second conductor layer 305 is a gold, as previously mentioned, can utilize the mode of electrogilding to form.The material of first conductor layer 304 is then selected the conductance copper slightly poorer than gold for use.Therefore, the first metal layer 303a can select the metal of titanium, tungsten and its alloy for use, and the material of the second metal level 303b then can be identical with the material of first conductor layer 304, is copper.
In addition, gold also has the characteristic that is difficult for oxidation, thereby the material of covering conductor layer 306 also may be selected to be gold.And coat the part that whole projection surface metal exposes in the mode of electroless plating (chemical plating).Wherein, cover conductor layer 306 mainly in order to preventing basic projection cube structure oxidation, and increase thickness that covers conductor layer 306 and the conductivity that can't improve projection cube structure basically, so covering conductor layer 306 has an average thickness of 1 micron basically.
By above-mentioned exposure, the present invention only needs to select gold as material in the part of basic projection cube structure, and second conductor layer 305 and covering conductor layer 306 as above-mentioned embodiment can reach the purpose that reduces cost.Simultaneously, coat covering conductor layer 306, can avoid the projection cube structure surface oxidation, and then solve the shortcoming of known technology on basic projection cube structure surface.
See also Fig. 4, be the schematic diagram of second embodiment of the invention.Compare with a last embodiment, main difference place is that a buffering conductor layer 307 is formed between first conductor layer 304 and second conductor layer 305, electrically connects with first conductor layer 304 and second conductor layer 305 respectively.This buffering conductor layer 307 has one the 3rd longitudinal size W3, and the first longitudinal size W1 is not less than the 3rd longitudinal size W3 basically.
The main purpose of buffering conductor layer 307 is total to golden effect in order to prevent that first conductor layer 304 and second conductor layer 305 from producing down in solid-state state, and makes conductivity variation between conductor layer, and then influences the conductivity of whole projection.Among this embodiment, the material of buffering conductor layer 307 is a nickel.Other of second embodiment partly with to have the part of similar elements label identical among first embodiment, repeat no more.
Similarly, according to a second embodiment of the present invention, add buffering conductor layer 307 and can avoid first conductor layer 304 and second conductor layer, 305 conductivity to be comparable to the phenomenon that gold takes place to be total to.Cover conductor layer 306 simultaneously and can protect the part of the easy oxidation of lug surface, and then improve the defective of known technology.
The above embodiments only are used for exemplifying enforcement aspect of the present invention, and explain technical characterictic of the present invention, are not to be used for limiting protection category of the present invention.Any be familiar with this operator can unlabored change or the arrangement of the isotropism scope that all belongs to the present invention and advocated, the scope of the present invention should be as the criterion with claims.
Claims (9)
1. conductive structure that is used for the semiconductor integrated circuit, wherein this semiconductor integrated circuit comprises a liner and a protective layer, local this liner that covers; to define an open area; this conductive structure is suitable can to pass through this open area, is electric connection with this liner, and this conductive structure comprises:
One lower metal layer, the part is formed in this open area at least;
One first conductor layer has one first longitudinal size, is formed on this lower metal layer, is electrically connect with this lower metal layer;
One second conductor layer has one second longitudinal size, is formed on this first conductor layer, be electric connection with this first conductor layer, and wherein this first longitudinal size is not less than this second longitudinal size basically; And
One covers conductor layer;
Wherein this lower metal layer, first conductor layer and second conductor layer define a basic projection cube structure jointly, and this covering conductor layer is suitable to cover basic projection cube structure basically fully.
2. conductive structure as claimed in claim 1 is characterized in that, the material of this second conductor layer is a gold, material one metal of this first conductor layer, and its conductance gold is low.
3. conductive structure as claimed in claim 2 is characterized in that, the material of this first conductor layer is a copper.
4. conductive structure as claimed in claim 1 is characterized in that, this material that covers conductor layer is a gold.
5. conductive structure as claimed in claim 4 is characterized in that, this covering conductor layer has an average thickness of 1 micron basically.
6. conductive structure as claimed in claim 1, it is characterized in that, this lower metal layer comprises a first metal layer and one second metal level, this the first metal layer is formed on this liner, this second metal level is formed on this first metal layer, and the material of this first metal layer is different with the material of this second metal level.
7. conductive structure as claimed in claim 6 is characterized in that, the material of this first metal layer is selected from the group of titanium, tungsten and its alloy, and the material of this second metal level is identical with the material of this first conductor layer.
8. conductive structure as claimed in claim 1, it is characterized in that, more comprise a buffering conductor layer, form between this first conductor layer and this second conductor layer, be electrically connect with this first conductor layer and this second conductor layer, this buffering conductor layer has one the 3rd longitudinal size, and this first longitudinal size is not less than the 3rd longitudinal size basically.
9. conductive structure as claimed in claim 8 is characterized in that, the material of this buffering conductor layer is a nickel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810081039 CN101515573B (en) | 2008-02-22 | 2008-02-22 | Conductive structure used for semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810081039 CN101515573B (en) | 2008-02-22 | 2008-02-22 | Conductive structure used for semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101515573A true CN101515573A (en) | 2009-08-26 |
| CN101515573B CN101515573B (en) | 2011-12-28 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810081039 Expired - Fee Related CN101515573B (en) | 2008-02-22 | 2008-02-22 | Conductive structure used for semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101515573B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103167725A (en) * | 2011-12-16 | 2013-06-19 | 元太科技工业股份有限公司 | Three-dimensional circuit structure and semiconductor element |
| CN106876351A (en) * | 2017-03-01 | 2017-06-20 | 西安电子科技大学 | The metal interconnection structure and preparation method of a kind of radiofrequency power semiconductor device |
| CN112861464A (en) * | 2021-03-16 | 2021-05-28 | 上海壁仞智能科技有限公司 | Design method of integrated circuit chip and integrated circuit chip |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4327656B2 (en) * | 2004-05-20 | 2009-09-09 | Ｎｅｃエレクトロニクス株式会社 | Semiconductor device |
-
2008
- 2008-02-22 CN CN 200810081039 patent/CN101515573B/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103167725A (en) * | 2011-12-16 | 2013-06-19 | 元太科技工业股份有限公司 | Three-dimensional circuit structure and semiconductor element |
| CN103167725B (en) * | 2011-12-16 | 2015-08-12 | 元太科技工业股份有限公司 | three-dimensional circuit structure and semiconductor element |
| CN106876351A (en) * | 2017-03-01 | 2017-06-20 | 西安电子科技大学 | The metal interconnection structure and preparation method of a kind of radiofrequency power semiconductor device |
| CN106876351B (en) * | 2017-03-01 | 2019-04-23 | 西安电子科技大学 | A kind of the metal interconnection structure and production method of radiofrequency power semiconductor device |
| CN112861464A (en) * | 2021-03-16 | 2021-05-28 | 上海壁仞智能科技有限公司 | Design method of integrated circuit chip and integrated circuit chip |
| CN112861464B (en) * | 2021-03-16 | 2022-08-16 | 上海壁仞智能科技有限公司 | Design method of integrated circuit chip and integrated circuit chip |
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| Publication number | Publication date |
|---|---|
| CN101515573B (en) | 2011-12-28 |
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Granted publication date: 20111228 |