CN101510780A - Device for generating CRC code and method for constructing and generating checkout code - Google Patents

Abstract

The invention relates to the field of transmission data inspection, in particular to a CRC check code generation technology which adopts parallel circuits to realize low cost. The invention discloses a cyclic redundancy check code generation device and a method for establishing and generating the check codes, and the characteristic polynomial of the device is: g(x) equals to x<n> plus * bkx<k> plus 1. The device has t parallel input ends and comprises m phase inverters N0-Nm-1, n triggers R0-Rn-1 and q exclusive-or gates Y0-Yq-1; m is determined by an exclusive-or relational expression: NOR0-NORn-1; input ends of the phase inverters N0-N<m-1> are respectively connected with input ends of the device corresponding to each input data reversed in the exclusive-or relational expression NOR0-NOR<n-1>; q is determined by the number of multidata element relational expressions in the exclusive-or relational expression NOR0-NORn-1; the connections of the output ends of the phase inverters N0-Nm-1, and the triggers R0-Rn-1 and the exclusive-or gates Y0-Yq-1 are determined according to the exclusive-or relational expression NOR0-NORn-1. As the phase inverters are added at a plurality of input ends of the parallel circuits, the phase inverters connected with each trigger in the parallel circuits can be saved, thus saving large quantity of phase inverters and reducing hardware cost.

Description

The method of a kind of cyclic redundancy check code generation apparatus and structure thereof, generation check code

Technical field

The present invention relates to transmit the data check field, relate in particular to and adopt parallel circuit to realize CRC check sign indicating number generation technique cheaply.

Background technology

CRC (Cyclic Redundancy Code, cyclic redundancy check (CRC) code) is a kind of error check code the most frequently used in the data communication, and it can find to transmit single double bit error, odd number mistake in the data, and length is less than the continuous mistake of CRC progression.

The principle of cyclic redundancy check method is as follows:

Any one code of being made up of bit string can be only corresponding one by one with the multinomial of ' 1 ' value for ' 0 ' with a coefficient, and for example: the multinomial of code 110111 correspondences is X ⁵+ X ⁴+ X ²+ X+1.

If the multinomial of the data correspondence that transmit leg will send is V (x);

Transmit leg and recipient arrange a proper polynomial g (x), and the high order power of establishing this proper polynomial is R;

Add R 0 at the end of the data that will send, then its corresponding multinomial is M (x)=x ^RV (x);

Divided by g (x), obtain discussing Q (x) and residue R (x) with M (x), then M (x)=Q (x) g (x)+R (x); The pairing code value step-by-step of residue R (x) negate is the CRC check code value.

Make T (x)=M (x)+R (x), transmit leg sends the pairing data of T (x);

If the multinomial of the data correspondence that the recipient receives be T ' (x), (x) divided by g (x), if residue is 0 (or constant of setting), then the recipient praises and receives the data that transmit leg sends with T '; Otherwise, think the reception mistake.Thereby reach the purpose that the information flow that receives is carried out verification.

Obtain the CRC check sign indicating number by hardware circuit, can accelerate the computational speed of CRC check sign indicating number.Usually can adopt serial or parallel two kinds of circuit to generate the CRC check sign indicating number.Proper polynomial as shown in Figure 1 is g (x)=x ¹⁶+ x ¹²+ x ⁵+ 1, generate the serial circuit of 16 CRC check sign indicating numbers, wherein, N0-N15 is inverter (a logic negate circuit), after all information flows are all imported from the input serial, the output valve of register (or trigger) R15-R0 is residue, after the step-by-step negate, just obtains 16 CRC check sign indicating number.

And proper polynomial g as shown in Figure 2 (x)=x ¹⁶+ x ¹²+ x ⁵+ 1, generates 8 grades of parallel circuits (being the parallel 8 grades of circuit of CRC-CCITT16) of 16 CRC check sign indicating numbers, wherein, N0-N15 is inverter (a logic negate circuit), Y0-Y15 is an XOR gate, D0-D7 is parallel input, the output valve of register (or trigger) R15-R0 is residue, after the step-by-step negate, just obtains 16 CRC check sign indicating number.According to CCITT (International Consultative Committee for Telephone and Telegraph, Consultative Committee on International Telephone and Telegraph (CCITT)) regulation, the reset values of trigger is 1 entirely in the parallel circuit of the prior art of generation CRC-CCITT16 type checking sign indicating number.

Because circuit shown in Figure 2 can be from the parallel input stream of D0-D7, then to generate the speed of CRC check sign indicating number can be 8 times of circuit among Fig. 1 to this parallel circuit.Therefore, the speed of parallel circuit generation CRC check sign indicating number is greater than serial circuit.

The present inventor finds that the inverter that the parallel circuit of the generation CRC check sign indicating number of prior art adopts is more, hardware cost is higher, it is bigger to take circuit space.

Summary of the invention

The embodiment of the invention provides the method for a kind of cyclic redundancy check code generation apparatus and structure thereof, generation check code, in order to reduce the cost of the parallel circuit that generates the CRC check sign indicating number.

A kind of cyclic redundancy check code generation apparatus, the proper polynomial of described cyclic redundancy check (CRC) code is $g\left(x\right)=x^n+\underset{k=1}{\overset{k=n-1}{\mathrm{\&Sigma;}}}{b}_k{x}^k+1,$ Wherein n is a natural number, b _kValue is 0 or 1, and described device has t parallel input I ₀-I _T-1, described device comprises: m inverter N ₀-N _M-1, a n trigger R ₀-R _N-1, and q XOR gate Y ₀-Y _Q-1

Described m is by XOR relational expression NOR ₀-NOR _N-1In the first negate number determine; Described XOR relational expression NOR ₀-NOR _N-1Be respectively and calculate C ₀ ^(t)-C _N-1 ^(t)Equation the right equivalent XOR relational expression; Described XOR relational expression refers to the relational expression that comprises XOR and negate relational operator at the most;

Calculate C ₀ ^(t)-C _N-1 ^(t)Equation determine according to first recurrence formula:

Wherein, r is the integer between [2, t]; Data element D ₀-D _T-1The input I of the corresponding described device of difference ₀-I _T-1At D ₀-D _T-1In if w data element arranged at XOR relational expression NOR ₀-NOR _N-1Middle negate, the then described first negate number is w; And m inverter N ₀-N _M-1The data element of respectively corresponding each negate;

C in described first recurrence formula ₀ ⁽¹⁾-C _N-1 ⁽¹⁾Value, determine by second formula:

C in described second formula ₀-C _N-1The corresponding trigger R of difference ₀-R _N-1Output;

If at XOR relational expression NOR ₀-NOR _N-1Middle existence～D _p, D then _pThe input and the D of corresponding inverter _pCorresponding input end I _pLink to each other; Described p is that span is 0 to t-1 integer;

Described q is by XOR relational expression NOR ₀-NOR _N-1The number of middle multidata element XOR relational expression is determined; And XOR gate Y ₀-Y _Q-1Respectively corresponding each multidata element XOR relational expression; Described multidata element XOR relational expression refers to the XOR relational expression that has an XOR relational operator at least;

Described inverter N ₀-N _M-1Output, trigger R ₀-R _N-1With XOR gate Y ₀-Y _Q-1Connection according to XOR relational expression NOR ₀-NOR _N-1Determine.

Described inverter N ₀-N _M-1Output, trigger R ₀-R _N-1With XOR gate Y ₀-Y _Q-1Connection according to XOR relational expression NOR ₀-NOR _N-1Determine, be specially:

If NOR _jBe multidata element XOR relational expression, then NOR _jThe output and the trigger R of corresponding XOR gate _jInput link to each other, the connection of this XOR gate input is then according to NOR _jDetermine;

If NOR _jNot multidata element XOR relational expression, then trigger R _jThe connection of input is then according to NOR _jDetermine;

Described j is that span is 0 to n-1 integer.

With NOR _jThe connection of the input of corresponding XOR gate is according to NOR _jDetermine, be specially:

If NOR _jIn have C _i, then this XOR gate input and trigger R _iOutput link to each other; Described i is that span is 0 to n-1 integer;

If NOR _jIn have the D of negate _l, then this XOR gate input and D _lThe output of corresponding inverter links to each other;

If NOR _jThe middle D that does not have negate that exists _l, the input I of this XOR gate input and described device then _lLink to each other; Described l is that span is 0 to t-1 integer.

Described trigger R _jThe connection of input is according to NOR _jDetermine, be specially:

If NOR _jIn have C _i, trigger R then _jInput and trigger R _iOutput link to each other; Described i is that span is 0 to n-1 integer.

Described trigger R ₀-R _N-1Reset values all be 0 or all be 1.

A kind of method by said apparatus generation cyclic redundancy check (CRC) code comprises:

With the parallel input I of information code from described device ₀-I _T-1Parallel input;

After described input input, the cyclic redundancy check (CRC) code of described information code is formed in the output of each trigger in all information codes.

A kind of method that makes up cyclic redundancy check code generation apparatus, the proper polynomial of described cyclic redundancy check (CRC) code is $g\left(x\right)=x^n+\underset{k=1}{\overset{k=n-1}{\mathrm{\&Sigma;}}}{b}_k{x}^k+1,$ Wherein n is a natural number, b _kValue is 0 or 1, and described device has t parallel input I ₀-I _T-1, described method comprises:

Determine the number m of the inverter of described device; Described m is by XOR relational expression NOR ₀-NOR _N-1In the first negate number determine; Described XOR relational expression NOR ₀-NOR _N-1Be respectively and calculate C ₀ ^(t)-C _N-1 ^(t)Equation the right equivalent XOR relational expression; Described XOR relational expression refers to the relational expression that comprises XOR and negate relational operator at the most;

Calculate C ₀ ^(t)-C _N-1 ^(t)Equation determine according to first recurrence formula:

Wherein, r is the integer between [2, t]; Data element D ₀-D _T-1The input I of the corresponding described device of difference ₀-I _T-1At D ₀-D _T-1In if w data element arranged at XOR relational expression NOR ₀-NOR _N-1Middle negate, the then described first negate number is w; And m inverter N ₀-N _M-1The data element of respectively corresponding each negate;

C in described first recurrence formula ₀ ⁽¹⁾-C _N-1 ⁽¹⁾Value, determine by second formula:

C in described second formula ₀-C _N-1The corresponding trigger R of difference ₀-R _N-1Output;

If at XOR relational expression NOR ₀-NOR _N-1Middle existence～D _p, D then _pThe input and the D of corresponding inverter _pCorresponding input end I _pLink to each other; Described p is that span is 0 to t-1 integer;

Determine the number q of the XOR gate of described device; Described q is by XOR relational expression NOR ₀-NOR _N-1The number of middle multidata element XOR relational expression is determined; And q XOR gate Y ₀-Y _Q-1Respectively corresponding each multidata element XOR relational expression; Described multidata element XOR relational expression refers to the XOR relational expression that has an XOR relational operator at least;

According to described XOR relational expression NOR ₀-NOR _N-1Determine described inverter N ₀-N _M-1Output, trigger R ₀-R _N-1With XOR gate Y ₀-Y _Q-1Connection.

A kind of cyclic redundancy check code generation apparatus has 8 parallel input I0-I7, comprising: 4 inverter N0-N3,16 XOR gate Y0-Y15,16 trigger R0-R15;

The input of described inverter N0-N3 links to each other with described input I0-I3 respectively;

The output of described XOR gate Y0-Y15 links to each other with the input of trigger R0-R15 respectively;

Each input of XOR gate Y0 links to each other with the output of inverter N3, the output of input I7, trigger R8, the output of trigger R12 respectively;

Each input of XOR gate Y1 links to each other with the output of inverter N2, the output of input I6, trigger R9, the output of trigger R13 respectively;

Each input of XOR gate Y2 links to each other with the output of inverter N1, the output of input I5, trigger R10, the output of trigger R14 respectively;

Each input of XOR gate Y3 links to each other with the output of inverter N0, the output of input I4, trigger R11, the output of trigger R15 respectively;

Each input of XOR gate Y4 links to each other with the output of input I3, trigger R12 respectively;

Each input of XOR gate Y5 respectively with input I2, I3, I7, and the output of trigger R8, R12, R13 links to each other;

Each input of XOR gate Y6 respectively with input I1, I2, I6, and the output of trigger R9, R13, R14 links to each other;

Each input of XOR gate Y7 respectively with input I0, I1, I5, and the output of trigger R10, R14, R15 links to each other;

Each input of XOR gate Y8 respectively with input I0, I4, and the output of trigger R0, R11, R15 links to each other;

Each input of XOR gate Y9 links to each other with the output of inverter N3, the output of trigger R1, the output of trigger R12 respectively;

Each input of XOR gate Y10 links to each other with the output of inverter N2, the output of trigger R2, the output of trigger R13 respectively;

Each input of XOR gate Y11 links to each other with the output of inverter N1, the output of trigger R3, the output of trigger R14 respectively;

Each input of XOR gate Y12 respectively with output, input I3, the I7 of inverter N0, and the output of trigger R4, R8, R12, R15 links to each other;

Each input of XOR gate Y13 respectively with input I2, I6, and the output of trigger R5, R9, R13 links to each other;

Each input of XOR gate Y14 respectively with input I1, I5, and the output of trigger R6, R10, R14 links to each other;

Each input of XOR gate Y15 respectively with input I0, I4, I7, and the output of trigger R11, R15 links to each other.

The parallel circuit of the generation CRC check sign indicating number of the embodiment of the invention is owing to some inputs at parallel circuit have increased inverter, the inverter that thereby each trigger in the parallel circuit can be connected removes, thereby saved a large amount of inverters, simplified CRC check sign indicating number parallel circuit, reduced hardware cost.

Description of drawings

Fig. 1 is the serial circuit schematic diagram of 16 CRC check sign indicating numbers of generation of prior art;

Fig. 2 is 8 grades of parallel circuit schematic diagrames of 16 CRC check sign indicating numbers of generation of prior art;

Fig. 3 is the serial circuit schematic diagram of 16 CRC check sign indicating numbers of generation of the embodiment of the invention;

Fig. 4 is 8 grades of parallel circuit schematic diagrames of 16 CRC check sign indicating numbers of generation of the embodiment of the invention;

Fig. 5 is the parallel circuit construction method flow chart of the generation CRC check sign indicating number of the embodiment of the invention.

Embodiment

Concrete scheme is told about with 8 grades of parallel circuits of the check code of generation CRC-CCITT16 type by embodiment of the invention elder generation, extends to other parallel circuit by this parallel circuit again.

The proper polynomial of CRC check sign indicating number can be expressed as $g\left(x\right)=x^n+\underset{k=1}{\overset{k=n-1}{\mathrm{\&Sigma;}}}{b}_k{x}^k+1,$ Wherein n is a natural number, b _kValue is 0 or 1.

When the n value is 16, b ₁-b ₄, b ₆-b ₁₁, b ₁₃-b ₁₅Value is 0, b ₁₆, b ₁₂, b ₅Value is 1 o'clock, and then the proper polynomial of CRC check sign indicating number is g (x)=x ¹⁶+ x ¹²+ x ⁵+ 1, i.e. the proper polynomial of the check code of CRC-CCITT16 type.

As shown in Figure 3, one of the correspondence that provides of the embodiment of the invention concrete serial circuit that generates CRC-CCITT16 type checking sign indicating number comprises: 3 trigger group (DG ₁-DG ₃), XOR gate (Y1 and Y2), inverter (N0), biconditional gate (Y0).

DG wherein ₁Corresponding to monomial x ⁵, DG ₂Corresponding to monomial x ¹², DG ₃Corresponding to monomial x ¹⁶The reset values of each trigger in the trigger group can be 0 according to actual conditions to the definition of CRC check sign indicating number, also can be 1.For example, the reset values that generates the trigger in the circuit of check code of CRC-CCITT16 type for the embodiment of the invention is 0.

DG ₁Trigger number in the trigger group is 5; DG ₂Trigger number in the trigger group is 12-5=7; DG ₃Trigger number in the trigger group is 16-12=4;

At DG ₁～DG ₃Be serially connected with XOR gate Y1, Y2 between the trigger group.And DG ₁-DG ₃The serial connection sequence of trigger group is connected in series according to the sequence number of trigger group, and just, serial connection sequence is DG ₁, DG ₂, DG ₃

Inverter, its output and DG ₁The input of trigger group links to each other.

Biconditional gate, an one input is the input of described CRC check code generation circuit, another input and DG ₃The output of trigger group links to each other, and its output links to each other with the input of described inverter and an input of each XOR gate (Y1 and Y2).

Information code is from the input of as shown in Figure 3 CRC check code generation circuit, an input that is biconditional gate is imported successively, then in all information codes after the input of described input, the output of each trigger of trigger group is the CRC check sign indicating number after the residue negate of information code.

Because circuit shown in Figure 3 has increased an inverter at input, then can remove the inverter that each trigger output connects, thereby save hardware resource than the serial circuit of prior art.

The CRC check sign indicating number that the CRC check sign indicating number that the following describes the output of embodiment of the invention CRC check code generation circuit shown in Figure 3 and prior art CRC check code generation circuit shown in Figure 1 is exported is identical:

In circuit as shown in Figure 3, suppose that the reset values (being initial value) of each trigger is C0-C15, owing to the reset values of the reset values and the prior art of each trigger trigger shown in Figure 1 is opposite, then the initial value of each trigger in Fig. 1 circuit is C0-C15.

After a clock cycle, first data D0 of information code is input to as in Fig. 1, the circuit shown in Figure 3.

Each trigger output valve in Fig. 1, the circuit shown in Figure 3 is as shown in table 1:

Table 1

Can find out directly that from last table after a clock cycle, the value that trigger R1-R4, R6-R11 in the value of trigger R1-R4, the R6-R11 in Fig. 1 circuit and R13-R15 output and Fig. 3 circuit and R13-R15 export is opposite.

And the trigger R0 output valve in Fig. 1 circuit is

, the trigger R0 output valve in Fig. 3 circuit is

According to formula , then have

, so the R0 in Fig. 1 circuit is also opposite with R0 output valve in Fig. 3 circuit.

In like manner, the output valve of R5, the R12 in Fig. 1 circuit is also opposite with the output valve of R5, R12 in Fig. 3 circuit.Therefore, promptly the R0-R15 output valve with Fig. 3 circuit is identical after inverter is reverse for the R0-R15 output valve in Fig. 1 circuit.

Through after the clock cycle, repeat the derivation of last clock cycle again, can find that the R0-R15 output valve is still opposite with the R0-R15 output valve of Fig. 3 circuit in Fig. 1 circuit.

And the like, through N clock cycle, after the N bit data stream had been imported in serial, the R0-R15 output valve was still opposite with the R0-R15 output valve of Fig. 3 circuit in Fig. 1 circuit.And in Fig. 1 circuit the R0-R15 output valve promptly the R0-R15 output valve with Fig. 3 circuit is identical after oppositely through inverter, thereby Fig. 1 obtains identical CRC check sign indicating number with Fig. 3 circuit.

Therefore, the CRC check sign indicating number that generates of the circuit as shown in Figure 3 that provides of the embodiment of the invention is identical with the CRC check sign indicating number of prior art circuit generation as shown in Figure 1.Similarly, the CRC check sign indicating number that other circuit that generates for the method that adopts the embodiment of the invention generates also can be identical with the CRC check sign indicating number that the circuit of prior art generates, no longer various circuit are proved one by one that herein art technology can easyly realize according to the disclosed technology contents of the embodiment of the invention.

Can derive corresponding parallel circuit by serial circuit shown in Figure 3:

Serial circuit shown in Figure 3 trigger R0-R15 output valve after the 1st, 2,4,8 clock cycle is as shown in table 2:

Table 2

Clock	Input	R0	R1	R2	R3	R4	R5	R6	R7	R8	R9	R10	R11	R12	R13	R14	R15
																		0		C0	C1	C2	C3	C4	C5	C6	C7	C8	C9	C10	C11	C12	C13	C14	C15
1	D0	D0 C15	C0	C1	C2	C3	～D0 C4 C15	C5	C6	C7	C8	C9	C10	～D0 C11 C15	C12	C13	C14
																		2	D1	D1 C14	D0 C15	C0	C1	C2	～D1 C3 C14	～D0 C4 C15	C5	C6	C7	C8	C9	～D1 C10 C14	～D0 C11 C15	C12	C13
4	D3	D3 C12	D2 C13	D1 C14	D0 C15	C0	～D3 C1 C12	～D2 C2 C13	～D1 C3 C14	～D0 C4 C15	C5	C6	C7	～D3 C8 C12	～D2 C9 C13	～D1 C10 C14	～D0 C11 C15
																		8	D7	～D3 D7 C8 C12	～D2 D6 C9 C13	～D1 D5 C10 C14	～D0 D4 C11 C15	D3 C12	D2 D3 D7 C8 C12 C13	D1 D2 D6 C9 C13 C14	D0 D1 D5 C10 C14 C15	D0 D4 C0 C11 C15	～D3 C1 C12	～D2 C2 C13	～D1 C3 C14	～D0 D3 D7 C4 C8 C12 C15	D2 D6 C5 C9 C13	D1 D5 C6 C10 C14	D0 D4 C7 C11 C15

Comprise " clock " item, " input " item in the above-mentioned table 2, and the R0-R15 item.Wherein, " clock " be in 0 the horizontally-arranged " C0-C15 " expression R0-R15 trigger in T0 output valve (if T0 is the initial moment of information code input, then C0-C15 equals the reset values of trigger R0-R15 respectively) constantly; " clock " is to represent the output of serial circuit R0-R15 trigger after 1,2,4,8 clock cycle after T0 respectively in 1,2,4,8 the horizontally-arranged; Data in " input " item are the 1st, 2,4,8 clock cycle after T0, the data of serial circuit input; Data in the R0-R15 item are after the 1st, 2,4,8 clock cycle after T0, the output result of each R0-R15 trigger.Pass between each data element in a cell is a distance: for example, comprise data element " D0 " and " C15 " in the 3rd row of table 2, the cell of the 3rd row, then R0 is output as

For the D0-D7 in the table is the input data that are input to serial circuit successively.

Output result according to the 2nd clock cycle trigger R0-R15 in the table 2 can make up the pairing 2 grades of parallel circuits of serial circuit shown in Figure 3; Output result according to the 4th clock cycle trigger R0-R15 in the table 2 can make up the pairing 4 grades of parallel circuits of serial circuit shown in Figure 3; The output result of the 8th clock cycle trigger R0-R15 in the table 2 can make up the pairing 8 grades of parallel circuits of serial circuit shown in Figure 3.

For example, in the 8 grades of parallel circuits as shown in Figure 4 that make up according to the output result of trigger R0-R15 after the 8th clock cycle in the table 2 (i.e. the data of the 6th row in the table 2).These 8 grades of parallel circuits comprise the port of 8 parallel inputs, then can import data D0-D7 simultaneously respectively.

8 grades of parallel circuits shown in Figure 4 also comprise: 4 inverters (N0-N3).After the 8th clock cycle from table 2 among the output result of trigger R0-R15, can see from the data D0-D7 of input input, the input data that 4 negates are arranged: "～D0 ", "～D1 ", "～D2 ", "～D3 " (illustrate here, symbol "～" appears in the equation or appears at the data front then represents " negate "), then in these 8 grades of parallel circuits with regard to corresponding 4 inverters (N0-N3) that comprise, promptly the number of inverter is identical with the input data number of negate.And the input of these 4 inverters is respectively the input port corresponding to corresponding data.For example, the input of N0 inverter is the input of these 8 grades of parallel circuit input data D0.

8 grades of parallel circuits shown in Figure 4 also comprise: 16 trigger R0-R15 and 16 XOR gate Y0-Y15, the output of XOR gate Y0-Y15 link to each other with the input of trigger R0-R15 respectively.The connection of the input of XOR gate Y0-Y15 is respectively according to the data decision that is input to trigger R0-R15 after the 8th clock cycle in the table 2 (in other words, the connection of the input of XOR gate Y0-Y15 is respectively by the decision of the relational expression between the data that are input to trigger R0-R15 after the 8th clock cycle in the table 2):

For example, the data element in the cell of the 6th row the 3rd row have "～D3 ", " D7 ", " C8 " and " C12 " in the table 2.Illustrate that then the data relationship formula that is input to trigger R0 by XOR gate Y0 is

So also just determined the input of Y0 should be respectively (D3 that is input as because of N3 is output as～D3), the input of the input D7 of these 8 grades of parallel circuits, the output (because of trigger R8 output C8) of trigger R8, the output (because of trigger R12 output C12) of trigger R12 with the output of inverter N3.

If, represent the output of trigger R0-R15 respectively with C0-C15, represent the port of 8 parallel inputs of 8 grades of parallel circuits respectively with D0-D7, represent the output of inverter N0-N3 respectively with～D0-～D3, then, just can determine the connection of the input of XOR gate Y0-Y15 intuitively according to the data in the cell of the 6th row in the table 2.Link to each other with the input of the input D6 data of inverter N2,8 grades of parallel circuits, the output of trigger R9, the output of trigger R13 respectively such as, the input that can determine XOR gate Y1 according to the data relationship formula in the 6th row the 4th column unit lattice in the table 2.

In 8 grades of parallel circuits as shown in Figure 4 according to the said method structure:

These 8 grades of parallel circuits have 8 input I0-I7 (not marking among the figure), 4 inverter N0-N3,16 XOR gate Y0-Y15,16 trigger R0-R15.Annexation between them is:

The input of inverter N0-N3 links to each other with the input I0-I3 of these 8 grades of parallel circuits respectively;

The output of XOR gate Y0-Y15 links to each other with the input of trigger R0-R15 respectively;

Each input of XOR gate Y0 links to each other with the output of input I7, the trigger R8 of the output of inverter N3, these 8 grades of parallel circuits, the output of trigger R12 respectively;

Each input of XOR gate Y1 links to each other with the output of input I6, the trigger R9 of the output of inverter N2, these 8 grades of parallel circuits, the output of trigger R13 respectively;

Each input of XOR gate Y2 links to each other with the output of input I5, the trigger R10 of the output of inverter N1, these 8 grades of parallel circuits, the output of trigger R14 respectively;

Each input of XOR gate Y3 links to each other with the output of input I4, the trigger R11 of the output of inverter N0, these 8 grades of parallel circuits, the output of trigger R15 respectively;

Each input of XOR gate Y4 links to each other with the input I3 of these 8 grades of parallel circuits, the output of trigger R12 respectively;

Each input of XOR gate Y5 respectively with input I2, I3, the I7 of these 8 grades of parallel circuits, and the output of trigger R8, R12, R13 links to each other;

Each input of XOR gate Y6 respectively with input I1, I2, the I6 of these 8 grades of parallel circuits, and the output of trigger R9, R13, R14 links to each other;

Each input of XOR gate Y7 respectively with input I0, I1, the I5 of these 8 grades of parallel circuits, and the output of trigger R10, R14, R15 links to each other;

Each input of XOR gate Y8 respectively with input I0, the I4 of these 8 grades of parallel circuits, and the output of trigger R0, R11, R15 links to each other;

Each input of XOR gate Y9 links to each other with the output of inverter N3, the output of trigger R1, the output of trigger R12 respectively;

Each input of XOR gate Y10 links to each other with the output of inverter N2, the output of trigger R2, the output of trigger R13 respectively;

Each input of XOR gate Y11 links to each other with the output of inverter N1, the output of trigger R3, the output of trigger R14 respectively;

Each input of XOR gate Y12 respectively with the output of inverter N0, input I3, the I7 of these 8 grades of parallel circuits, and the output of trigger R4, R8, R12, R15 links to each other;

Each input of XOR gate Y13 respectively with input I2, the I6 of these 8 grades of parallel circuits, and the output of trigger R5, R9, R13 links to each other;

Each input of XOR gate Y14 respectively with input I1, the I5 of these 8 grades of parallel circuits, and the output of trigger R6, R10, R14 links to each other;

Each input of XOR gate Y15 respectively with input I0, I4, the I7 of these 8 grades of parallel circuits, and the output of trigger R11, R15 links to each other.

8 grades of parallel circuits shown in Figure 4 obviously will lack such as 8 grades of inverters that parallel circuit adopted of prior art shown in Figure 2, thereby have reached the purpose that reduces hardware cost.

Sum up said method, for according to proper polynomial $g\left(x\right)=x^n+\underset{k=1}{\overset{k=n-1}{\mathrm{\&Sigma;}}}{b}_k{x}^k+1$ The serial circuit that generates the CRC check sign indicating number comprises: n trigger R ₀-R _N-1, inverter N0, a biconditional gate Y0, m XOR gate, m equals b _kIt is 1 number.The input that input is described serial circuit of biconditional gate Y0, another input and trigger R _N-1Output link to each other.The input of inverter N0 links to each other with the output of biconditional gate Y0.Each trigger R ₀-R _N-1Input then respectively according to b _kValue decision: if b _kBe 0, so directly with trigger R _K-1Output as trigger R _kData terminal input; If b _kBe 1, so with output and the trigger R of biconditional gate Y0 _K-1Output respectively with after two inputs of an XOR gate link to each other, the output of this XOR gate then with trigger R _kInput link to each other.

The embodiment of the invention is for according to proper polynomial $g\left(x\right)=x^n+\underset{k=1}{\overset{k=n-1}{\mathrm{\&Sigma;}}}{b}_k{x}^k+1$ Generate the method flow of t (t is the integer greater than 1) the level parallel circuit of CRC check sign indicating number, comprise the steps: as shown in Figure 5 to be characterized as:

S501, determine that described t level parallel circuit has t parallel input I ₀-I _T-1

S502, determine the number m of described t level parallel circuit inverter.

The number m of inverter is by C ₀ ^(t)-C _N-1 ^(t)Expression formula determine and C ₀ ^(t)-C _N-1 ^(t)Expression formula determined by following formula 1:

R is the integer (r value comprise 2, t) between [2, t] in the above-mentioned recurrence formula 1; Data element D ₀-D _T-1The input I of the corresponding described device of difference ₀-I _T-1, its physical significance can be expressed as from input I ₀-I _T-1The data of parallel input; C ₀ ^(t)-C _N-1 ^(t)Physical significance can be expressed as trigger R in the t level parallel circuit ₀-R _N-1Output valve.C in the recurrence formula 1 ₀ ⁽¹⁾-C _N-1 ⁽¹⁾, then by formula 2 decisions:

The physical significance of formula 2 is above-mentioned proper polynomial $g\left(x\right)=x^n+\underset{k=1}{\overset{k=n-1}{\mathrm{\&Sigma;}}}{b}_k{x}^k+1$ The serial circuit that generates the CRC check sign indicating number is at T0 time trigger device R ₀-R _N-1Output valve is C ₀-C _N-1, at T0 after clock cycle constantly, the trigger R in this serial circuit ₀-R _N-1Output valve is C ₀ ⁽¹⁾-C _N-1 ⁽¹⁾

Operation relation symbol “ ﹠amp in the above-mentioned formula 1 and 2; " expression " and with " operation relation, operation relation symbol "

" expression distance operation relation.C in the formula 1 ₀ ^(t)-C _N-1 ^(t)Physical significance be trigger R in the expression t level parallel circuit ₀-R _N-1Output valve.

C ₀ ^(t)-C _N-1 ^(t)Expression formula (be equation the right) finally can distinguish equivalence and be XOR relational expression NOR ₀-NOR _N-1Herein, the XOR relational expression refer to comprise at the most XOR "

" and the relational expression of negate "～" relational operator.XOR in the XOR relational expression " " or negate "～" relational operator be used for the data element is carried out the logical relation computing.At D ₀-D _T-1In if w data element arranged at XOR relational expression NOR ₀-NOR _N-1Middle negate, then the number m of inverter is w.And m inverter N ₀-N _M-1The data element of respectively corresponding each negate.Such as, at XOR relational expression NOR ₀-NOR _N-1In data element arranged: "～D0 ", "～D1 ", "～D2 ", "～D3 ", i.e. D ₀-D _T-1In the data element of negate have 4, so the number m of inverter also is 4, and inverter N ₀-N ₃The corresponding D0-D3 of difference.

S503, determine inverter N in the described t level parallel circuit ₀-N _M-1The connection of input.

Inverter N ₀-N _M-1The connection of input is also by C ₀ ^(t)-C _N-1 ^(t)Equation determine, specifically by XOR relational expression NOR ₀-NOR _N-1The D of middle negate ₀-D _T-1Determine.Be specially, if at XOR relational expression NOR ₀-NOR _N-1Middle existence～D _p, D then _pThe input and the D of corresponding inverter _pCorresponding input end I _p(p is that span is 0 to t-1 integer) links to each other.Such as, C ₀ ^(t)-C _N-1 ^(t)The XOR relational expression in the D of negate ₀-D _T-1Have: "～D0 ", "～D1 ", "～D2 ", "～D3 ", then inverter N ₀-N ₃Input links to each other with the input of the parallel circuit of importing D0, D1, D2, D3 respectively.

S504, determine the number q of XOR gate in the described t level parallel circuit.

Described q is by XOR relational expression NOR ₀-NOR _N-1The number of middle multidata element relation formula is determined; Described multidata element XOR relational expression refers to, and has the XOR relational expression of an XOR relational operator at least.For example, NOR ₀For , then have 3 XOR relational operators, be multidata element relation formula therefore; If do not have the XOR relational operator, then be called forms data element XOR relational expression.

The number q of XOR gate equals NOR in the described t level parallel circuit ₀-NOR _N-1In the number of multidata element XOR relational expression is arranged.

S505, determine m inverter N in the described t level parallel circuit ₀-N _M-1Output, a n trigger R ₀-R _N-1, a q XOR gate Y ₀-Y _Q-1Connection.

Concrete grammar is:

If NOR _jBe multidata element XOR relational expression (j is that span is 0 to n-1 integer), then NOR _jThe output and the trigger R of corresponding XOR gate _jInput link to each other, the connection of this XOR gate input is then according to NOR _jDetermine:

If NOR _jIn have C _i(i is that span is 0 to n-1 integer), then this XOR gate input and trigger R _iOutput link to each other;

If NOR _jIn have the D of negate _l, then this XOR gate input and D _lThe output of corresponding inverter links to each other;

If NOR _jThe middle D that does not have negate that exists _l(l is that span is 0 to t-1 integer), then the input I of this XOR gate input and described device _lLink to each other.

Such as, XOR relational expression NOR ₀:

, NOR ₀Each data element in the XOR relational expression is respectively " D3 " of " D7 ", " C8 ", " C12 " and negate, then with NOR ₀Corresponding XOR gate Y ₀Corresponding with the D3 respectively inverter N of input ₃The input I of described t level parallel circuit of output, D7 correspondence ₇, the C8 correspondence trigger R ₈Output, the trigger R of C12 correspondence ₁₂Output link to each other.

If NOR _jNot multidata element XOR relational expression, then trigger R _jThe connection of input is then according to NOR _jDetermine: if NOR _jIn have C _i(i is that span is 0 to n-1 integer), then trigger R _jInput and trigger R _iOutput link to each other.Such as, if NOR _j=C ₂, trigger R then _jInput directly and trigger R ₂Output link to each other.

Because XOR relational expression NOR according to above-mentioned formula 1, formula 2 acquisitions ₀-NOR _N-1, with corresponding serial circuit at T0 t clock cycle constantly, each trigger R of serial circuit ₀-R _N-1The data relationship formula of output valve is the same.Therefore, according to C ₀ ^(t)-C _N-1 ^(t)Equation can determine trigger R respectively ₀-R _N-1The connection of input.

S506, determine trigger R in the described t level parallel circuit ₀-R _N-1Reset values.

Trigger R ₀-R _N-1Reset values, be trigger R ₀-R _N-1Initial value, be C ₀-C _N-1Those skilled in the art can determine trigger R according to the CRC check code type ₀-R _N-1Reset values.Such as, for the parallel circuit of the check code that generates the CRC-CCITT16 type, the trigger reset value that is provided with in the circuit all is 0; Generate the parallel circuit of the check code of other type for some, the trigger reset value in can circuit all is 1.Usually, according to the trigger reset value of the parallel circuit of prior art, trigger reset value and prior art opposite of the parallel circuit of the corresponding embodiment of the invention is set.

Though it will be understood by those skilled in the art that in the above-mentioned explanation, for ease of understanding, the step of method has been adopted the succession description, should be pointed out that for the order of above-mentioned steps and do not do strict the restriction.Then can determine proper polynomial according to above-mentioned steps $g\left(x\right)=x^n+\underset{k=1}{\overset{k=n-1}{\mathrm{\&Sigma;}}}{b}_k{x}^k+1$ The t level parallel circuit of pairing generation CRC check sign indicating number.For example, can determine proper polynomial g (x)=x according to above-mentioned steps S501-S505 ¹⁶+ x ¹²+ x ⁵8 grades of parallel circuits (as shown in Figure 4) of 16 CRC check sign indicating numbers of+1 pairing generation, perhaps the proper polynomial according to n=32 adopts said method to build the t level parallel circuit that generates 32 bit check sign indicating numbers.Those skilled in the art can realize the t level parallel circuit of various generation n bit check sign indicating numbers according to the disclosed technology contents of the embodiment of the invention, enumerate no longer one by one herein.

Behind said method structure parallel circuit, the process that generates verification by this parallel circuit is: with the parallel input I of information code from described device ₀-I _T-1Parallel input; After described input input, the cyclic redundancy check (CRC) code of described information code is formed in the output of each trigger in the parallel circuit in all information codes.

The parallel circuit that generates according to said method lacks than the inverter of the parallel circuit of the same progression of prior art, thereby has reached the purpose that reduces hardware cost.Such as, according to 4 inverters of 4 grades of parallel circuit needs of 16 CRC check sign indicating numbers of embodiment of the invention generation, 4 grades of parallel circuits of 16 CRC check sign indicating numbers of generation of prior art then need 16 inverters.

The parallel circuit of the generation CRC check sign indicating number of the embodiment of the invention is owing to some inputs at parallel circuit have increased inverter, the inverter that thereby each trigger in the parallel circuit can be connected removes, thereby saved a large amount of inverters, simplified CRC check sign indicating number parallel circuit, reduced hardware cost.

One of ordinary skill in the art will appreciate that all or part of step that realizes in the foregoing description method is to instruct relevant hardware to finish by program, this program can be stored in the computer read/write memory medium, as: ROM/RAM, magnetic disc, CD etc.

Will also be appreciated that the apparatus structure shown in accompanying drawing or the embodiment only is schematically, the presentation logic structure.Wherein the module that shows as separating component may or may not be physically to separate, and the parts that show as module may be or may not be physical modules.

The above only is a preferred implementation of the present invention; should be pointed out that for those skilled in the art, under the prerequisite that does not break away from the principle of the invention; can also make some improvements and modifications, these improvements and modifications also should be considered as protection scope of the present invention.

Claims (12)

1, a kind of cyclic redundancy check code generation apparatus, the proper polynomial of described cyclic redundancy check (CRC) code is $g\left(x\right)=x^n+\underset{k=1}{\overset{k=n-1}{\mathrm{\&Sigma;}}}{b}_x{x}^k+1,$ Wherein n is a natural number, b _kValue is 0 or 1, and described device has t parallel input I ₀-I _T-1, it is characterized in that described device comprises: m inverter N ₀-N _M-1, a n trigger R ₀-R _N-1, and q XOR gate Y ₀-Y _Q-1

Described m is by XOR relational expression NOR ₀-NOR _N-1In the first negate number determine; Described XOR relational expression NOR ₀-NOR _N-1Be respectively C ₀ ^(t)-C _N-1 ^(t)Expression formula equivalent XOR relational expression; Described XOR relational expression refers to the relational expression that comprises XOR and negate relational operator at the most;

Described C ₀ ^(t)-C _N-1 ^(t)Expression formula determine according to first recurrence formula:

Wherein, r is the integer between [2, t]; Data element D ₀-D _T-1The input I of the corresponding described device of difference ₀-I _T-1At D ₀-D _T-1In if w data element arranged at XOR relational expression NOR ₀-NOR _N-1Middle negate, the then described first negate number is w; And m inverter N ₀-N _M-1The data element of respectively corresponding each negate;

C in described first recurrence formula ₀ ⁽¹⁾-C _N-1 ⁽¹⁾Value, determine by second formula:

C in described second formula ₀-C _N-1The corresponding trigger R of difference ₀-R _N-1Output;

If at XOR relational expression NOR ₀-NOR _N-1Middle existence～D _p, D then _pThe input and the D of corresponding inverter _pCorresponding input end I _pLink to each other; Described p is that span is 0 to t-1 integer;

Described q is by XOR relational expression NOR ₀-NOR _N-1The number of middle multidata element XOR relational expression is determined; And XOR gate Y ₀-Y _Q-1Respectively corresponding each multidata element XOR relational expression; Described multidata element XOR relational expression refers to the XOR relational expression that has an XOR relational operator at least;

Described inverter N ₀-N _M-1Output, trigger R ₀-R _N-1With XOR gate Y ₀-Y _Q-1Connection according to XOR relational expression NOR ₀-NOR _N-1Determine.

2, device as claimed in claim 1 is characterized in that,

Described inverter N ₀-N _M-1Output, trigger R ₀-R _N-1With XOR gate Y ₀-Y _Q-1Connection according to XOR relational expression NOR ₀-NOR _N-1Determine, be specially:

If NOR _jBe multidata element XOR relational expression, then NOR _jThe output and the trigger R of corresponding XOR gate _jInput link to each other, the connection of this XOR gate input is then according to NOR _jDetermine;

If NOR _jNot multidata element XOR relational expression, then trigger R _jThe connection of input is then according to NOR _jDetermine;

Described j is that span is 0 to n-1 integer.

3, device as claimed in claim 2 is characterized in that,

With NOR _jThe connection of the input of corresponding XOR gate is according to NOR _jDetermine, be specially:

If NOR _jIn have C _i, then this XOR gate input and trigger R _iOutput link to each other; Described i is that span is 0 to n-1 integer;

If NOR _jIn have the D of negate _l, then this XOR gate input and D _lThe output of corresponding inverter links to each other;

If NOR _jThe middle D that does not have negate that exists _l, the input I of this XOR gate input and described device then _lLink to each other; Described l is that span is 0 to t-1 integer.

4, device as claimed in claim 2 is characterized in that,

Described trigger R _jThe connection of input is according to NOR _jDetermine, be specially:

If NOR _jIn have C _i, trigger R then _jInput and trigger R _iOutput link to each other; Described i is that span is 0 to n-1 integer.

5, as the arbitrary described device of claim 1-4, it is characterized in that described trigger R ₀-R _N-1Reset values all be 0 or all be 1.

6, a kind of method of passing through to generate as the described device of claim 1-4 cyclic redundancy check (CRC) code is characterized in that, comprising:

With the parallel input I of information code from described device ₀-I _T-1Parallel input;

After described input input, the cyclic redundancy check (CRC) code of described information code is formed in the output of each trigger in all information codes.

7, a kind of method that makes up cyclic redundancy check code generation apparatus, the proper polynomial of described cyclic redundancy check (CRC) code is $g\left(x\right)=x^n+\underset{k=1}{\overset{k=n-1}{\mathrm{\&Sigma;}}}{b}_x{x}^k+1,$ Wherein n is a natural number, b _kValue is 0 or 1, and described device has t parallel input I ₀-I _T-1, it is characterized in that described method comprises:

Determine the number m of the inverter of described device; Described m is by XOR relational expression NOR ₀-NOR _N-1In the first negate number determine; Described XOR relational expression NOR ₀-N; OR _N-1Be respectively and calculate C ₀ ^(t)-C _N-1 ^(t)Equation the right equivalent XOR relational expression; Described XOR relational expression refers to the relational expression that comprises XOR and negate relational operator at the most;

Calculate C ₀ ^(t)-C _N-1 ^(t)Equation determine according to first recurrence formula:

Wherein, r is the integer between [2, t]; Data element D ₀-D _T-1The input I of the corresponding described device of difference ₀-I _T-1At D ₀-D _T-1In if w data element arranged at XOR relational expression NOR ₀-NOR _N-1Middle negate, the then described first negate number is w; And m inverter N ₀-N _M-1The data element of respectively corresponding each negate;

C in described first recurrence formula ₀ ⁽¹⁾-C _N-1 ⁽¹⁾Value, determine by second formula:

C in described second formula ₀-C _N-1The corresponding trigger R of difference ₀-R _N-1Output;

If at XOR relational expression NOR ₀-NOR _N-1Middle existence～D _p, D then _pThe input and the D of corresponding inverter _pCorresponding input end I _pLink to each other; Described p is that span is 0 to t-1 integer;

Determine the number q of the XOR gate of described device; Described q is by XOR relational expression NOR ₀-NOR _N-1The number of middle multidata element XOR relational expression is determined; And q XOR gate Y ₀-Y _Q-1Respectively corresponding each multidata element XOR relational expression; Described multidata element XOR relational expression refers to the XOR relational expression that has an XOR relational operator at least;

According to described XOR relational expression NOR ₀-NOR _N-1Determine described inverter N ₀-N _M-1Output, trigger R ₀-R _N-1With XOR gate Y ₀-Y _Q-1Connection.

8, method as claimed in claim 7 is characterized in that, and is described according to described XOR relational expression NOR ₀-NOR _N-1Determine described inverter N ₀-N _M-1Output, trigger R ₀-R _N-1With XOR gate Y ₀-Y _Q-1Connection, specifically comprise:

If NOR _jBe multidata element XOR relational expression, then NOR _jThe output and the trigger R of corresponding XOR gate _jInput link to each other, then according to NOR _jDetermine the connection of this XOR gate input;

If NOR _jNot multidata element XOR relational expression, then according to NOR _jDetermine trigger R _jThe connection of input; Described j is that span is 0 to n-1 integer.

9, method as claimed in claim 8 is characterized in that, according to NOR _jDetermine NOR _jThe connection of corresponding XOR gate input specifically comprises:

If NOR _jIn have C _i, then determine this XOR gate input and trigger R _iOutput link to each other; Described i is that span is 0 to n-1 integer;

If NOR _jIn have the D of negate _l, then this XOR gate input and D _lThe output of corresponding inverter links to each other;

If NOR _jThe middle D that does not have negate that exists _l, the input I of this XOR gate input and described device then _lLink to each other; Described l is that span is 0 to t-1 integer.

10, method as claimed in claim 8 is characterized in that, the described connection of determining trigger Rj input according to NORj specifically comprises:

If NOR _jIn have C _i, then determine trigger R _jInput and trigger R _iOutput link to each other; Described i is that span is 0 to n-1 integer.

11, as the arbitrary described method of claim 7-10, it is characterized in that, also comprise:

Described trigger R is set ₀-R _N-1Reset values all be 0 or all be 1.

12, a kind of cyclic redundancy check code generation apparatus has 8 parallel input I0-I7, it is characterized in that, comprising: 4 inverter N0-N3,16 XOR gate Y0-Y15,16 trigger R0-R15;

The input of described inverter N0-N3 links to each other with described input I0-I3 respectively;

The output of described XOR gate Y0-Y15 links to each other with the input of trigger R0-R15 respectively;

Each input of XOR gate Y0 links to each other with the output of inverter N3, the output of input I7, trigger R8, the output of trigger R12 respectively;

Each input of XOR gate Y1 links to each other with the output of inverter N2, the output of input I6, trigger R9, the output of trigger R13 respectively;

Each input of XOR gate Y2 links to each other with the output of inverter N1, the output of input I5, trigger R10, the output of trigger R14 respectively;

Each input of XOR gate Y3 links to each other with the output of inverter N0, the output of input I4, trigger R11, the output of trigger R15 respectively;

Each input of XOR gate Y4 links to each other with the output of input I3, trigger R12 respectively;

Each input of XOR gate Y5 respectively with input I2, I3, I7, and the output of trigger R8, R12, R13 links to each other;

Each input of XOR gate Y6 respectively with input I1, I2, I6, and the output of trigger R9, R13, R14 links to each other;

Each input of XOR gate Y7 respectively with input I0, I1, I5, and the output of trigger R10, R14, R15 links to each other;

Each input of XOR gate Y8 respectively with input I0, I4, and the output of trigger R0, R11, R15 links to each other;

Each input of XOR gate Y9 links to each other with the output of inverter N3, the output of trigger R1, the output of trigger R12 respectively;

Each input of XOR gate Y10 links to each other with the output of inverter N2, the output of trigger R2, the output of trigger R13 respectively;

Each input of XOR gate Y11 links to each other with the output of inverter N1, the output of trigger R3, the output of trigger R14 respectively;

Each input of XOR gate Y12 respectively with output, input I3, the I7 of inverter N0, and the output of trigger R4, R8, R12, R15 links to each other;

Each input of XOR gate Y13 respectively with input I2, I6, and the output of trigger R5, R9, R13 links to each other;

Each input of XOR gate Y14 respectively with input I1, I5, and the output of trigger R6, R10, R14 links to each other;

Each input of XOR gate Y15 respectively with input I0, I4, I7, and the output of trigger R11, R15 links to each other.

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