CN101496266B - Low-voltage locked-in oscillator of DC-DC converter - Google Patents

Abstract

The system and method disclosed by invention provide an oscillator circuit which outputs non-overlapping triggering signal in the whole operating voltage range when an RS trigger type circuit structure is used. An embodiment uses an output driving bugger in the RS trigger type circuit structure for providing the feedback delay of oscillator. A feedback control circuit can be applied for ensuring the delay of a random driving buffer not only provides feedback delay. The embodiment also adopts an input delay circuit so that a relatively stable replacement and setting input feedback delay ratio is kept in the whole large-area operating condition.

Description

The low-voltage locked-in oscillator of DC-DC converter

Technical field

The present invention relates generally to pierce circuit, the pierce circuit that particularly in the DC-DC converter applications, uses.

Background technology

The electronic equipment that is used for individual and commercial use is general all the more.For example, many people use personal computer, calculator, entertainment systems and phone every day in its daily life.These electronic devices are portable, therefore comprise an independent current source, like the form of a battery or battery pack.

The battery that aforementioned power source is used provides a direct current (DC) source.Commercial batteries has various structures usually, has preset capacity and output voltage.In the time of mostly, the DC output voltage that the battery of use provides, and be different from the desired voltage of one or more circuit that this powered battery is given electronic equipment.For example, some commercial batteries can provide a very high output voltage, and some commercial batteries can provide a very low output voltage, do not have commercial batteries to provide one just in time to be the circuit desired output voltage of concrete electronic equipment.Similarly; Consider for example size (to be convenient for carrying) from some; Electronic equipment can use the battery of a small-sized apparent size (small form-factor), although this special battery does not provide an output voltage of the circuit requirement of this electronic equipment.The further deterioration of this phenomenon that do not match between cell output voltage and electronic device circuitry voltage request; Mainly be to come from such fact: promptly along with time and/or use, all this batteries all tend to experience electric voltage dropping (voltage sag) (the voltage output of decline).Therefore, although the output voltage of battery initially can satisfy the circuit voltage requirement, the output voltage of battery can not continue to satisfy the circuit voltage that electronic equipment uses.

So, developed various circuit so that DC-DC to be provided voltage transitions, like the output voltage (like 1.5 volts of output voltages of typical AA dry cell) that improves commercial batteries to a voltage (as 3.3 volts) that is enough to reliability service normal transistor logical circuit.For example, the DC-DC converter can use pair of switches (like transistor), controllably to change the electric current that is provided by the DC source, is used for source voltage transitions to a higher voltage.For fear of there being ground short circuit (i.e. " short circuit "), the triggering signal of controlling these switches should be synchronous, makes these two switches can not open (i.e. conduction) simultaneously.Therefore, this DC-DC voltage conversion circuit has adopted a pierce circuit usually, produces the voltage transitions of expectation to provide triggering signal to be used to.With reference to B.Sahu, " A Low Voltage, Dynamic, Non-inverting, the SynchronousBuck-Boost Converter for Portable Applications " of Gabriel A. and Rincon-Mora; IEEE Transactions on PowerElectronics, Vol.19, No.2, the 443rd page, in March, 2004; C.Y.Leung, " the A 1-V Integrated Current-Mode Boost Converter inStandard 3.3/5-V CMOS Technologies " of P.K.T.Mok and K.N.Leung, Vol.40, No.11; The 2265-2274 page or leaf, in November, 2005, U.S. Patent number 6,603; 291, license to Wheeler etc., U.S. Patent number 6,396; 250, license to Bridge and U.S. Patent number 7,006; 364, license to Jin etc., be attached to this paper general the quoting of these these reference papers, for example to adopting the DC-DC voltage conversion circuit of pierce circuit.

So far, the oscillator that can be used in the DC-DC transducer is very not desirable.For example, some previous oscillator configurations adopt a fixed delay so that non-overlapped triggering signal output to be provided.In above reference papers " A Low Voltage; Dynamic; Non-inverting, SynchronousBuck-Boost Converter for Portable Applications " and " A 1-V IntegratedCurrent-Mode Boost Converter in Standard 3.3/5-V CMOS Technologies " and above referenced patent 6,603; The oscillator of 291 li demonstrations all adopts this fixed delay.But, it has been found that this delay although be on the implication that can not regulate and control, to be fixed, in fact is unfixed in running environment.For example, delay is to receive the variable effect of working voltage (falling like supply voltage), operating temperature etc.For example, on 3.3 volts of the working voltages of an expectation, one " fixing " postpones can be 10nsec; But possibly on 1 volt, rise to 100nsec, on 0.6 volt, rise to 200nsec, therefore; Postponing becomes governing factor, and the DC-DC converter no longer can be changed reliably.Use hybrid circuit (like analog-and digital-circuit) that previous problem will be worsened more.Along with the delay that in pierce circuit, provides changes, triggering signal output becomes asynchronous, causes triggering signal output overlapping malfunctioning with the DC-DC converter.

Adopt the oscillator of programmable delay to be used to attempt addressing the above problem.The oscillator that shows in the above referenced patent 6,396,250 adopts this programmable delay.These adopt the oscillator of analog-and digital-circuit very complicated usually, take sizable physical space, and are difficult for implementing.In addition; If programmable delay makes a mistake (as to be used for the model that forecasting institute need postpone be not accurate, and changing through the integrated circuit process has difference to produce circuit, or the like); Triggering signal output possibly be nonsynchronous, causes triggering signal output overlapping malfunctioning with the DC-DC converter.

In order to address the above problem, many previous oscillator configurations adopt one or more delay tuning circuits.Oscillator in 7,006,364 li demonstrations of above referenced patent adopts this delay tuning circuit.Variation on the corresponding service conditions changes like working voltage, although this tuning circuit maybe be effective a little when control lag, it is not impeccable using sort circuit.For example, the delay tuning circuit is very complicated usually, and increases DC-DC converter cost, complexity and physical size.The complexity that postpones tuning circuit possibly cause the integrated circuit process to change and can not move or the uncertain circuit of generation.In addition, postpone tuning circuit and often adopt voltage sensor, its when low pressure (as 8 volts) are invalid, therefore can not be used in most of battery life cycle, provide reliably and voltage transitions accurately.Particularly boosting or falling-rising when pressing the DC-DC converter circuit to open, this restriction on low pressure operation is problematic especially, is impossible because this converter provides high voltage.In addition, although the operation control lag is to keep non-overlapped triggering signal output, this delay tuning circuit often can not keep a constant-duty cycle of circuits for triggering output, and therefore, the output of DC-DC converter voltage is not constant.

Summary of the invention

The system and method that the present invention relates to, use directly reset-set (RS) triggers in the whole service voltage range of type circuit structure provides a pierce circuit to export non-overlapped triggering signal.

A kind of low-voltage locked-in oscillator system of DC-DC converter comprises:

A rest-set flip-flop circuit, it has the cross-couplings signal path, and has input and first output and second output,

Said rest-set flip-flop circuit comprises cross-linked first, second NOR door when being the NOR type; Said input connects first input end of a NOR door; And connect first input end of the 2nd NOR door through reverser; The lead-out terminal of a said NOR door connects first output and second input terminal of the 2nd NOR door through first delay circuit, and the lead-out terminal of said the 2nd NOR door connects second through second delay circuit and exports and second input terminal of a NOR door

Said rest-set flip-flop circuit comprises cross-linked first, second NAND door when being the NAND type; Said input connects first input end of a NAND door; And connect first input end of the 2nd NAND door through reverser; The lead-out terminal of a said NAND door connects first output and second input terminal of the 2nd NAND door through first delay circuit, and the lead-out terminal of said the 2nd NAND door connects second through second delay circuit and exports and second input terminal of a NAND door;

Said first delay circuit provides first signal delay; Said second delay circuit provides secondary signal to postpone; Wherein when said output is fed back to said input; Select said first and second signal delays to combine, so that the self-oscillation of said rest-set flip-flop circuit to be provided in a working voltage expected range

Oscilator system also is included in the switching circuit that moves under the control of controller; Controller is connected to input so that detect status input signal; And the control switch circuit is used for oscillatory feedback with a suitable input that outputs to that connects in first output and second output; Make that feeding back to input from first output or second output is used for oscillatory signal and comprises the delay that is produced by first delay circuit and second delay circuit

When wherein said rest-set flip-flop circuit is the NOR type; Make and to export feedback signal second when being high when input; And when input when being low in first output feedback signal; And said rest-set flip-flop circuit is when being the NAND type, make when input when being high in first output feedback signal, export feedback signal and exporting second when being low when input.

A kind of low pressure synchronized oscillation method of DC-DC converter comprises:

The rest-set flip-flop circuit is provided, and it has the cross-couplings signal path, and has input and first output and second output; Said rest-set flip-flop circuit comprises cross-linked first, second NOR door when being the NOR type; Said input connects first input end of a NOR door; And connect first input end of the 2nd NOR door through reverser; The lead-out terminal of a said NOR door is coupled to second input terminal of first output and the 2nd NOR door, and the lead-out terminal of said the 2nd NOR door is coupled to second input terminal of output second output and a NOR door; Said rest-set flip-flop circuit comprises cross-linked first, second NAND door when being the NAND type; Said input connects first input end of a NAND door; And connect first input end of the 2nd NAND door through reverser; The lead-out terminal of a said NAND door is coupled to second input terminal of first output and the 2nd NAND door, and the lead-out terminal of said the 2nd NAND door is coupled to second input terminal of second output and a NAND door

When said rest-set flip-flop circuit is the NOR type; The lead-out terminal of a said NOR door is connect second input terminal of first output and the 2nd NOR door through first delay circuit, the lead-out terminal of said the 2nd NOR door is connect second through second delay circuit export and second input terminal of a NOR door; When said rest-set flip-flop circuit is the NAND type; The lead-out terminal of a said NAND door is connect second input terminal of first output and the 2nd NAND door through first delay circuit; The lead-out terminal of said the 2nd NAND door is connect second input terminal of second output and a NAND door through second delay circuit

Between first output of said rest-set flip-flop circuit and second output and the input of said rest-set flip-flop circuit, connect a gate-controlled switch circuit; With

Control said gate-controlled switch circuit to select a output in said first output and second output feeding back to said input, said output is definite in such a way:

When said rest-set flip-flop circuit is the NOR type, when input when being high in second output feedback signal, and export feedback signal first when being low when input,

When said rest-set flip-flop circuit is the NAND type, when input when being high in first output feedback signal, and export feedback signal second when being low when input,

Make feedback signal always comprise to provide one delay that postpones and provide by said second delay circuit by said first delay circuit.

Embodiments of the invention use the inner output driving buffer of rest-set flip-flop circuit structure that oscillator feedback delay is provided, thereby a self-oscillatory circuit structure is provided.Preferably, adopt feedback control circuit feedback delay not merely to be provided to guarantee any one delay that drives buffer.Therefore, the control circuit of embodiment provides FEEDBACK CONTROL, make the signal that is fed back propagate through each output driving buffer, thereby the triggering signal that pierce circuit continues to provide non-overlapped in whole large-scale working voltage is exported.Embodiments of the invention also adopt the input delay circuit, in whole aforementioned large-scale working voltage, to keep constant relatively resetting and set input feedback delay ratio.So the pierce circuit of the embodiment of the invention provides a kind of self-maintained circuit, the non-overlapped triggering signal output that it provides has a relative constant-duty cycle on the working voltage on a large scale.

Oscillator circuit structure of the present invention does not need programmed delays or complicated delay tuning circuit, therefore, can avoid the shortcoming relevant with sort circuit.Correspondingly, pierce circuit of the present invention is operation reliably on low pressure more, in using at CMOS, is 6 volts, even boosting and falling-rising presses the DC-DC converter circuit also easily to use in starting.In addition, adopt pierce circuit of the present invention, can use less physical space (like chip area (die area)) and little cost.

Aforementioned characteristic of the present invention and the technical advantage set forth quite widely is so that can understand detailed description of the present invention better.Further feature of the present invention and advantage will be in following descriptions, and it has constituted claim project of the present invention.The notion that it should be appreciated by those skilled in the art that disclosure can be used at an easy rate as the basis with specific embodiment and be used for revising or designing other structure to accomplish identical purpose of the present invention.Those skilled in the art also should be realized that, the spirit and scope of the present invention that this structure that is equal to does not squint and sets forth in the accompanying claims.The novel features that is considered to characteristics of the present invention, its structure and How It Works, and further purpose and advantage are from following description and combine accompanying drawing to be better understood.But, should recognize profoundly that each characteristic that provides all only is in order to describe and to explain, rather than is intended to limit definition of the present invention.

Description of drawings

In order more fully to understand the present invention, combine accompanying drawing and the following description of reference, wherein at present;

Figure 1A shows the NOR type rest-set flip-flop circuit that uses according to the embodiment of the invention;

Figure 1B shows the NAND type rest-set flip-flop circuit that uses according to the embodiment of the invention;

Fig. 2 A and 2B show the sequential chart of the flip-flop circuit of Figure 1A and 1B;

Fig. 3 A shows the NOR type rest-set flip-flop circuit of Figure 1A, and it has the feedback delay circuit that is arranged in the cross-couplings signal path according to the embodiment of the invention;

Fig. 3 B shows the NAND type rest-set flip-flop circuit of Figure 1B, and it has the feedback delay circuit that is arranged in the cross-couplings signal path according to the embodiment of the invention;

Fig. 4 A and 4B show the feedback signal path of Fig. 3 A flip-flop circuit embodiment of varying input signal level;

Fig. 5 A shows a rest-set flip-flop type oscillator that has FEEDBACK CONTROL according to the embodiment of the invention;

The various embodiment of Fig. 5 B-5G display delay circuit, it can be used in the pierce circuit of Fig. 5 A;

The NOR type rest-set flip-flop circuit of Fig. 6 A displayed map 3A, it has the FEEDBACK CONTROL of Fig. 5 A according to the embodiment of the invention;

The NAND type rest-set flip-flop circuit of Fig. 6 B displayed map 3B, it has the FEEDBACK CONTROL of Fig. 5 A according to the embodiment of the invention;

Fig. 7 A and 7B show the FEEDBACK CONTROL running according to Fig. 6 A of the embodiment of the invention;

Fig. 8 A, Fig. 8 B, Fig. 8 C and Fig. 8 D are presented at the generation and the sequential of signal delay in the NAND type rest-set flip-flop circuit of the embodiment of the invention; With

Fig. 9 shows the curve chart according to the work period contrast feedback delay of exemplary embodiments.

Embodiment

Describing when of the present invention, should be realized that in order to provide reliably and voltage transitions accurately, the oscillator that in the DC-DC voltage changer, uses should satisfy some operation standards.Particularly, this oscillator should provide stable self-oscillation, and the vibration of synchronous or non-overlapped triggering signal output is provided, and the work period of vibration should be constant.The previous various pierce circuits of having been proposed to be used for the DC-DC converter, coming to light, it can not provide satisfactory performance about one or more aforementioned operation standards.In addition, many previous pierce circuit more complicated, with high costs and/or take sizable physical space (as requiring the IC chip space of unimaginable number).

With reference to Figure 1A, 1B, 2A and 2B, can observe the triggering signal output that the rest-set flip-flop circuit structure can be used to provide non-overlapped.Can find that from Figure 1A NOR type rest-set flip-flop circuit structure 100A comprises cross-linked NOR door 101A and 102A, so that a rest-set flip-flop circuit to be provided.Shown in Figure 1B, NAND type rest-set flip-flop circuit structure 100B comprises cross-linked NAND door 101B and 102B, so that a rest-set flip-flop circuit to be provided.In each aforesaid rest-set flip-flop circuit structure; Input R and S are coupling in together through a reverser (inverter) (the reverser 103A in Figure 1A and the reverser 103B in Figure 1B); So that when signal in input when being high on the R, signal is low importing on the S.

Shown in Fig. 2 A, NOR type rest-set flip-flop circuit structure 100A provides non-overlapped high output signal level on output QB and Q.Can see that from the sequential chart of Fig. 2 A as input D when being low (R be low and S is high), output QB is high and Q is low, and as input D when being high (R be high and S is low), export QB and be low and Q is high.What induce one interest most about the non-overlapped triggering signal output facet of circuit is such fact: promptly at input D from low high and from the transition period that height drops, output QB and Q will never be high simultaneously, shown in the regional 201A-203A of Fig. 2 A.Therefore, output QB and the output of the high level on the Q at rest-set flip-flop circuit structure 100A can be utilized as a non-overlapped triggering signal.

Similarly, shown in Fig. 2 B, NAND type rest-set flip-flop circuit structure 100B provides non-overlapped low-output signal level on output QB and Q.Can see that from the sequential chart of Fig. 2 B as input D when being low (R be low and S is high), output QB is high and Q is low, and as input D when being high (R be high and S is low), export QB and be low and Q is high.From low high and from the transition period that height drops, output QB and Q will never be low simultaneously, shown in the regional 201B-203B of Fig. 2 B at input D.Therefore, output QB and the output of the low level on the Q at rest-set flip-flop circuit structure 100A can be utilized as a non-overlapped triggering signal.

Aforementioned non-overlapped triggering signal output characteristic is provided by the cross-couplings circuit structure that above NOR type (Figure 1A) and NAND type (Figure 1B) realize.Although good non-overlapped output signal characteristic is provided, aforesaid rest-set flip-flop structure can not move the self-oscillation that has constant-duty cycle to provide, thereby is not suitable for using the unlatching pierce circuit as a DC-DC converter.

With reference to figure 3A and 3B, shown the rest-set flip-flop circuit structure that can be made into self-oscillation and continue to provide non-overlapped triggering signal output.Particularly, the NOR type rest-set flip-flop circuit structure 300A of said embodiment comprises feedback delay circuit, pdriver 301A and ndriver 302A in Fig. 3 A, on the cross-couplings signal path of NOR door 101A and 102A.Similarly, the NAND type rest-set flip-flop circuit structure 300B of said embodiment comprises feedback delay circuit, pdriver 301B and ndriver 302B in Fig. 3 B, on the cross-couplings signal path of NAND door 101B and 102B.The pdriver 301A of embodiment and 301B and ndriver 302A and 302B are output buffers; It possibly comprise an operational amplifier as a buffer amplifier, the buffering of output signal (QB and Q) is provided and produces a delay (as in the 10-100nsec scope) in signal path.Separately by 301A, 301B (pdriver delay=t _PD) and 302A, 302B (ndriver delay=t _ND) introduce the delay in the signal path, or combine other delay (like the input delay circuit of following description) relevant with other signal path, enough signal delay can be provided, so that the self-oscillation of rest-set flip-flop circuit structure to be provided, this will be in following description.

Although the embodiment of the invention of above description can utilize buffer amplifier as feedback delay circuit; But other embodiments of the invention can also be utilized various other circuit, as long as sort circuit can provide enough delays to be provided at the self-oscillation of this described rest-set flip-flop circuit structure.For example, about any pdriver 301A or 301B or ndriver 302A or 302B, the embodiment of the invention can be used resistor and capacitor circuit, delay line, active device etc.

For a self-maintained circuit is provided, the output (being QB or Q) of NOR type rest-set flip-flop circuit structure 300A, or similarly, the output of NAND type rest-set flip-flop circuit structure 300B is fed back to input (being D).Fig. 4 A and 4B show that output QB is fed back to input D, is used for the self-oscillation of NOR type rest-set flip-flop circuit structure 300A.Signal will adopt shortest path through accomplishing circuit.Therefore, shown in the dotted line in Fig. 4 A, when the input signal on D when being high, feedback signal will comprise the delay that is produced by pdriver 301A, rather than the delay that is produced by ndriver 302A.But shown in the dotted line in Fig. 4 B, when the input signal on D when being low, feedback signal is through comprising the delay that is produced by pdriver 301A and ndriver 302A.In NOR type rest-set flip-flop circuit structure 300A; When output Q is fed back to input D; And in NAND type rest-set flip-flop circuit structure 300B; When output QB or output Q are fed back to input during D, can obtain similar result (when input signal when being high and low, the delay that produces varying number).

The delay of the varying number that produces when being high and low when input signal will can not stop circuit to produce self-oscillation; Although if single delay (like the delay that in the circuit structure of Fig. 4 A, is produced by pdriver 301A) enough is used to provide vibration; But an output triggering signal is used for controlling the pierce circuit of DC-DC converter, and this running is normally unsafty.The delay that is promptly produced by delay circuit (like pdriver 301A, 301B and ndriver 302A, 302B) possibly change along with the difference of service conditions, like working voltage, temperature, service life etc.In addition, the variation in the delay that is provided by a pair of phase delay circuit (like pdriver 301A, ndriver 302A or pdriver 301B, ndriver 302B) can not be similar identical each other.Because the delay that is provided by a corresponding delay circuit can begin dominating role, as because supply voltage falls, and output QB and Q become and be not synchronous, therefore, can not rely on circuit provides DC-DC to change needed non-overlapped triggering signal.

Embodiments of the invention provide a feedback control circuit with the delay of guaranteeing any one delay circuit feedback delay to be provided not only.Therefore, the control circuit of embodiment provides FEEDBACK CONTROL, make the signal that is fed back propagate and pass each output driving buffer, thereby the triggering signal that pierce circuit continues to provide non-overlapped in whole large-scale working voltage is exported.Any variation difference of each sort buffer driver on the service conditions practical range has been offset in deferred run according to each this driving buffer of embodiments of the invention.Be that embodiments of the invention can carry out self calibration to the difference on the feedback delay, so that non-overlapped triggering signal output to be provided.Therefore, the embodiment of the invention can reliably and predictably be moved in the service conditions scope, and does not need programmed delays complicated and with high costs or complicated delay tuning circuit.

With reference to figure 5A, shown rest-set flip-flop type pierce circuit 500 according to the embodiment of the invention, be used for exporting non-overlapped triggering signal and be used to control the DC-DC converter.Rest-set flip-flop circuit 300 can comprise that any suitable R S triggers the type circuit, like the NOR type rest-set flip-flop circuit structure 300A of Fig. 3 A or the NAND type rest-set flip-flop circuit structure 300B of Fig. 3 B.Rest-set flip-flop type pierce circuit 500 comprises switching circuit 501; Preferably include solid-state switch (like transistor); Although can use other switching device (like the physical switch contact); Operation under the control of controller 502, controller preferably includes control logic, like concrete application integrated circuit form or general processor form.The switching circuit 501 of a preferred embodiment comprises the multiplexer (MUX) of an operation under controller 502 controls.The controller 502 of said embodiment is connected to input D, so that detect status input signal (as high or low), and control switch circuit 501 is used for oscillatory feedback with a suitable input D that outputs to who connects among output QB and the Q.The controller 502 monitoring input D that are said embodiment are with control switch circuit 501, make that feeding back to input D from output (QB or Q) is used for oscillatory signal and comprises the delay that is produced by pdriver 301 and ndriver 302.

Should be appreciated that the reverser 503 that provides between output Q and the switching circuit 501, the feedback signal level that provides a feedback signal level correspondence to provide by output QB.Promptly export QB and Q and be reverse each other, therefore use QB output to export with Q and be used for feedback oscillation, one or another feedback signal are reversed.

With reference to figure 6A and 6B, shown the details of special rest-set flip-flop circuit embodiments of the rest-set flip-flop type pierce circuit of relevant Fig. 5 A.Particularly, Fig. 6 A shows NOR type rest-set flip-flop oscillator circuit structure 600A, and Fig. 6 B shows NAND type rest-set flip-flop oscillator circuit structure 600B.Switching circuit 501 and the reverser 503 of switching circuit 501A and 501B and reverser 503A and 503B corresponding diagram 5A.Although it is not shown in the diagram in order to simplify; Preferably; NOR type rest-set flip-flop oscillator circuit structure 600A and NAND type rest-set flip-flop oscillator circuit structure 600B comprise controller circuitry, like the controller 502 of Fig. 5 A, are connected to switching circuit 501A and 501B so that described control like this to be provided.

Like what in Fig. 6 A, seen, preferably, the switching circuit 501A Be Controlled of NOR type rest-set flip-flop oscillator circuit structure 600A, make when input D when being high on output Q feedback signal, and when to import D be low, exporting feedback signal on the QB.Be appreciated that from the description of above Fig. 4 A and 4B the control of this feedback signal causes the delay of pdriver 301A and ndriver 302A, is introduced in the feedback signal as input D when being high and low.This representes with dotted line in Fig. 7 A and 7B.

Preferably, the switching circuit 501B Be Controlled of NAND type rest-set flip-flop oscillator circuit structure 600B, make when input D when being high on output QB feedback signal, and when to import D be low, exporting feedback signal on the Q, shown in Fig. 6 B.Moreover, being appreciated that from the discussion of Fig. 4 A and 4B the control of this feedback signal causes the delay of pdriver 301B and ndriver 302B, it is introduced in the feedback signal when being high and low as input D.

Below described a kind of oscillator circuit structure, it is self-oscillation and non-overlapped triggering signal output is provided.But owing to change (like change in voltage) in the delay that is provided by delay circuit (being pdriver 301 and ndriver 302 in above embodiment) on the circuit service conditions, the work period of triggering signal output possibly change.Be that the high time cycle is the high time will can not maintain a constant ratio with signal on output QB promptly, because different by the delay of delay circuit generation at signal on the output D.But when being provided for the triggering signal of DC-DC conversion, expectation has constant or more constant trigger signal duty, so that consistent and predictable DC-DC change-over circuit output voltage are provided.

Therefore, embodiments of the invention adopt the input delay circuit, with in the whole service condition and range, keep a constant relatively replacement with the input feedback delay ratio of setting.With reference to Fig. 5 A, input delay circuit 504 and 505 are arranged in the input of rest-set flip-flop circuit 300 once more. Input delay circuit 504 and 505 is preferably used in provides delay (t _DBAnd t _D), keep constant or constant relatively ratio on its all service conditionss in the whole service condition and range.For example, input delay circuit 504 and 505 can adopt capacitor, and its running is not influenced by working voltage, so that the constant ratio that postpones between input delay circuit 504 and 505 to be provided in the whole service voltage range.The embodiment of Fig. 5 B and 5C display delay circuit 504 and 505 wherein adopts resistor and capacitor circuit according to the embodiment of the invention.According to following equality, the delay ratio that is provided by the delay circuit 504 and 505 of Fig. 5 B and 5C can be expressed as:

$\frac{t_{\mathrm{DB}}}{t_D}=\frac{\mathrm{RC}}{(N\×R)(M\×C)}---\left(1\right)$

To preferentially select the special circuit structure and the assembly of Fig. 5 B and 5C delay circuit 504 and 505, to provide aforesaid maintenance constant or constant relatively ratio on all service conditionss in the service conditions scope.

Also can use except at those circuit structures described in Fig. 5 B and the 5C embodiment and other circuit structures and the assembly the assembly, can be used to provide delay according to the embodiment of the invention.For example, Fig. 5 D and 5E show the delay circuit 504 of use active device and 505 embodiment.Fig. 5 F and 5G show the delay circuit 504 of use delay line (using a string delay buffer at this) and 505 embodiment.

According to preferred embodiment, input delay circuit 504 and 505 provides delay (delay circuit 504 delay=t _DBWith delay circuit 505 delay=t _D), the delay (t that its domination (dominate) is provided by the feedback delay circuit on all service conditionss of (as in the whole service voltage range) in the service conditions scope _PDAnd t _ND)." domination (dominate) " in this use is meant that main (dominating) postpones to postpone an enough big quantity greater than non-main (non-dominating) and implement the main control that postpones.Work period or delay ratio (Duty cycle or delay ratio) that the delay that provides from said embodiment produces can be expressed as:

$\mathrm{Dutycycle}\left(\mathrm{delayratio}\right)=\frac{t_D+(t_{\mathrm{PD}}+t_{\mathrm{ND}})}{t_{\mathrm{DB}}+t_D+(t_{\mathrm{PD}}+t_{\mathrm{ND}})\×2}---\left(2\right)$

Be longer than oscillator frequency, t if suppose mains voltage variations (as because the electric voltage dropping of battery or battery life) _PDAnd t _NDTo be similar.So, can be reduced at the work period or the delay ratio of equality (2) lining:

$\mathrm{Dutycycle}\left(\mathrm{delayratio}\right)\≈\frac{t_D+(t_{\mathrm{PD}}\×2)}{t_{\mathrm{DB}}+t_D+(t_{\mathrm{PD}}\×4)}---\left(3\right)$

From above equality, be appreciated that and work as t _PDWhen being top dog, the minimum work period is 50%.Along with t _PDThe irrelevant weight that becomes, the work period will more depend on t more _DAnd t _DBRatio.For example, the hypothetical target work period is 70%, and target frequency is 500KHz (2000ns), t _DBe 1400ns, t _DBBe 600ns, and t _PD=t _NDThrough at log scale change t _PDDelay is (1ms) from 0ns to 1000000ns, and the minimum work period is maintained 50%.This relation such as Fig. 9 graphical representation.

Fig. 8 A-8D shows according to the said constant duty cycle trigger signal output that provides of preamble.Particularly, Fig. 8 A has shown the delay that in RS D-flip flop oscillator circuit structure 600A, produces when being high as input D.The typical sequential chart of the correspondence shown in Fig. 8 B has explained that the work period maintenance of output triggering signal QB and Q is constant, shown in high output time 801 and 802.Fig. 8 C shows the delay that when to import D be low, in RS D-flip flop oscillator circuit structure 600A, produces.The typical sequential chart of the correspondence shown in Fig. 8 D has explained that the work period of output triggering signal QB and Q keeps constant and (should be appreciated that t _PDAnd t _NDBe inessential), shown in high output timing 803 and 804.

Description from above should be appreciated that, the said embodiment running of rest-set flip-flop type pierce circuit 500 provides a self-maintained circuit, and it provides the non-overlapped triggering signal output with relative constant-duty cycle in a large-scale working voltage.Correspondingly, the rest-set flip-flop type pierce circuit of the embodiment of the invention provides a pierce circuit that in the DC-DC conversion, uses, so that consistent and predictable voltage transitions to be provided.In addition, rest-set flip-flop type pierce circuit as described herein can move on the low-voltage reliably very much, as 6 volts in using at CMOS, promptly is used in and boosts and the unlatching of falling-rising pressure DC-DC converter circuit.In addition, the enforcement of the rest-set flip-flop type pierce circuit of the embodiment of the invention can be used less physical space (like chip area) and lower cost.

Although embodiments of the invention described here are with reference to the pierce circuit that uses in the DC-DC converter, should be appreciated that rest-set flip-flop type pierce circuit of the present invention can be used for many different application.For example, pierce circuit described here can be used for various timing circuits (timing circuit), presses converter etc. like charge pump (charge pump), falling-rising.

Although described the present invention and advantage thereof in detail, should be appreciated that, in non-migration such as the defined the spirit and scope of the present invention of claim, can make various variations, replacement and change.In addition, the specific embodiment of the scope used of the present invention process, machine, manufacturing, material composition, mode, method and the step that are not limited in specification, describe.From disclosure of the present invention, those skilled in the art will utilize easily and carry out with the corresponding embodiment identical function of explanation here in fact or realized the existing of identical result or later on process, machine, manufacturing, material composition, mode, method or the step of exploitation.Therefore, accompanying claims is intended to comprise these processes, machine, manufacturing, material composition, mode, method or step.

Claims (8)

1. the low-voltage locked-in oscillator system of a DC-DC converter comprises:

A rest-set flip-flop circuit, it has the cross-couplings signal path, and has input (D) and first output (QB) and second output (Q),

Said rest-set flip-flop circuit comprises cross-linked first, second NOR door when being the NOR type; Said input (D) connects first input end of a NOR door; And connect first input end of the 2nd NOR door through reverser; The lead-out terminal of a said NOR door connects second input terminal of first output (QB) and the 2nd NOR door through first delay circuit, the lead-out terminal of said the 2nd NOR door through second delay circuit connect second export (Q) and a NOR door second input terminal

Said rest-set flip-flop circuit comprises cross-linked first, second NAND door when being the NAND type; Said input (D) connects first input end of a NAND door; And connect first input end of the 2nd NAND door through reverser; The lead-out terminal of a said NAND door connects second input terminal of first output (QB) and the 2nd NAND door through first delay circuit, the lead-out terminal of said the 2nd NAND door through second delay circuit connect second export (Q) and a NAND door second input terminal;

Said first delay circuit provides first signal delay; Said second delay circuit provides secondary signal to postpone; Wherein when said output is fed back to said input; Select said first and second signal delays to combine, so that the self-oscillation of said rest-set flip-flop circuit to be provided in a working voltage expected range

Oscilator system also is included in the switching circuit that moves under the control of controller; Controller is connected to input (D) so that detect status input signal; And the control switch circuit is used for oscillatory feedback with a suitable input (D) that outputs to that connects in first output (QB) and second output (Q); Make that feeding back to input (D) from first output (QB) or second output (Q) is used for oscillatory signal and comprises the delay by first delay circuit and the generation of second delay circuit

When wherein said rest-set flip-flop circuit is the NOR type; Make when input (D) when being high in second output (Q) feedback signal; And go up feedback signal in first output (QB) when being low when input (D); And said rest-set flip-flop circuit is when being the NAND type, makes to go up feedback signal in first output (QB) when being high when input (D), and exports (Q) upward feedback signal second when being low when input (D).

2. system according to claim 1 also comprises:

First, second input delay circuit; The first input delay circuit is positioned between first input end of input (D) and NOR door/NAND door; The second input delay circuit is positioned between second input terminal of input (D) and the 2nd NOR door/NAND door; Said first, second input delay circuit provides an input delay separately; Wherein select said input delay with in the working voltage of whole said expected range, to make first output (QB) be high time cycle with maintain a constant ratio the high time cycle in second output (Q).

3. said input delay is wherein selected by system according to claim 2, postpones greater than first signal delay on all voltages of the working voltage of said expected range and secondary signal.

4. system according to claim 1, wherein said first delay circuit and said second delay circuit comprise a buffer circuits separately.

5. system according to claim 4, wherein said buffer circuits comprises an operational amplifier separately.

6. the low pressure synchronized oscillation method of a DC-DC converter comprises:

The rest-set flip-flop circuit is provided, and it has the cross-couplings signal path, and has input (D) and first output (QB) and second output (Q); Said rest-set flip-flop circuit comprises cross-linked first, second NOR door when being the NOR type; Said input (D) connects first input end of a NOR door; And connect first input end of the 2nd NOR door through reverser; The lead-out terminal of a said NOR door is coupled to second input terminal of first output (QB) and the 2nd NOR door, and the lead-out terminal of said the 2nd NOR door is coupled to second input terminal of second output (Q) and a NOR door; Said rest-set flip-flop circuit comprises cross-linked first, second NAND door when being the NAND type; Said input (D) connects first input end of a NAND door; And connect first input end of the 2nd NAND door through reverser; The lead-out terminal of a said NAND door is coupled to second input terminal of first output (QB) and the 2nd NAND door, and the lead-out terminal of said the 2nd NAND door is coupled to second input terminal of second output (Q) and a NAND door

When said rest-set flip-flop circuit is the NOR type; The lead-out terminal of a said NOR door is connect second input terminal of first output (QB) and the 2nd NOR door through first delay circuit, with the lead-out terminal of said the 2nd NOR door through second delay circuit connect second export (Q) and a NOR door second input terminal; When said rest-set flip-flop circuit is the NAND type; The lead-out terminal of a said NAND door is connect second input terminal of first output (QB) and the 2nd NAND door through first delay circuit; The lead-out terminal of said the 2nd NAND door is connect second input terminal of second output (Q) and a NAND door through second delay circuit

Gate-controlled switch circuit of connection between the input (D) of first output (QB) of said rest-set flip-flop circuit and second output (Q) and said rest-set flip-flop circuit; With

Control said gate-controlled switch circuit to select said first output (QB) and second output of output in (Q) to feed back to said input, said output is definite in such a way:

When said rest-set flip-flop circuit is the NOR type, when input (D) is gone up feedback signal in second output (Q) when being high, and when input when being low in the last feedback signal of first output (QB),

When said rest-set flip-flop circuit is the NAND type, when input (D) is gone up feedback signal in first output (QB) when being high, and when input when being low in the last feedback signal of second output (Q),

Make feedback signal always comprise to provide one delay that postpones and provide by said second delay circuit by said first delay circuit.

7. method according to claim 6 also comprises:

The first input delay circuit is arranged between first input end of input (D) and NOR door/NAND door of said rest-set flip-flop circuit;

The second input delay circuit is arranged between first input end of input (D) and the 2nd NOR door/NAND door of said rest-set flip-flop circuit, it is the high time cycle and second to export (Q) to maintain a constant ratio the high time cycle that wherein said first input delay circuit and the said second input delay circuit are selected in whole expectation working voltage scope, to make first output (QB).

8. method according to claim 6 also comprises:

By said rest-set flip-flop circuit non-overlapped triggering signal to a voltage converter circuit is provided.

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