CN101496266A - Low-voltage locked-in oscillator of DC-DC converter - Google Patents

Abstract

The system and method disclosed by invention provide an oscillator circuit which outputs non-overlapping triggering signal in the whole operating voltage range when an RS trigger type circuit structure is used. An embodiment uses an output driving bugger in the RS trigger type circuit structure for providing the feedback delay of oscillator. A feedback control circuit can be applied for ensuring the delay of a random driving buffer not only provides feedback delay. The embodiment also adopts an input delay circuit so that a relatively stable replacement and setting input feedback delay ratio is kept in the whole large-area operating condition.

Description

The low-voltage locked-in oscillator of DC-DC converter

Technical field

[0001] the present invention relates generally to pierce circuit, particularly the pierce circuit that in the DC-DC converter applications, uses.

Background of invention

[0002] it is general all the more to be used for the individual and the electronic equipment of commercial use.For example, many people use personal computer, calculator, entertainment systems and phone every day in its daily life.These electronic devices are portable, therefore comprise an independent current source, as the form of a battery or battery pack.

[0003] battery of aforementioned power source use provides a direct current (DC) source.Commercial batteries has various structures usually, has preset capacity and output voltage.In the time of mostly, the DC output voltage that the battery of use provides, and be different from the desired voltage of one or more circuit that this powered battery is given electronic equipment.For example, some commercial batteries can provide a very high output voltage, and some commercial batteries can provide a very low output voltage, do not have commercial batteries to provide one just in time to be the circuit desired output voltage of concrete electronic equipment.Similarly, consider for example size (to be convenient for carrying) for some, electronic equipment can use the battery of a small-sized apparent size (small form-factor), although this special battery does not provide an output voltage of the circuit requirement of this electronic equipment.The further deterioration of this phenomenon that do not match between cell output voltage and electronic device circuitry voltage request, mainly be to come from such fact: promptly along with time and/or use, all this batteries all tend to experience electric voltage dropping (voltage sag) (the voltage output of decline).Therefore, although the output voltage of battery initially can satisfy the circuit voltage requirement, the output voltage of battery can not continue to satisfy the circuit voltage that electronic equipment uses.

[0004] so, developed various circuit so that DC-DC to be provided voltage transitions, as the output voltage (as 1.5 volts of output voltages of typical AA dry cell) that improves commercial batteries to a voltage (as 3.3 volts) that is enough to reliability service normal transistor logical circuit.For example, the DC-DC converter can use pair of switches (as transistor), so that the electric current that is provided by the DC source controllably to be provided, is used for source voltage transitions to a higher voltage.For fear of there being ground short circuit (i.e. " short circuit "), the triggering signal of controlling these switches should be synchronous, makes these two switches can not open (i.e. conduction) simultaneously.Therefore, this DC-DC voltage conversion circuit has adopted a pierce circuit usually, produces the voltage transitions of expectation to provide triggering signal to be used to.With reference to B.Sahu, " A Low Voltage, Dynamic; Non-inverting, the SynchronousBuck-Boost Converter for Portable Applications " of Gabriel A. and Rincon-Mora, IEEE Transactions on PowerElectronics, Vol.19, No.2, the 443rd page, in March, 2004, C.Y.Leung, " the A 1-V Integrated Current-Mode Boost Converter inStandard 3.3/5-V CMOS Technologies " of P.K.T.Mok and K.N.Leung, Vol.40, No.11, the 2265-2274 page or leaf, in November, 2005, U.S. Patent number 6,603,291, license to Wheeler etc., U.S. Patent number 6,396,250, license to Bridge and U.S. Patent number 7,006,364, license to Jin etc., be attached to this paper, for example to adopting the DC-DC voltage conversion circuit of pierce circuit general the quoting of these these reference papers.

[0005] so far, the oscillator that can be used in the DC-DC transducer is very not desirable.For example, some previous oscillator configurations adopt a fixed delay so that non-overlapped triggering signal output to be provided.In above reference papers " A Low Voltage; Dynamic; Non-inverting; SynchronousBuck-Boost Converter for Portable Applications " and " A 1-V IntegratedCurrent-Mode Boost Converter in Standard 3.3/5-V CMOS Technologies " and above referenced patent 6,603, the oscillator of 291 li demonstrations all adopts this fixed delay.But, it has been found that this delay although be to be fixed, in fact is unfixed in running environment on the implication that can not regulate and control.For example, delay is to be subjected to the variable effect of working voltage (falling as supply voltage), operating temperature etc.For example, on 3.3 volts of the working voltages of an expectation, one " fixing " postpones can be 10nsec, but may on 1 volt, rise to 100nsec, on 0.6 volt, rise to 200nsec, therefore, postponing becomes governing factor, and the DC-DC converter no longer can be changed reliably.Use hybrid circuit (as analog-and digital-circuit) that previous problem will be worsened more.Along with the delay that provides in pierce circuit changes, triggering signal output becomes asynchronous, causes triggering signal output overlapping malfunctioning with the DC-DC converter.

[0006] adopt the oscillator of programmable delay to be used to attempt addressing the above problem.The oscillator that shows in the above referenced patent 6,396,250 adopts this programmable delay.These adopt the oscillator of analog-and digital-circuit very complicated usually, take sizable physical space, and are difficult for implementing.In addition, if programmable delay makes a mistake (as to be used for the model that forecasting institute need postpone be not accurate, and changing by the integrated circuit process has difference to produce circuit, or the like), triggering signal output may be nonsynchronous, causes triggering signal output overlapping malfunctioning with the DC-DC converter.

[0007] in order to address the above problem, many previous oscillator configurations adopt one or more delay tuning circuits.Oscillator in 7,006,364 li demonstrations of above referenced patent adopts this delay tuning circuit.Variation on the corresponding service conditions changes as working voltage, although this tuning circuit may be effective a little when control lag, it is not impeccable using sort circuit.For example, the delay tuning circuit is very complicated usually, and increases DC-DC converter cost, complexity and physical size.The complexity that postpones tuning circuit may cause the integrated circuit process to change and can not move or the uncertain circuit of generation.In addition, postpone tuning circuit and often adopt voltage sensor, its when low pressure (as 8 volts) are invalid, therefore can not be used to provide reliably in most of battery life cycle and voltage transitions accurately.Particularly boosting or falling-rising when pressing the DC-DC converter circuit to open, this restriction on low pressure operation is problematic especially, is impossible because this converter provides high voltage.In addition, although the operation control lag is to keep non-overlapped triggering signal output, this delay tuning circuit often can not keep a constant-duty cycle of circuits for triggering output, and therefore, the output of DC-DC converter voltage is not constant.

Summary of the invention

[0008] system and method that the present invention relates to, use directly reset-set (RS) triggers in the whole service voltage range of type circuit structure provides a pierce circuit to export non-overlapped triggering signal.Embodiments of the invention use the output driving buffer of rest-set flip-flop circuit structure inside that oscillator feedback delay is provided, thereby a self-oscillatory circuit structure is provided.Preferably, adopt feedback control circuit not merely to provide feedback delay to guarantee any one delay that drives buffer.Therefore, the control circuit of embodiment provides FEEDBACK CONTROL, make the signal that is fed propagate through each output driving buffer, thereby the triggering signal that pierce circuit continues to provide non-overlapped in whole large-scale working voltage is exported.Embodiments of the invention also adopt the input delay circuit, to keep constant relatively resetting and set input feedback delay ratio in whole aforementioned large-scale working voltage.So the pierce circuit of the embodiment of the invention provides a kind of self-maintained circuit, the non-overlapped triggering signal output that it provides has a relative constant-duty cycle on the working voltage on a large scale.

[0009] oscillator circuit structure of the present invention does not need programmed delays or complicated delay tuning circuit, therefore, can avoid the shortcoming relevant with sort circuit.Correspondingly, pierce circuit of the present invention is operation reliably on low pressure more, is 6 volts in using at CMOS, even boosting and falling-rising presses the DC-DC converter circuit also easily to use in starting.In addition, adopt pierce circuit of the present invention, can use less physical space (as chip area (die area)) and less cost.

[0010] aforementioned feature of the present invention and the technical advantage set forth quite widely is so that can understand detailed description of the present invention better.Further feature of the present invention and advantage will be in following descriptions, and it has constituted claim project of the present invention.The notion that it should be appreciated by those skilled in the art that disclosure can be used at an easy rate as the basis with specific embodiment and be used for revising or designing other structure to finish identical purpose of the present invention.Those skilled in the art should be realized that also this structure that is equal to is not offset the spirit and scope of the present invention of setting forth in the claims.The novel features that is considered to characteristics of the present invention, its structure and How It Works, and further purpose and advantage also will be better understood in conjunction with the accompanying drawings from following description.But, should recognize profoundly that each feature that provides all only is in order to describe and to illustrate, rather than is intended to limit definition of the present invention.

Description of drawings

[0011] for a more complete understanding of the present invention, existing in conjunction with the accompanying drawings also with reference to following description, wherein;

[0012] Figure 1A shows the NOR type rest-set flip-flop circuit that uses according to the embodiment of the invention;

[0013] Figure 1B shows the NAND type rest-set flip-flop circuit that uses according to the embodiment of the invention;

[0014] Fig. 2 A and 2B show the sequential chart of the flip-flop circuit of Figure 1A and 1B;

[0015] Fig. 3 A shows the NOR type rest-set flip-flop circuit of Figure 1A, and it has the feedback delay circuit that is arranged in the cross-couplings signal path according to the embodiment of the invention;

[0016] Fig. 3 B shows the NAND type rest-set flip-flop circuit of Figure 1B, and it has the feedback delay circuit that is arranged in the cross-couplings signal path according to the embodiment of the invention;

[0017] Fig. 4 A and 4B show the feedback signal path of Fig. 3 A flip-flop circuit embodiment of varying input signal level;

[0018] Fig. 5 A shows a rest-set flip-flop type oscillator that has FEEDBACK CONTROL according to the embodiment of the invention;

[0019] the various embodiment of Fig. 5 B-5G display delay circuit, it can be used in the pierce circuit of Fig. 5 A;

[0020] the NOR type rest-set flip-flop circuit of Fig. 6 A displayed map 3A, it has the FEEDBACK CONTROL of Fig. 5 A according to the embodiment of the invention;

[0021] the NAND type rest-set flip-flop circuit of Fig. 6 B displayed map 3B, it has the FEEDBACK CONTROL of Fig. 5 A according to the embodiment of the invention;

[0022] Fig. 7 A and 7B show the FEEDBACK CONTROL running according to Fig. 6 A of the embodiment of the invention;

[0023] Fig. 8 A, Fig. 8 B, Fig. 8 C and Fig. 8 D are presented at the generation and the sequential of signal delay in the NAND type rest-set flip-flop circuit of the embodiment of the invention; With

[0024] Fig. 9 shows the curve chart according to the work period contrast feedback delay of exemplary embodiments.

Detailed Description Of The Invention

Describing when of the present invention, should be realized that [0025] in order to provide reliably and voltage transitions accurately, the oscillator that uses should satisfy some operation standards in the DC-DC voltage changer.Particularly, this oscillator should provide stable self-oscillation, and the vibration of synchronous or non-overlapped triggering signal output is provided, and the work period of vibration should be constant.The previous various pierce circuits that have been proposed for the DC-DC converter are found it and can not provide satisfactory performance about one or more aforementioned operation standards.In addition, many previous pierce circuit more complicated, with high costs and/or take sizable physical space (as requiring the integrated circuit (IC) chip space of unimaginable number).

[0026], can observe the triggering signal output that the rest-set flip-flop circuit structure can be used to provide non-overlapped with reference to Figure 1A, 1B, 2A and 2B.Can find that from Figure 1A NOR type rest-set flip-flop circuit structure 100A comprises cross-linked NOR door 101A and 102A, so that a rest-set flip-flop circuit to be provided.Shown in Figure 1B, NAND type rest-set flip-flop circuit structure 100B comprises cross-linked NAND door 101B and 102B, so that a rest-set flip-flop circuit to be provided.In each aforesaid rest-set flip-flop circuit structure, input R and S are coupling in together by an inverter (inverter) (the inverter 103A in Figure 1A and the inverter 103B in Figure 1B), so that when signal in input when being high on the R, signal is low importing on the S.

[0027] shown in Fig. 2 A, NOR type rest-set flip-flop circuit structure 100A provides non-overlapped high output signal level on output QB and Q.Can see that from the sequential chart of Fig. 2 A as input D when being low (R be low and S is high), output QB is high and Q is low, and as input D when being high (R be high and S is low), export QB and be low and Q is high.What induce one interest most about the non-overlapped triggering signal output facet of circuit is such fact: promptly at input D from low high and from the transition period that height drops, output QB and Q will never be high simultaneously, shown in the regional 201A-203A of Fig. 2 A.Therefore, output QB and the output of the high level on the Q at rest-set flip-flop circuit structure 100A can be utilized as a non-overlapped triggering signal.

[0028] similarly, shown in Fig. 2 B, NAND type rest-set flip-flop circuit structure 100B provides non-overlapped low-output signal level on output QB and Q.Can see that from the sequential chart of Fig. 2 B as input D when being low (R be low and S is high), output QB is high and Q is low, and as input D when being high (R be high and S is low), export QB and be low and Q is high.From low high and from the transition period that height drops, output QB and Q will never be low simultaneously, shown in the regional 201B-203B of Fig. 2 B at input D.Therefore, output QB and the output of the low level on the Q at rest-set flip-flop circuit structure 100A can be utilized as a non-overlapped triggering signal.

[0029] aforementioned non-overlapped triggering signal output characteristic is provided by the cross-couplings circuit structure that above NOR type (Figure 1A) and NAND type (Figure 1B) realize.Although good non-overlapped output signal feature is provided, aforesaid rest-set flip-flop structure can not move the self-oscillation that has constant-duty cycle to provide, thereby is not suitable for using the unlatching pierce circuit as a DC-DC converter.

[0030], shown the rest-set flip-flop circuit structure that can be made into self-oscillation and continue to provide non-overlapped triggering signal output with reference to figure 3A and 3B.Particularly, the NOR type rest-set flip-flop circuit structure 300A of described embodiment comprises feedback delay circuit, pdriver 301A and ndriver 302A in Fig. 3 A, on the cross-couplings signal path of NOR door 101A and 102A.Similarly, the NAND type rest-set flip-flop circuit structure 300B of described embodiment comprises feedback delay circuit, pdriver 301B and ndriver 302B in Fig. 3 B, on the cross-couplings signal path of NAND door 101B and 102B.The pdriver 301A of embodiment and 301B and ndriver 302A and 302B are output buffers, it may comprise an operational amplifier as a buffer amplifier, the buffering of output signal (QB and Q) is provided and produces a delay (as in the 10-100nsec scope) in signal path.Separately by 301A, 301B (pdriver delay=t _PD) and 302A, 302B (ndriver delay=t _ND) introduce the delay in the signal path, or, can provide enough signal delay in conjunction with other delay (input delay circuit as described below) relevant with other signal path, so that the self-oscillation of rest-set flip-flop circuit structure to be provided, this will be in following description.

[0031] although the embodiment of the invention described above can utilize buffer amplifier as feedback delay circuit, but other embodiments of the invention can also be utilized various other circuit, as long as sort circuit can provide enough delays that the self-oscillation of rest-set flip-flop circuit structure described herein is provided.For example, about any pdriver 301A or 301B or ndriver 302A or 302B, the embodiment of the invention can be used resistor and capacitor circuit, delay line, active device etc.

[0032] for a self-maintained circuit is provided, the output (being QB or Q) of NOR type rest-set flip-flop circuit structure 300A, or similarly, the output of NAND type rest-set flip-flop circuit structure 300B is fed and is fed back into (being D).Fig. 4 A and 4B demonstration output QB are fed and are fed back into D, are used for the self-oscillation of NOR type rest-set flip-flop circuit structure 300A.Signal will adopt shortest path through finishing circuit.Therefore, shown in the dotted line in Fig. 4 A, when the input signal on D when being high, feedback signal will comprise the delay that is produced by pdriver 301A, rather than the delay that is produced by ndriver 302A.But shown in the dotted line in Fig. 4 B, when the input signal on D when being low, feedback signal is through comprising the delay that is produced by pdriver 301A and ndriver 302A.In NOR type rest-set flip-flop circuit structure 300A, Q is fed when being fed back into D when output, and in NAND type rest-set flip-flop circuit structure 300B, when output QB or output Q are fed when being fed back into D, can obtain similar result (when input signal when being high and low, the delay that produces varying number).

[0033] delay of the varying number that produces when being high and low when input signal will can not stop circuit to produce self-oscillation, although if single delay (as the delay that is produced by pdriver 301A in the circuit structure of Fig. 4 A) enough is used to provide vibration, but an output triggering signal is used for controlling the pierce circuit of DC-DC converter, and this running is normally unsafty.The i.e. delay that is produced by delay circuit (as pdriver 301A, 301B and ndriver 302A, 302B) may change along with the difference of service conditions, as working voltage, temperature, service life etc.In addition, the variation in the delay that is provided by a pair of phase delay circuit (as pdriver 301A, ndriver 302A or pdriver 301B, ndriver 302B) can not be similar identical mutually.Because the delay that is provided by a corresponding delay circuit can begin dominating role, as because supply voltage falls, and output QB and Q become and be not synchronous, therefore, can not rely on circuit provides DC-DC to change needed non-overlapped triggering signal.

[0034] embodiments of the invention provide a feedback control circuit not only to provide feedback delay with the delay of guaranteeing any one delay circuit.Therefore, the control circuit of embodiment provides FEEDBACK CONTROL, make the signal that is fed propagate and pass each output driving buffer, thereby the triggering signal that pierce circuit continues to provide non-overlapped in whole large-scale working voltage is exported.Offset any variation difference of each sort buffer driver on the service conditions practical range according to the deferred run of each this driving buffer of embodiments of the invention.Be that embodiments of the invention can carry out self calibration to the difference on the feedback delay, so that non-overlapped triggering signal output to be provided.Therefore, the embodiment of the invention can reliably and predictably be moved in the service conditions scope, and does not need programmed delays complicated and with high costs or complicated delay tuning circuit.

[0035] with reference to figure 5A, shown rest-set flip-flop type pierce circuit 500 according to the embodiment of the invention, be used for exporting non-overlapped triggering signal and be used to control the DC-DC converter.Rest-set flip-flop circuit 300 can comprise that any suitable R S triggers the type circuit, as the NOR type rest-set flip-flop circuit structure 300A of Fig. 3 A or the NAND type rest-set flip-flop circuit structure 300B of Fig. 3 B.Rest-set flip-flop type pierce circuit 500 comprises switching circuit 501, preferably include solid-state switch (as transistor), although can use other switching device (as the physical switch contact), under the control of controller 502, move, controller preferably includes control logic, as concrete application integrated circuit form or general processor form.The switching circuit 501 of a preferred embodiment comprises the multiplexer (MUX) of an operation under controller 502 controls.The controller 502 of described embodiment is connected to input D, so that detect status input signal (as high or low), and control switch circuit 501 is used for oscillatory feedback with a suitable input D that outputs to who connects among output QB and the Q.The controller 502 monitoring input D that are described embodiment are with control switch circuit 501, make that feeding back to input D from output (QB or Q) is used for oscillatory signal and comprises the delay that is produced by pdriver 301 and ndriver 302.

[0036] inverter 503 that provides between output Q and the switching circuit 501, the feedback signal level that provides a feedback signal level correspondence to be provided by output QB are provided.Promptly export QB and Q and be reverse mutually, therefore use QB output and Q to export and be used for feedback oscillation, one or another feedback signal are reversed.

[0037], shown the details of special rest-set flip-flop circuit embodiments of the rest-set flip-flop type pierce circuit of relevant Fig. 5 A with reference to figure 6A and 6B.Particularly, Fig. 6 A shows NOR type rest-set flip-flop oscillator circuit structure 600A, and Fig. 6 B shows NAND type rest-set flip-flop oscillator circuit structure 600B.The switching circuit 501 of switching circuit 501A and 501B and inverter 503A and 503B corresponding diagram 5A and inverter 503.Although it is not shown in the diagram in order to simplify, preferably, NOR type rest-set flip-flop oscillator circuit structure 600A and NAND type rest-set flip-flop oscillator circuit structure 600B comprise controller circuitry, as the controller 502 of Fig. 5 A, are connected to switching circuit 501A and 501B so that said control to be provided.

[0038] as in Fig. 6 A, seeing, preferably, the switching circuit 501A Be Controlled of NOR type rest-set flip-flop oscillator circuit structure 600A, make when input D when being high on output Q feedback signal, and when to import D be low, exporting feedback signal on the QB.Be appreciated that from the description of above Fig. 4 A and 4B the control of this feedback signal causes the delay of pdriver 301A and ndriver 302A, is introduced in the feedback signal as input D when being high and low.This represents with dotted line in Fig. 7 A and 7B.

[0039] preferably, the switching circuit 501B Be Controlled of NAND type rest-set flip-flop oscillator circuit structure 600B, make when input D when being high on output QB feedback signal, and when to import D be low, exporting feedback signal on the Q, shown in Fig. 6 B.Moreover, being appreciated that from the discussion of Fig. 4 A and 4B the control of this feedback signal causes the delay of pdriver 301B and ndriver 302B, it is introduced in the feedback signal when being high and low as input D.

[0040] described a kind of oscillator circuit structure more than, it is self-oscillation and non-overlapped triggering signal output is provided.But owing to change (as change in voltage) in the delay that is provided by delay circuit (being pdriver 301 and ndriver 302 in above embodiment) on the circuit service conditions, the work period of triggering signal output may change.Be high time cycle with signal on output QB promptly be high time will can not maintain a constant ratio, because the delay difference that produces by delay circuit at signal on the output D.But, when being provided for the triggering signal of DC-DC conversion, expect to have constant or more constant trigger signal duty, so that consistent and predictable DC-DC change-over circuit output voltage are provided.

[0041] therefore, embodiments of the invention adopt the input delay circuit, with in the whole service condition and range, keep a constant relatively replacement with the input feedback delay ratio of setting.Referring again to Fig. 5 A, input delay circuit 504 and 505 are arranged in the input of rest-set flip-flop circuit 300. Input delay circuit 504 and 505 is preferably used in provides delay (t _DBAnd t _D), keep constant or constant relatively ratio on its all service conditionss in the whole service condition and range.For example, input delay circuit 504 and 505 can adopt capacitor, and its running is not influenced by working voltage, so that the constant ratio that postpones between input delay circuit 504 and 505 to be provided in the whole service voltage range.The embodiment of Fig. 5 B and 5C display delay circuit 504 and 505 wherein adopts resistor and capacitor circuit according to the embodiment of the invention.According to following equation, the delay ratio that is provided by the delay circuit 504 and 505 of Fig. 5 B and 5C can be expressed as:

$\frac{t_{\mathrm{DB}}}{t_D}=\frac{\mathrm{RC}}{(N\×R)(M\×C)}---\left(1\right)$

To preferentially select the special circuit structure and the assembly of Fig. 5 B and 5C delay circuit 504 and 505, to provide aforesaid maintenance constant or constant relatively ratio on all service conditionss in the service conditions scope.

[0042] also can use except at those circuit structures described in Fig. 5 B and the 5C embodiment and other circuit structures and the assembly the assembly, can be used to provide delay according to the embodiment of the invention.For example, Fig. 5 D and 5E show the delay circuit 504 of use active device and 505 embodiment.Fig. 5 F and 5G show the delay circuit 504 of use delay line (using a string delay buffer at this) and 505 embodiment.

[0043] according to preferred embodiment, input delay circuit 504 and 505 provides delay (delay circuit 504 delay=t _DBWith delay circuit 505 delay=t _D), the delay (t that its domination (dominate) is provided by the feedback delay circuit on all service conditionss of (as in the whole service voltage range) in the service conditions scope _PDAnd t _ND)." arrange (dominate) " as used herein and be meant that main (dominating) postpones to postpone an enough big quantity greater than non-main (non-dominating) and implement mainly to postpone control.Work period or delay ratio (Duty cycle or delay ratio) that the delay that provides from described embodiment produces can be expressed as:

$\mathrm{Duty\; cycle}\left(\mathrm{delay\; ratio}\right)=\frac{t_D+(t_{\mathrm{PD}}+t_{\mathrm{ND}})}{t_{\mathrm{DB}}+t_D+(t_{\mathrm{PD}}+t_{\mathrm{ND}})\×2}---\left(2\right)$

Be longer than oscillator frequency, t if suppose mains voltage variations (as owing to exhaust the electric voltage dropping of battery or battery life) _PDAnd t _NDTo be similar.So, can be reduced at the work period or the delay ratio of equation (2) lining:

$\mathrm{Duty\; cycle}\left(\mathrm{delay\; ratio}\right)\≈\frac{t_D+(t_{\mathrm{PD}}\×2)}{t_{\mathrm{DB}}+t_D+(t_{\mathrm{PD}}\×4)}---\left(3\right)$

[0044], is appreciated that and works as t from above equation _PDWhen being top dog, the minimum work period is 50%.Along with t _PDThe irrelevant weight that becomes, the work period with the t that depend on more _DAnd t _DBRatio.For example, the hypothetical target work period is 70%, and target frequency is 500KHz (2000ns), t _DBe 1400ns, t _DBBe 600ns, and t _PD=t _NDBy at log scale change t _PDDelay is (1ms) from 0ns to 1000000ns, and the minimum work period is maintained 50%.This relation such as Fig. 9 graphical representation.

[0045] Fig. 8 A-8D shows according to the described constant duty cycle trigger signal output that provides of preamble.Particularly, Fig. 8 A has shown the delay that produces when being high as input D in RS D-flip flop oscillator circuit structure 600A.The typical sequential chart of the correspondence shown in Fig. 8 B has illustrated that the work period maintenance of output triggering signal QB and Q is constant, shown in high output time 801 and 802.Fig. 8 C shows the delay that produces in RS D-flip flop oscillator circuit structure 600A when to import D be low.The typical sequential chart of the correspondence shown in Fig. 8 D has illustrated that the work period of output triggering signal QB and Q keeps constant and (should be appreciated that t _PDAnd t _NDBe inessential), shown in high output timing 803 and 804.

[0046] from above description, should be appreciated that, the described embodiment running of rest-set flip-flop type pierce circuit 500 provides a self-maintained circuit, and it provides the non-overlapped triggering signal output with relative constant-duty cycle in a large-scale working voltage.Correspondingly, the rest-set flip-flop type pierce circuit of the embodiment of the invention provides a pierce circuit that uses in the DC-DC conversion, so that consistent and predictable voltage transitions to be provided.In addition, rest-set flip-flop type pierce circuit as described herein can move on the low-voltage reliably very much, as 6 volts in using at CMOS, promptly is used in and boosts and the unlatching of falling-rising pressure DC-DC converter circuit.In addition, the enforcement of the rest-set flip-flop type pierce circuit of the embodiment of the invention can be used less physical space (as chip area) and lower cost.

[0047] although embodiments of the invention described here are with reference to the pierce circuit that uses in the DC-DC converter, should be appreciated that rest-set flip-flop type pierce circuit of the present invention can be used for many different application.For example, pierce circuit described here can be used for various timing circuits (timing circuit), presses converter etc. as charge pump (charge pump), falling-rising.

[0048] although described the present invention and advantage thereof in detail, should be appreciated that, in non-migration such as the defined the spirit and scope of the present invention of claim, can make various variations, replacement and change.In addition, the specific embodiment of the scope used of the present invention process, machine, manufacturing, material composition, mode, method and the step that are not limited in specification, describe.From disclosure of the present invention, those skilled in the art will utilize easily and carry out with the corresponding embodiment identical function of explanation here in fact or realized the existing of identical result or later on process, machine, manufacturing, material composition, mode, method or the step of exploitation.Therefore, claims are intended to comprise these processes, machine, manufacturing, material composition, mode, method or step.

Claims (21)

1. system comprises:

One directly reset-(it has the cross-couplings signal path for reset-set, RS) flip-flop circuit, and the circuit element of described rest-set flip-flop circuit is connected, and described rest-set flip-flop circuit has an input and a plurality of output at least in set;

First delay circuit is positioned in first path of described cross-couplings signal path, and described first delay circuit provides first signal delay; With

Second delay circuit, be positioned in second path of described cross-couplings signal path, described second delay circuit provides secondary signal to postpone, wherein when described output is fed back described input, select described first and second signal delays to combine, so that the self-oscillation of described rest-set flip-flop circuit to be provided in a working voltage expected range.

2. system according to claim 1 also comprises:

A gate-controlled switch circuit is connected between described a plurality of output and the described input, provides controlled signal output to feed back to described input in each described output.

3. system according to claim 2 also comprises:

A controller is connected with described input with described gate-controlled switch circuit, and described controller can move with the signal of monitoring in described input, and controls described gate-controlled switch circuit accordingly.

4. system according to claim 2 also comprises:

A controller is connected with described gate-controlled switch circuit, and described controller can move to control described switching circuit, makes a signal that is fed back to described input always comprise that described first signal delay and described secondary signal postpone.

5. system according to claim 1 also comprises:

A plurality of input delay circuit, be positioned in the signal path that is connected to described at least one input, described a plurality of input delay circuit provides an input delay separately, wherein selects described input delay to keep a relevant constant ratio separately in the working voltage of whole described expected range.

6. described input delay is wherein selected by system according to claim 5, postpones greater than first signal delay on all voltages of the working voltage of described expected range and secondary signal.

7. system according to claim 1, wherein said circuit element comprises:

A plurality of cross-linked NOR doors.

8. system according to claim 1, wherein said circuit element comprises:

A plurality of cross-linked NAND doors.

9. system according to claim 1, wherein said first delay circuit and described second delay circuit comprise a buffer circuits separately.

10. system according to claim 9, wherein said buffer circuits comprises an operational amplifier separately.

11. a system comprises:

A rest-set flip-flop circuit, it has the cross-couplings signal path, and with the circuit element connection of described rest-set flip-flop circuit, described rest-set flip-flop circuit has an input and a plurality of output at least;

First delay circuit is positioned on first path of described cross-couplings signal path, and described first delay circuit provides first signal delay;

Second delay circuit, be positioned on second path of described cross-couplings signal path, described second delay circuit provides secondary signal to postpone, and wherein said first and second signal delays change separately about the voltage difference in the working voltage of an expected range; With

A gate-controlled switch circuit is connected between described a plurality of output and the described input, provides controlled signal output to feed back to described input in each described output.

12. system according to claim 11 also comprises:

A controller is connected with described input with described gate-controlled switch circuit, and described controller can move with the signal of monitoring in described input, and controls described gate-controlled switch circuit accordingly.

13. system according to claim 11 also comprises:

A controller is connected with described gate-controlled switch circuit, and described controller can move to control described switching circuit, makes a signal that feeds back to described input always comprise that described first signal delay and described secondary signal postpone.

14. described first and second signal delays are wherein selected by system according to claim 11, so that the self-oscillation of described rest-set flip-flop circuit to be provided in the working voltage of whole described expected range.

15. system according to claim 11 also comprises:

A plurality of input delay circuit, be positioned on the signal path that connects described at least one input, described a plurality of input delay circuit provides an input delay separately, wherein selects described input delay so that keep a relevant constant ratio separately in the working voltage of whole described expected range.

16. described input delay is wherein selected by system according to claim 15, postpones greater than first signal delay on all voltages of the working voltage of described expected range and secondary signal.

17. a method comprises:

The first input delay circuit is arranged on the first cross-couplings signal path of rest-set flip-flop circuit;

The second input delay circuit is arranged on the second cross-couplings signal path of described rest-set flip-flop circuit;

Between first and second outputs of described rest-set flip-flop circuit and the input of described rest-set flip-flop circuit, connect a gate-controlled switch circuit; With

Control described gate-controlled switch circuit selecting one in described first and second outputs to export to feed back to described input especially, a delay that makes feedback signal always comprise to provide and a delay that provides by described second delay circuit by described first delay circuit.

18. method according to claim 17 also comprises:

The first input delay circuit is arranged on the first input signal path of described rest-set flip-flop circuit;

The second input delay circuit is arranged on the second input signal path of described rest-set flip-flop circuit, the wherein said first input delay circuit is selected so that a relevant constant delay ratio separately to be provided in whole expectation working voltage scope with the described second input delay circuit.

19. method according to claim 18, wherein said first input delay circuit and the described second input delay circuit are set in the feedback loop (feedback loop) by the described gate-controlled switch definition that is connected to described first and second outputs and described input.

20. method according to claim 17 also comprises:

According to the described gate-controlled switch circuit of conversion, export non-overlapped triggering signal.

21. method according to claim 20 also comprises:

Described non-overlapped triggering signal to a voltage converter circuit is provided.

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