CN101494196B

CN101494196B - Method for preparing low-voltage, low power consumption, high-density phase-change memory cell array

Info

Publication number: CN101494196B
Application number: CN2009100459295A
Authority: CN
Inventors: 宋志棠; 冯高明; 钟旻; 刘波; 封松林
Original assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Current assignee: Shanghai Institute of Microsystem and Information Technology of CAS
Priority date: 2009-01-22
Filing date: 2009-01-22
Publication date: 2010-08-04
Anticipated expiration: 2029-01-22
Also published as: CN101494196A

Abstract

The invention provides a method for preparing a phase-changing memory cell array with low voltage, low power consumption and high density. The method comprises the following steps: a first dielectric material layer, a phase-changing material layer and a second dielectric material layer are deposited in sequence on a substrate with CVD technology; a nanometer pattern is prepared on a structure already formed with an exposure technique of CMOS standard under 90nm or an electron beam exposure technique, and etched with dry etching process into a nano-columnar structure by RIE; an insulating layer is deposited on the nano-columnar structure with CVD technology and smoothened to the second dielectric material layer with a chemical mechanical polishing technology; then a metal layer as a top electrode material is deposited on the smoothened structure by the CVD technology; and finally a nanometer top-electrode pattern is formed by etching on the metal layer with the exposure technique of CMOS standard under 90nm or the electron beam exposure technique so as to obtain the nanometer phase-changing memory cell array. With the method, the nanometer phase-changing memory cell array under 100nm with low power consumption and high density can be prepared.

Description

The preparation method of low-voltage and low-power dissipation, high-density phase-change memory cell array

Technical field

The present invention relates to a kind of preparation method of phase-change memory cell array, the preparation method of particularly a kind of low-voltage and low-power dissipation, high-density phase-change memory cell array.

Background technology

Phase transition storage (Chalcogenide random access memory based on sulphur based semiconductor alloy material, C-RAM) have that driving voltage is low, power consumption is little, read or write speed is fast, storage density is high,, and outstanding feature such as non-volatile good with CMOS standard technology compatibility, become the focus that each major company of the world, research institution pay close attention to.From 2003, international semiconductor TIA thought that always phase transition storage most possibly replaces current main product such as SRAM, DRAM, FLASH and becomes non-volatile semiconductor memory of future generation.Main in the world semiconductor company all is being devoted to the research and development of phase transition storage at present, there are Ovonyx, Intel, Samsung, ST Micron, Hitachi, AMD etc. in main research unit, wherein the most representative with Samsung, they utilized the 90nm processing line successfully to develop the 512M phase transition storage in 2006.

Yet if will realize the industrialization of phase transition storage, phase transition storage just must develop toward high speed, high density, low pressure, low-power consumption direction, to replace existing memory technology.And the most crucial part of phase transition storage is exactly the zone that phase-change material underwent phase transition, realized memory function, because it directly determines driving voltage, power consumption and the integrated level of phase transition storage.On the other hand, recent decades, microelectronic technique developed rapidly according to Moore's Law, many in the world major companies are in CMOS processing lines such as research and development 45nm, 32nm, therefore, how to utilize the following CMOS standard technology of 90nm to prepare highdensity nano phase change memory cell array and become the technical task that those skilled in the art need to be resolved hurrily in fact.

Summary of the invention

The object of the present invention is to provide the preparation method of a kind of low-voltage and low-power dissipation, high-density phase-change memory cell array,, effectively reduce the driving voltage and the power consumption of phase transition storage to prepare the high-density phase-change memory cell array below the 100nm.

Reach other purposes in order to achieve the above object, the preparation method of low-voltage and low-power dissipation provided by the invention, high-density phase-change memory cell array comprises step: 1) utilize the CVD technology to deposit first layer of dielectric material, phase-change material layers, second layer of dielectric material successively to form three layer stack structures on substrate; 2) utilize 90nm following CMOS technological standards exposure technique or electron beam lithography on described three layer stack structures, to prepare nano graph; 3) utilize RIE with described nano graph dry etching to the described first dielectric material laminar surface to form the nanometer column structure; 4) utilize the CVD technology on described nanometer column structure, to deposit an insulating barrier that described nanometer column structure is encased; 5) body structure surface that utilizes chemical Mechanical Polishing Technique will have insulating barrier polishes to described second layer of dielectric material; 6) utilize the CVD technology on the structure that has polished, to deposit metal level as upper electrode material; 7) utilize 90nm following CMOS technological standards exposure technique or electron beam lithography etching on described metal level to form nanometer top electrode figure to obtain the nano phase change memory cell array.

Wherein, the material that described first layer of dielectric material and described second layer of dielectric material adopt can be a kind of among Al, Cu, Ti, TiN, the W, and both thickness can be 20～500nm; The adoptable material of described phase-change material layers is the phase-change alloy material that monobasic, binary, ternary, quaternarys such as Ge2Sb2Te5, Ge1sb2Te4, Sb2Te3, GeTe, Si2Sb2Te5, Sb have memory function, and its thickness is 20～200nm; The material that described insulating barrier adopts can be SiNx or SiO2; The material that described metal level adopts can be Ti, TiN or W.

Preferably, after the etching of step 3) was finished, execution in step 4 under the situation of not removing photoresist).

In sum, the preparation method of low-voltage and low-power dissipation of the present invention, high-density phase-change memory cell array utilizes the exposure technique of high-resolution such as 90nm following CMOS standard technology exposure technique or electron beam exposure, in conjunction with dry etching and chemical Mechanical Polishing Technique, can prepare the nano phase change memory cell array of the following high density low-power consumption of 100nm.

Description of drawings

Fig. 1 to Fig. 6 is the preparation method's of low-voltage and low-power dissipation of the present invention, high-density phase-change memory cell array an operating process schematic diagram.

Embodiment

See also Fig. 1 to Fig. 6, the preparation method of low-voltage and low-power dissipation of the present invention, high-density phase-change memory cell array may further comprise the steps:

At first, utilize the CVD technology on substrate 1, to deposit first layer of dielectric material 2 successively, phase-change material layers 3, second layer of dielectric material 4 is to form three layer stack structures, as shown in Figure 1, wherein, the material that described first layer of dielectric material 2 and second layer of dielectric material 4 are adopted can be: Al, Cu, Ti, TiN or W etc., the thickness of described first layer of dielectric material 2 can be 20～500nm, the thickness of described second layer of dielectric material can be 20～500nm, the material that described phase-change material layers adopts can be Ge2Sb2Te5, Ge1sb2Te4, Sb2Te3, GeTe, Si2Sb2Te5, monobasics such as Sb, binary, ternary, quaternary has the phase-change alloy material of memory function, and its thickness is 20～200nm.

Then, utilize 90nm following CMOS technological standards exposure technique or electron beam lithography on described three layer stack structures, to prepare nano graph, as shown in Figure 2.

Then, under the situation of not removing photoresist 5, utilize RIE with described nano graph dry etching to described first layer of dielectric material 2 surfaces to form the nanometer column structure, as shown in Figure 3.Certainly, also can under the situation of having removed photoresist 5, carry out dry etching.

Then, utilize the CVD technology to deposit an insulating barrier 6 that described nanometer column structure is encased on described nanometer column structure, the material of employing can be SiNx or SiO2, as shown in Figure 4.

Then, the body structure surface that utilizes chemical Mechanical Polishing Technique will have insulating barrier 6 polishes to described second layer of dielectric material 4 surfaces, as shown in Figure 5.

Then, utilize the CVD technology to deposit metal level 7 as upper electrode material on the structure that has polished, the material of employing can be Ti, TiN or W etc.

At last, utilize 90nm following CMOS technological standards exposure technique or electron beam lithography etching on described metal level to form nanometer top electrode figure to obtain the nano phase change memory cell array, as shown in Figure 6.

In sum, the preparation method of low-voltage and low-power dissipation of the present invention, high-density phase-change memory cell array utilizes 90nm following CMOS technological standards exposure technique or electron beam lithography phase-change memory cell can be defined into below the 100nm, reduced the contact area of phase-change material and heating electrode, thereby reduce the driving voltage and the power consumption of phase transition storage, improved the density of phase transition storage; Moreover, adopt dry etching to form nano-pillar, because the height pattern of reactive ion etching is relatively good, can effectively avoid destruction to phase-change material, improved the stability of phase transition storage; In addition, photoresist can be removed by the technology of chemical polishing, can avoid removing photoresist and can destroy shortcomings such as phase-change memory cell after etching, has improved the stability and the feasibility of phase transition storage.The present invention also is applicable to the particularly required nano-electrode of nanometer electronic device of other electronic devices of preparation, has very big using value.

Claims

1. the preparation method of a low-voltage and low-power dissipation, high-density phase-change memory cell array is characterized in that comprising step:

1) utilize the CVD technology on substrate, to deposit first layer of dielectric material, phase-change material layers, second layer of dielectric material successively to form three layer stack structures;

2) utilize 90nm following CMOS technological standards exposure technique or electron beam lithography on described three layer stack structures, to prepare nano graph;

3) utilize RIE that described nano graph is etched to the described first dielectric material laminar surface to form the nanometer column structure in method;

4) utilize the CVD technology on described nanometer column structure, to deposit an insulating barrier that described nanometer column structure is encased;

5) body structure surface that utilizes chemical Mechanical Polishing Technique will have insulating barrier polishes to described second layer of dielectric material;

6) utilize the CVD technology on the structure that has polished, to deposit metal level as upper electrode material;

7) utilize 90nm following CMOS technological standards exposure technique or electron beam lithography etching on described metal level to form nanometer top electrode figure to obtain the nano phase change memory cell array.

2. the preparation method of low-voltage and low-power dissipation as claimed in claim 1, high-density phase-change memory cell array is characterized in that: the material that described first layer of dielectric material adopts is a kind of among Al, Cu, Ti, TiN, the W.

3. the preparation method of low-voltage and low-power dissipation as claimed in claim 1, high-density phase-change memory cell array is characterized in that: the material that described second layer of dielectric material adopts is a kind of among Al, Cu, Ti, TiN, the W.

4. the preparation method of low-voltage and low-power dissipation as claimed in claim 1, high-density phase-change memory cell array is characterized in that: the material that described phase-change material layers adopts is that Sb monobasic, binary, ternary, quaternary have a kind of in the phase-change alloy material of memory function.

5. the preparation method of low-voltage and low-power dissipation as claimed in claim 1, high-density phase-change memory cell array, it is characterized in that: the thickness of described first layer of dielectric material is 20～500nm, the thickness of described phase-change material layers is 20～200nm, and the thickness of described second layer of dielectric material is 20～500nm.

6. the preparation method of low-voltage and low-power dissipation as claimed in claim 1, high-density phase-change memory cell array is characterized in that: the material that described insulating barrier adopts is SiNx or SiO2.

7. the preparation method of low-voltage and low-power dissipation as claimed in claim 1, high-density phase-change memory cell array is characterized in that: the material that described metal level adopts is a kind of among Ti, TiN, the W.

8. the preparation method of low-voltage and low-power dissipation as claimed in claim 1, high-density phase-change memory cell array is characterized in that: after the etching of step 3) was finished, execution in step 4 under the situation of not removing photoresist).