CN101493494A - Semiconductor element test method and system - Google Patents
Semiconductor element test method and system Download PDFInfo
- Publication number
- CN101493494A CN101493494A CN 200810003873 CN200810003873A CN101493494A CN 101493494 A CN101493494 A CN 101493494A CN 200810003873 CN200810003873 CN 200810003873 CN 200810003873 A CN200810003873 A CN 200810003873A CN 101493494 A CN101493494 A CN 101493494A
- Authority
- CN
- China
- Prior art keywords
- semiconductor element
- boundary
- unit
- those
- testing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Abstract
The invention provides a testing method and a testing system for testing semiconductors; at least one semiconductor element is provided; the semiconductor element is provided with a plurality of units; each unit is provided with a unit state respectively; subsequently, the testing to the semiconductor element is carried out; according to the testing result, the boundary unit of the semiconductor element is defined; the boundary unit state is compared with the prearranged value so as to decide whether the information is sent or not, thus prompting the operator with the possibility of map offset.
Description
Technical field
The present invention relates to a kind of method of testing and system of semiconductor element, particularly survey the determination methods and the system of map migration situation in spot in (chip probe) process at the wafer pin about a kind of.
Background technology
Integrated circuit (IC, integrated circuit) production procedure is the division of labor framework of multilayer level, has comprised integrated circuit (IC) design (IC design), wafer manufacturing (wafer manufacturing), wafer pin survey (circuit probing), encapsulation (assembling) and final test (finaltesting).In the aforesaid production division of labor, the wafer pin is surveyed and final test twice trace routine, all is the important outpost of the tax office of guaranteeing product quality.
Contain many unit on one wafer, these unit are commonly called crystal grain (die) but are not that all crystal grain all has good quality, so method of wafer pin survey, be with each crystal grain on very thin probe (probe card) or small probe (fine-point needle) test wafer, then on bad crystal grain, indicate mark or retain test pattern (mapping file), in order to classification non-defective unit and defective products.Do not survey if carry out the wafer pin, directly cut and encapsulate after the wafer manufacturing is finished, then the packaging cost of defective products is inessential waste.Therefore the wafer pin is surveyed this step can classify non-defective unit and defective products on the wafer, to reduce the cost of encapsulation and follow-up test.
The wafer pin is to have arrived measuring point (first die) with the computer vision Equipment Inspection in surveying, and follows predefined test specification that crystal grain is tested one by one again.In above-mentioned method, correctly do not found if play a measuring point, then test specification can be offset, and causes the mistake of test result, title be map migration (map shift).
Can use artificial judgment to solve this problem at present, with artificial judgment not map shift phenomenon is arranged, each wafer is checked with the method for artificial visual what the method can be comprehensive checks, need the experienced technician can valid function, and the explanation that can't present evidence.
Effectively solution is to preestablish mark crystal grain (marking die), and this mark crystal grain has known crystal grain state, when the test result of mark crystal grain and known test result are different, has then judged the measuring point mistake, the problem of spot map migration.But the method must preestablish mark crystal grain before every test, and the result that step increases also can lose time, and is difficult to implement in full.
Because above disappearance, the method for testing of semiconductor element provided by the present invention and system are improved at prior art.
Summary of the invention
Based on the disappearance that solves above-mentioned prior art, a purpose of the present invention is to provide the method for testing and the system of semiconductor element, in order to whether the phenomenon of ground map migration is arranged in the test process of judging semiconductor element.
The method of testing of semiconductor element provided by the present invention need not to establish in advance mark crystal grain, can increase testing efficiency.
Another object of the present invention is to provide the method for testing and the system of semiconductor element, can reduce manpower requirement, the minimizing time also increases efficient.
A further object of the present invention is to provide the method for testing and the system of semiconductor element, when the situation of ground map migration takes place, sends signal with alert.
According to above-mentioned purpose, the present invention at first provides a kind of method of testing of semiconductor element, provides at least one semiconductor element, and has a plurality of unit on the semiconductor element, and all there is location mode separately each unit; Then carry out the test of semiconductor element, according to the boundary element of test result definition semiconductor element, boundary element state and preset value compare, and whether decision sends information, in order to alert.
The present invention then provides a kind of test macro of semiconductor element, is to comprise proving installation, and in order to the measuring semiconductor element, semiconductor element has then comprised a plurality of unit, and all there is location mode separately each unit; Test result can define boundary element via definition device; Utilize selecting arrangement or indication device in boundary element, to select the target unit; Utilize arithmetic unit to judge the information of whether sending again.
Description of drawings
Fig. 1 is of the present invention and surveys the skew synoptic diagram;
Fig. 2 is the boundary element definition synoptic diagram of a preferred embodiment of the present invention;
Fig. 3 is the judgement ground map migration synoptic diagram of a preferred embodiment of the present invention;
Fig. 4 is the judgement ground map migration synoptic diagram of a preferred embodiment of the present invention;
Fig. 5 is the judgement ground map migration synoptic diagram of a preferred embodiment of the present invention; Wherein:
Fig. 5 a be border crystal grain Y is divided into about two relative groups;
Fig. 5 b is divided into two relative groups up and down with border crystal grain Y;
Fig. 5 c is divided into upper right and two the relative groups in lower-left with border crystal grain Y;
Fig. 5 d is divided into upper left and two the relative groups in bottom right with border crystal grain Y.
[main element symbol description]
1 crystal grain state (available)
3 crystal grain states (short circuit)
4 crystal grain states (open circuit)
100 wafers
102 crystal grain
110 measurement ranges
Subscriber line test figure
Y border crystal grain
Y1 target crystal grain
A1-A4 boundary element group
Embodiment
Because the present invention is a kind of method of testing and system of semiconductor element, some ultimate principles that wherein used belong to that personage institute that this field has common knowledge can understand easily, so repeat no more.And graphic with what hereinafter contrasted, be to express the signal relevant with feature of the present invention, also do not need according to the complete drafting of physical size, illustrate formerly.
At first, please refer to shown in Figure 1ly, is synoptic diagram according to a preferred embodiment of the present invention.As shown in Figure 1, provide semiconductor element earlier, this semiconductor element is wafer 100 in the present embodiment, and a plurality of unit that comprised in the wafer 100 are crystal grain 102.Then, when wafer 100 being tested with proving installation, make measurement range 110 when depart from the upper right side when playing the measuring point skew, then test result is shown in the test Figure 112 among Fig. 1, digitized representation crystal grain state among test Figure 112, wherein crystal grain state 1 is represented available crystal grain, and crystal grain state 3 is represented crystal grain short circuit (short), and crystal grain state 4 is represented crystal grain open circuit (open).In the ordinary course of things, the defect test of crystal grain 102 can be carried out earlier, when the test mode of crystal grain 102 is open circuit or short circuit, mistake can be referred to as; Perhaps when the test mode of crystal grain 102 and expecting state not simultaneously, also can be described as mistake.
Then, as shown in Figure 2, be that the present invention is in order to judge the synoptic diagram of border crystal grain.Arbitrary crystal grain X in the present embodiment is up to 8 adjacent crystal grain, and when a certain crystal grain 102 in the test result has when being less than 8 adjacent crystal grain, then definition device can judge that this crystal grain is border crystal grain Y.
Following, please refer to Fig. 3, is another preferred embodiment synoptic diagram that the present invention judges the ground map migration.As shown in Figure 3, after defining border crystal grain Y, (or all) border crystal grain is target crystal grain Y1 to utilize selecting arrangement to select part, utilizing arithmetic unit to calculate number of errors among the target crystal grain Y1 has and does not arrive preset value, when number of errors arrives preset value, arithmetic unit can send a signal, the situation of the ground map migration that expresses possibility.
Then, please refer to Fig. 4, is the preferred embodiment synoptic diagram again that the present invention judges the ground map migration.As shown in Figure 4, after defining border crystal grain Y, utilize sorter that border crystal grain Y is categorized as four boundary element groups such as A1, A2, A3, A4 according to the position, utilize arithmetic unit to calculate crystal grain number of states in the one or more boundary element group, when some crystal grain state in these boundary element groups (for example open circuit, short circuit or other represent different electrical crystal grain states) when quantity arrives preset value, then arithmetic unit can send a signal, the situation of the ground map migration that expresses possibility.
According to a preferred embodiment of the present invention, after defining border crystal grain Y, utilize indication device that the border crystal grain Y of different boundary direction is indicated, this step can be utilized computing machine to carry out computing and indicate.Shown in Fig. 5 a-Fig. 5 d, Fig. 5 a is that two relative groups, Fig. 5 b were that two relative groups, Fig. 5 c were that being divided into border crystal grain Y upper right is to be divided into upper left border crystal grain Y and two the relative groups in bottom right with two the relative groups in lower-left, Fig. 5 d about border crystal grain Y was divided into about border crystal grain Y was divided into; Each border crystal grain can belong to a plurality of different groups.Then use a comparison means part or all of relative group to be carried out the comparison of error rate, when the difference of error rate arrives a preset value, send a signal, alarming device is given in this signal transmission, alarming device can show to have the situation of ground map migration in order to remind operating personnel with graphical information.
In sum, the invention provides a kind of method of testing and system of semiconductor element, the method can be used for judging the phenomenon whether the ground map migration is arranged in the test process of semiconductor element, can judge all semiconductor elements of testing, and need not increase the manpower burden.When system judges the phenomenon that has the ground map migration, can further send signal, the alert inspection plays measuring point.
Apparently, according to the description among the top embodiment, the present invention has many corrections and difference.Therefore need be understood in the scope of its additional claim item, except above-mentioned detailed description, the present invention can also implement widely in other embodiments.Above-mentioned is preferred embodiment of the present invention only, is not in order to limit claim of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or modification, all should be included in the following claim.
Claims (10)
1, a kind of method of testing of semiconductor element, the feature of this method of testing comprises:
At least one semiconductor element is provided, and this semiconductor element comprises a plurality of unit;
Test those unit on this semiconductor element;
Defining the boundary element of this semiconductor element, is that the test result according to this semiconductor element defines those boundary elements;
Selecting a plurality of boundary elements is the target unit; And
Carry out one and relatively judge, when the number of errors of those target unit reaches a preset value, send a signal.
2, method of testing as claimed in claim 1 is characterized in that, those unit are crystal grain.
3, method of testing as claimed in claim 1 is characterized in that, this target unit comprises all boundary elements.
4, method of testing as claimed in claim 1 is characterized in that, this target unit comprises the segment boundary unit.
5, a kind of method of testing of semiconductor element, the feature of this method of testing comprises:
At least one semiconductor element is provided, and this semiconductor element comprises a plurality of unit, and those unit have location mode separately;
Test those unit on this semiconductor element;
Defining the boundary element of this semiconductor element, is that the test result according to this semiconductor element defines those boundary elements;
Carry out a sort program, those boundary elements are categorized as a plurality of boundary element group; And
Carry out one and relatively judge, when at least one location mode of at least one boundary element group arrives a preset value, send a signal.
6, method of testing as claimed in claim 5 is characterized in that, according to the boundary element position those boundary elements is categorized as a plurality of boundary element group.
7, a kind of method of testing of semiconductor element, the feature of this method of testing comprises:
At least one semiconductor element is provided, and this semiconductor element comprises a plurality of unit;
Test those unit on this semiconductor element;
Defining the boundary element of this semiconductor element, is that test result according to this semiconductor element defines at least one side not have the unit of adjacent cells be boundary element;
Indicating this boundary element, is to indicate this boundary element with at least one bearing mark;
Carry out a sort program, those boundary elements are categorized as a plurality of boundary element group according to this direction; And
Carry out one and relatively judge, when the wrong proportional difference of the boundary element with relative direction arrives a preset value, send a signal.
8, a kind of test macro of semiconductor element, the feature of this test macro comprises:
One proving installation, in order to the measuring semiconductor element, wherein this semiconductor element comprises a plurality of unit;
One definition device is at least one boundary element that defines this semiconductor element according to the test result of this proving installation;
One selecting arrangement is the target unit in order to select those boundary elements; And
One arithmetic unit when the number of errors of those target unit reaches a preset value, sends a signal.
9, a kind of test macro of semiconductor element, the feature of this test macro comprises:
One proving installation, in order to the test semiconductor element, and this semiconductor element comprises a plurality of unit, and those unit have location mode separately;
One definition device is at least one boundary element that defines this semiconductor element according to the test result of surveying this proving installation
One sorter is in order to be categorized as those boundary elements a plurality of boundary element group; And
One arithmetic unit when the quantity of at least one location mode of at least one boundary element group arrives a preset value, sends a signal.
10, a kind of test macro of semiconductor element, the feature of this test macro comprises:
One proving installation, in order to the measuring semiconductor element, wherein this semiconductor element comprises a plurality of unit;
One definition device is according to test result, and the unit that definition has at least one side and do not have adjacent cells is a boundary element;
One indication device is used to the direction that this boundary element indicates at least one no adjacent cells;
One sorter is categorized as a plurality of boundary element group according to this direction with described boundary element; And
One comparison means when the wrong proportional difference of the boundary element with relative direction arrives a preset value, sends a signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810003873 CN101493494B (en) | 2008-01-24 | 2008-01-24 | Semiconductor element test method and system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200810003873 CN101493494B (en) | 2008-01-24 | 2008-01-24 | Semiconductor element test method and system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101493494A true CN101493494A (en) | 2009-07-29 |
| CN101493494B CN101493494B (en) | 2011-09-21 |
Family
ID=40924191
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200810003873 Active CN101493494B (en) | 2008-01-24 | 2008-01-24 | Semiconductor element test method and system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101493494B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102236070A (en) * | 2010-04-28 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Semiconductor test system and method |
| CN104576477A (en) * | 2014-12-10 | 2015-04-29 | 南通富士通微电子股份有限公司 | Wafer structure and chip picking method thereof |
| CN106483444A (en) * | 2015-08-31 | 2017-03-08 | 北京确安科技股份有限公司 | The method preventing wafer Map figure displacement using test program |
| CN112683210A (en) * | 2020-12-28 | 2021-04-20 | 上海利扬创芯片测试有限公司 | MAP graph offset detection method for wafer test |
-
2008
- 2008-01-24 CN CN 200810003873 patent/CN101493494B/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102236070A (en) * | 2010-04-28 | 2011-11-09 | 台湾积体电路制造股份有限公司 | Semiconductor test system and method |
| CN104576477A (en) * | 2014-12-10 | 2015-04-29 | 南通富士通微电子股份有限公司 | Wafer structure and chip picking method thereof |
| CN106483444A (en) * | 2015-08-31 | 2017-03-08 | 北京确安科技股份有限公司 | The method preventing wafer Map figure displacement using test program |
| CN112683210A (en) * | 2020-12-28 | 2021-04-20 | 上海利扬创芯片测试有限公司 | MAP graph offset detection method for wafer test |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101493494B (en) | 2011-09-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101785009B (en) | Computer-implemented methods for determining if actual defects are potentially systematic defects or potentially random defects | |
| US8372663B2 (en) | Good chip classifying method on wafer, and chip quality judging method, marking mechanism, and manufacturing method of semiconductor device using the good chip classifying method | |
| CN108919083A (en) | A method of improving Serdes IP wafer test efficiency | |
| CN101689521B (en) | Method and apparatus for monitoring vias in a semiconductor fab | |
| KR102239051B1 (en) | Inspection system and failure analysis and prediction method of inspection system | |
| CN104916559B (en) | The position failure method for detecting of binding entity coordinate | |
| US8054097B2 (en) | Method and system for automatically managing probe mark shifts | |
| CN101493494B (en) | Semiconductor element test method and system | |
| WO2022028102A1 (en) | Testing method and testing system | |
| KR102305872B1 (en) | Inspection system, wafer map indicator, wafer map display method, and computer program stored in a recording medium | |
| JP6122965B2 (en) | Inspection system | |
| US7649370B2 (en) | Evaluation method of probe mark of probe needle of probe card using imaginary electrode pad and designated determination frame | |
| CN107038697A (en) | Method and system for diagnosing semiconductor crystal wafer | |
| CN102101112B (en) | Light emitting diode wafer sorting method | |
| TW442880B (en) | Method for automatically classifying the wafer with failure mode | |
| CN108508637A (en) | A kind of detection method of display panel, device and automated optical detection equipment | |
| CN102435928B (en) | Wafer tester and the crystal round test approach of correspondence | |
| CN105203941B (en) | The method of inspection of wafer sort special pattern and probe card defect | |
| TWI472778B (en) | System - level IC test machine automatic retest method and the test machine | |
| CN104035015A (en) | Method for testing components and measuring arrangement | |
| CN101349723A (en) | Semiconductor test management system | |
| JP2005109056A (en) | Inspection device for semiconductor device | |
| KR20100109399A (en) | Setting method of contact parameter and computer readable recording medium having recorded setting program of contact parameter thereon | |
| CN104952750B (en) | The early stage detecting system and method for a kind of silicon chip electrical testing | |
| CN105866652A (en) | Automatic wafer calibration method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |